![Page 1: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/1.jpg)
Semester design review A TEST VEHICLE FOR RESEARCH ON THERMAL MANAGEMENT FOR INTEGRATED CIRCUITSKarl Peterson , Emmanuel Owusu, and Joshua Ellis
12/8/2009Iowa State UniversityEE491 - Senior Design I
![Page 2: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/2.jpg)
Our project is special…
International collaboration
Product conceptualization & specification in addition to design
Integrated circuit (IC) rather than system design
Research-orientated objectives
![Page 3: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/3.jpg)
Problem Statement
Design an integrated circuit (IC) for testing activities related to Iowa State University research activities in the area of thermal measurement and management for high-performance chips
Research in this area is being conducted by Dr. Randy Geiger and Dr. Degang Chen and members of their research group
![Page 4: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/4.jpg)
Problem Statement
Experimental activities related to this research have not been specifically planned
Part of our job has been to anticipate the type of tests for which the IC might be used
Flexibility and configurability are key features of the solution we have proposed
In preparation for the design, we imagined possible tests scenarios in detail and discussed them with the research team
![Page 5: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/5.jpg)
Types of IC testing activities
1. Evaluation of existing or novel analog temperature sensing circuits
2. Study of failure mechanisms affecting the long-term reliability of high-performance chips
3. Development of dynamic thermal management strategies taking advantage of the products of items (1) and (2)
![Page 6: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/6.jpg)
Solution approach
Flexibility can be achieved by realizing complex testing functionality on a programmable external controller
The IC itself allows test measurements to be taken and experimental conditions to be set while the controller manages these operations according to the specific test being conducted
![Page 7: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/7.jpg)
Top-level block diagram
![Page 8: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/8.jpg)
Analog test unit - subcircuits
![Page 9: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/9.jpg)
Digital functionality
![Page 10: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/10.jpg)
Design approach
‘Divide-and-conquer’ Top-down design
methodology Levels of design
Behavioral (Verilog, Verilog-A) Transistor level (schematic) Layout (mask description)
All descriptions (and documentation) are organized in Cadence design environment
Shared library
![Page 11: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/11.jpg)
Schedule
Based around January 20th submission deadline for MOSIS educational program
Very aggressive!
![Page 12: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/12.jpg)
Resources
Design & fabrication are separated in modern integrated circuit operations
Design itself is really a software task, resources include: Software tools (Cadence front-to-back
tool-set, ModelSim, etc.) Engineering labor
![Page 13: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/13.jpg)
Resources - labour
Team Member
Hours Hourly Rate Total Cost
Emmanuel 600 $30 $18,000
Josh 400 $30 $12,000
Karl 600 $30 $18,000
TOTAL $48,000
Table 7 - Labor costs for team members (September 2009 - April 2010)
![Page 14: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/14.jpg)
Risks & risk mitigation
Aggressive schedule, tight deadline Risk of not meeting deadline In this case, our product cannot be used
for research or its use may be delayed Near-impossibility of modification
after fabrication Statistical variations in the fabrication
process Oversights in verification
![Page 15: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/15.jpg)
Thank you!
Any questions? Details about sub-blocks?
![Page 16: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/16.jpg)
BACKUP SLIDES
![Page 17: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/17.jpg)
CMOS Temperature sensors Research centers
around compact, low power designs
Most temperature sensors in this category are based off of a view basic architectures
Many details of their performance and operation on not well understood!
VDD
VO1(T)
VO2(T)
M1 M2
M3
M5 M4
V3
![Page 18: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/18.jpg)
ADC – Sigma-delta modulator
![Page 19: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/19.jpg)
Test interconnect
Maximum current-density section(also uniform current density and linear)
![Page 20: 12/8/2009 Iowa State University EE491 - Senior Design I](https://reader036.vdocument.in/reader036/viewer/2022062422/56813336550346895d9a333b/html5/thumbnails/20.jpg)
Current DAC – Basic architecture
(to test interconnect)
D<0> D<1> D<2> D<3> ...D<7>
(W/L) 2(W/L) 4(W/L) 8(W/L)