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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
2014-1-21
John Lazzaro(not a prof - “John” is always OK)
CS 152Computer Architecture and Engineering
www-inst.eecs.berkeley.edu/~cs152/
TA: Eric Love
Lecture 1 – Single Cycle Design
Play:
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Today’s lecture plan ...
Short Break.
Single-cycle processor design.
Preliminaries ... prep for Thursday.
Class Outline.
What we’ll be doing this semester.
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NvidiaTegra K1 Tech Talk
5:30 PMthis
Thursday in the Woz.
Tegra K1 remixes theKepler GPU
architecture for lowpower
SOCs.
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NvidiaTegra K1
This class prepares you to be on a team
like the one at
Nvidia that designed this chip.
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NvidiaTegra K1
This is true even if
your goal is to be in the group that
designs circuits ... ... or writes software ...
for the chip.
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Lecture topics
GPU architecture:Apr 15/17.
Array of 192 CUDA cores
in the Kepler GPUDynamic
scheduling:Apr 1/3, 8/10.
ARM A15 CPU Cores (4+1)
Hierarchical Memory System
Memory System:(February)
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And other topics What do we get to do?
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Timeline
Lab 1: Pipelines:
Lab 3: Dynamically-Scheduled CPU Design:
For 9 weeks, lectures and labs only.
Lab 2: Caches:
Midterm March 18:
Midterm II May 1:
Complete HW1 and take Midterm 1
Complete HW2 and take Midterm 2
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About the labs Rocket, a RISC-V (“risk five”) chip project
Professor Krste Asanovic directs ASPIRE
(microprocessor design research
project).
RISC-V: a new instruction set architecture (ISA)
CS 152 uses ASPIRE software tools and
CPU designs. ASPIRE graduate
students take turns with TA duties.
Extensive software support: gcc port, disassemblers, etc.Chisel: Professor Bachrach’s hardware description language
Labs will use Chisel simulators of RISC-V CPU designs
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Open-source ... on the web ... Warning: It’s tricky to compile ...
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Each lab has two parts
Directed portion
Open-ended portion
Teaches you how to use the tools.
Helps you understand the material.
Not doing well puts you in ‘C’ grade territory.
Define a project and work on it for several weeks.“High bar” for an ‘A’ grade (about 10% of class).“Solid, competent work” gets you a ‘B’ grade.
Not ‘team’ labs - you
work alone.
Falls out of EECS 2.7-3.1 upper-division GPA guidelines.
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About exams:Two mid-terms and no final.
Mid-term start time TBD
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About homeworks:
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Discussion sections
Focused on labs.
What constitutes ‘cheating’ on labs?
TA: Eric Love (ASPIRE graduate student).
Essential for doing well in the labs.
Go to the section you can make.
John does Q&A for lecture materials, midterms, hw.
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And more generally ...
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Required text ... 5th edition only
See class website for readings for each lecture ...
On reserve in library.
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Recommended text ...
Any edition is fine ... whatever you used for 61C.
On reserve in library.
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Administriva, Part I
Piazza is our all-to-all communication media.Send John email if he hasn’t contacted you about it.
Tools run on EECS instructional machines.Get the account form from Eric in discussion.
Laptop/tablet/smartphone in class.
Fine for note taking and class-related activities.Every lecture will have a short break in the middle. Please wait till the break for heavy-duty multitasking.
Class website is our archival media.Lecture slides, labs, due dates ... add ‘/sp14’ to URL.
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Administriva Rain Checks
Course gradingBreakdown between mid-terms and labs, more details on how we will grade the labs.
Office hours
For Eric and John.
Deadlines policies.Our late policies for labs, and procedures if you can’t make it to one of the mid-terms.
Wait list.We hope we can let everyone in, but we don’t know for sure yet. If you are planning to drop, email John.
Expect updates soon on the following items:
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Break
Play:
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Instruction Set Architecture
The labs will use the RISC-V ISA ...
Lectures examples
will mostly use the
MIPS ISA.
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
New successful instruction sets are rare
instruction set
software
hardware
Implementors suffer with original sins of ISAs, to support the installed base
of software.
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Instruction Sets: A Thin Interface
Instruction Set Architecture
I/O systemProcessor
Digital DesignCircuit Design
Datapath & Control
Transistors
MemoryHardware
CompilerOperating
System(Mac OS X)
Application (iTunes)
Software Assembler
Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10
In Hexadecimal: 012A4020000000 01001 01010 01000 00000 100000Binary:
6 bits 5 bits 5 bits 5 bits 5 bits 6 bitsFieldsize:
opcode rs rt rd functshamtBitfield:
“R-Format”
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Hardware implements semantics ...
InstructionFetch
InstructionDecode
OperandFetch
Execute
ResultStore
NextInstruction
Fetch next inst from memory:012A4020
opcode rs rt rd functshamtDecode fields to get : ADD $8 $9 $10
“Retrieve” register values: $9 $10
Add $9 to $10
Place this sum in $8
Prepare to fetch instruction that follows the ADD in the program.
Syntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
ADD syntax &semantics, as seen inthe MIPS ISA document.
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Memory Instructions: LW $1,32($2)
InstructionFetch
InstructionDecode
OperandFetch
Execute
ResultStore
NextInstruction
Fetch the load inst from memory
“Retrieve” register value: $2
Compute memory address: 32 + $2
Load memory address contents into: $1
Prepare to fetch instr that follows the LW in the program. Depending on load semantics, new $1 is visible to that instr, or not until the following instr (”delayed loads”).
Decode fields to get : LW $1, 32($2)
opcode rs rt offset “I-Format”
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
LW syntax &semantics, as seen inthe MIPS ISA document.
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Branch Instructions: BEQ $1,$2,25
InstructionFetch
InstructionDecode
OperandFetch
Execute
ResultStore
NextInstruction
Fetch branch inst from memory
“Retrieve” register values: $1, $2
Compute if we take branch: $1 == $2 ?
Decode fields to get: BEQ $1, $2, 25
opcode rs rt offset “I-Format”
ALWAYS prepare to fetch instr that follows the BEQ in the program (”delayed branch”). IF we take branch, the instr we fetch AFTER that instruction is PC + 4 + 100.
PC == “Program Counter”
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
BEQ syntax &semantics, as seen inthe MIPS ISA document.
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
define: The Architect’s Contract
To the program, it appears that instructions execute in the correct order defined by the ISA.
What the machine actually does is up to the hardware designers, as long as the contract is kept.
As each instruction completes, themachine state (regs, mem) appears to the program to obey the ISA.
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Single Cycle CPU Design
Preliminaries ...
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Single cycle data paths: Assumptions
Processor uses synchronous logicdesign (a “clock”).
f T
1 MHz 1 μs
10 MHz 100 ns
100 MHz 10 ns
1 GHz 1 ns
All state elements act like positive edge-triggered flip flops.
D Q
clk
Reset ?
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Review: Edge-Triggered D Flip Flops
D Q
CLK
Value of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.
D
Q
This abstraction is sufficient for the 2014 CS 152!
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UC Regents Fall 2013 © UCBCS 250 L3: Timing
If you are a circuit designer ...
D QA flip-flop “samples” right before the edge, and then “holds” value.
Sampling circuit
Holds value
16 Transistors: Makes an SRAM look compact!
What do we get for the 10 extra
transistors?
Clocked logic semantics.
Not required for 2014 CS 152 ...
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
If you are a CS 150 veteran ...
module ff(D, Q, CLK);
input D, CLK;output Q;reg Q;
always @ (posedge CLK) Q <= D;
endmodule
D Q
CLK
Value of D is sampled on positive clock edge.Q outputs sampled value for rest of cycle.
Not required for 2014 CS 152 ...
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
define: Single-cycle datapath
All instructions execute in a single cycle of the clock (positive edge to
positive edge)
Advantage: a great way to learn CPUs.
Drawbacks: unrealistic hardware
assumptions,slow clock period
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UC Regents Spring 2014 © UCBCS 152: Single-Cycle Design
Thursday:
Complete single-cycle ... and maybe get to other listed topics.