2/2/07 EECS150 Lab Lecture #3 1
Verilog Synthesis & FSMs
EECS150 Spring 2007 – Lab Lecture #3
Brent MochizukiGreg Gibeling
2/2/07 EECS150 Lab Lecture #3 2
Today Designing Digital Logic Efficient Hardware Design HDL Simulation Blocking vs. Non-Blocking Administrative Info Lab #3: The Combo Lock FSMs in Verilog
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Designing Digital Logic (1) High Level Design
Top-Down Design Different from testing!
Implementing the Design Follow the flow of data Start with Inputs Determine State Generate Outputs
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Designing Digital Logic (2) Start with Inputs
What are they? Possible Values and Don’t Cares Timing
Process Them Raw inputs are often not what you need
Might need delay/timing change Might look for a specific value/range
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Designing Digital Logic (3) Determine State
What does the module need to remember?
Has it seen a particular input? How many cycles have passed?
Design Memory for State Generalized FSM Standard D Register Counter Shift Register
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Designing Digital Logic (4) Generate Outputs
What are they? Possible Values Timing
Create the outputs Don’t set them, they’re not variables Compute them from state (and inputs)
Learn to think in Boolean equations assign is helpful
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Efficient Hardware Design (1)
C
a
B
1
A
01
Z
aA01
aux
Z
B Calways @ (*) begin
if (a) aux =B;else aux = C;Z = A + aux;
end
always @ (*) beginif (a) Z = A + B;else Z = A + C;
end
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Efficient Hardware Design (2)
B
Z
A
<<
A
Z
n+1 bit adder
assign B = 3;assign Z = A * B;
assign Z = A + (2 * A);
assign Z = A + (A << 1);
assign Z = A + {A, 1’b0};
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Efficient Hardware Design (3)
aux
A[n-1:1]
Z
n bit adder
A
A[0]
assign aux = A + {1’b0, A[n-1:1]};assign Z = {aux, A[0]};
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HDL Simulation (1) Software Based Simulation
Fast, simple and accurate Allows for simulation at any precision Easy to see any signal - perfect Visibility
Drawbacks Simulator Dependant Deadlocks are Possible!
Simulation != Synthesis
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HDL Simulation (2) Implications
Verilog is not executed! Things don’t necessarily happen in order
Verilog is SIMULATED
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Blocking vs. Non-Blocking (1)
always @ (a) beginb = a;c = b;
end
always @ (posedge Clock) beginb <= a;c <= b;
end
C = B = A
B = AC = Old B
Verilog Fragment Result
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Blocking vs. Non-Blocking (2) Use Non-Blocking for FlipFlop Inference posedge/negedge require Non-Blocking Else simulation and synthesis wont match
Use #1 to show causality
always @ (posedge Clock) beginb <= #1 a;c <= #1 b;
end
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Administrative Info Don’t expect to be checked off during any lab times other than your own You should get checked off during your lab or during your lab TA’s office hours
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Administrative Info (2) Partners - 1 week warning
You MUST have one for Lab4 and later…
Try to keep the same one for the project
You must have one in your lab section If you do not have a partner:
Find one now!! Post to the newsgroup E-mail Jeff
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Lab #3: The Combo Lock (1)
Used to control entry to a locked room2bit, 2 digit combo (By Default 11, 01)Set code to 11, Press EnterSet code to 01, Press EnterLock Opens (Open = 1)
Lab4Top(Lab4Lock)
0101
Lab4CompareOpen
Error
Prog1
Prog2
ResetCombo
Reset
Enter
Code[0]Code[1]
DIPSwitches
ButtonsOutputs
Your Verilog
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Lab #3: The Combo Lock (2)Signal Width Dir DescriptionCode 2 I Code from the dipswitchesEnter 1 I Enter button (examine the code)ResetCombo 1 I Reset to the default
combinationClock 1 I System ClockReset 1 I System Reset, doesn’t affect
the comboOpen 1 O Indicates the lock is openError 1 O Indicates a bad combinationProg1 1 O Reprogramming the first digitProg2 1 O Reprogramming the second digitLED 8 O Use these for debugging
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Lab #3: The Combo Lock (3) Example 1:
1: Press ResetCombo, Combo: 2’b11, 2’b01 2: Set 2’b11, Press Enter 3: Set 2’b01, Press Enter, LEDs: “OPEN” 4: Press Enter, LEDs: “Prog1” 5: Set 2’b00, Press Enter, LEDs: “Prog2” 6: Set 2’b10, Press Enter, LEDs: “OPEN” 7: Combo: 2’b00, 2’b10
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Lab #3: The Combo Lock (4) Example 2:
1: Press ResetCombo, Combo: 2’b11, 2’b01
2: Set 2’b01, Press Enter 3: Set 2’b01, Press Enter, LEDs: “Error”
Why doesn’t “Error” show until step 3?
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Lab #3: The Combo Lock (5)
Init
OK1 BAD1
OK2[Open]
Prog1[Prog1]
Prog2[Prog2]
BAD2[Error]
Code 1 &Enter
~Code1 &Enter
Code 2 & Enter
Enter
Enter
Enter
~Code2 &Enter
Enter
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Lab #3: The Combo Lock (6)
Code 1Reg
==
Code 2Reg
==
Lab4Compare
Decode 2Decode 1
CodeEnter
Prog1/Prog2
In it
OK 1 BAD 1
OK 2[Open]
Prog1[Prog1]
Prog2[Prog2]
BAD 2[Error]
Code1 &Enter
~Code1 &Enter
Code2 & Enter
Enter
Enter
Enter
~Code2 &Enter
Enter
Open
Error
Prog 1
Prog 2
Outputs
Code
Enter
Enter
Prog 1
Prog 2
Decode 1 Decode 2
0101Code [0]Code [1]
DIPSwitches
Enter
Lab4Lock
Lab4Top
ResetCombo
Reset
ResetCombo
2b
2b 2b
2b2b
2b 2b
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Lab #3: The Combo Lock (7) Debugging with LEDs
A powerful way to debug Easy to understand Lower overhead than other debugging tools
A great way to see NextState/CurrentState
Drawbacks Slow, can’t see fast events No timing information, no waveform Limited number
Dipswitches!
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FSMs in Verilog (1) Mealy Machines
Output based on input and current state
Can have major timing problems
Moore Machines Output based on current state
Easier to work with Slightly harder to build
Mealy Machine
Moore Machine
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FSMs in Verilog (2) Two or Three always blocks
1st: CurrentState Register Clocked Handles Reset
2nd: Generates NextState (+ Outputs in Mealy)
Uses CurrentState and Inputs Combinational
3rd: Generates Outputs (Optional) Uses CurrentState only (for Moore Machines) Might be replaced with a few assigns
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FSMs in Verilog (3)
always @ (posedge Clock) beginif (Reset) CurrentState <= STATE_Idle;else CurrentState <=
NextState;end
module MyFSM(In, Out, Clock, Reset);input In, Clock, Reset;output Out;
parameter STATE_Idle = 1’b0,STATE_Run = 1’b1,STATE_X = 1’bx;
reg CurrentState, NextState, Out;
…
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FSMs in Verilog (4)
// The case block goes here// Its on the next slide…
endendmodule
…always @ (CurrentState or In) begin
NextState = CurrentState;Out = 1’b0;
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FSMs in Verilog (5)case (CurrentState)
STATE_Idle: beginif (In) NextState = STATE_Run;Out = 1’b0;
endSTATE_Run: begin
if (In) NextState = STATE_Idle;Out = 1’b1;
enddefault: begin
NextState = STATE_X;Out = 1’bX;
endendcase