Download - 2.CMOS Transistor Theory
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Introduction
CMOS VLSI Design
2.CMOS Transistor Theory
Fu yuzhuo
School of microelectronics,SJTU
omar fadhil,Baghdad
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outline
• PN junction principle
• CMOS transistor introduction
• Ideal I-V characteristics under static
conditions
• Dynamic Characteristics
• Non-ideal I-V effects
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• PN junction diffusion
• P-type hole concentration>>N-type hole concentration
• N-type electron concentration>>P-type electron
concentration
• Diffusion result
• Build up space-charge region(depletion)
• Stronger diffusion current, wider space-charge region
• Drift result
• Opposite to the diffusion current
• Resulting in a zero net flow
Diffusion&Drift activity
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Depletion Region
http://en.wikipedia.org/wiki/P–n_junction4/59
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PN junction Energy Band
mV600≈)n
NNln(0.026=)
n
NNln(
q
kT=Φ 2
i
AD
2
i
AD
0
势垒区
Example an abrupt junction has doping densities of NA=1015 atoms/cm3,
and ND=1016 atoms/cm3, calculate the built-in potential at 300K, ni is the
intrinsic carrier concentration in a pure sample of semi and equals
approximately 1.5X1010 atoms/cm3
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Forward-bias Mode
• Applied potential lowers the potential barrier
• Diffusion current dominates the drift component
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Reverse-bias mode
• Potential barrier is raised
• Drift current becomes dominant
• The number of minority carriers in the
neutral regions is very small, so drift
current component can almost be ignored
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Pn-juntion outline
• PN junction analysis
• PN junction current
• PN junction capacitance
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Minority carrier concentration in the neutral
regions near the pn-junction under forward-
bias conditions
Diode static behavior
Minority carrier concentration
is supported by p-zone
majority carrier concentration
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Diode static behavior
Minority carrier concentration in the neutral regions
near the pn-junction under reverse-bias conditions
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How to calculate diffusion
current?
1)(e TD0 /ΦV
2
WW
pDqAI
n
n
pDDp
1)(e TD0 /ΦV
1
WW
nDqAI
p
p
nDDn
1)(e
1)(e)(
TD
TD00
/ΦV
/ΦV
21
S
n
n
p
p
p
nDDDD
I
WW
pD
WW
nDqAIII
np
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Diode Current
T = kT/q = 26mV at 300K
IS is the saturation current of the diode
ID = IS (eVD /nVT 1)=IS (e
0.1/1*0.026 1)=48.23IS
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Models for Manual Analysis
VD
ID = IS(eVD/T – 1)+
–
VD
+
–
+
–VDon
ID
(a) Ideal diode model (b) First-order diode model
Example 3.2
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PN junction outline
• PN junction analysis
• PN junction current
• PN junction capacitance
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Dynamic behavior of pn-junction
Junction capacitance/depletion capacitance -Cj
Diffusion capacitance/dope capacitance -Cd
dV
dQC
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Junction capacitance
P N
+ -
+-
• The boundary of PN-junction could accumulatecharge when bias voltage was changed, whichshow capacitance characteristic
• When forward voltage improved,more chargespass,just like these charges are saved
• When forward voltage decreased, less chargespass, just like these charges are leaved
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Junction capacitance
D
DA
DAsiDj V
NN
NNqAQ
0Φ2
DA
DAsiDj
NN
NNqAC
0Φ20
D
DA
DAsij V
NN
NN
qWWW
012 Φ
2
D
DA
DA
si
j VNN
NNqE
0Φ
2
5.0
00
1
0Φ1Φ1
Φ2
00
D
j
D
j
D
DA
DAsiD
D
j
jV
C
V
CV
NN
NNqA
dV
dQC
Depletion-region charge
Maximum electric field
Depletion-region width
Zero-bias conditions
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Junction Capacitance
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Diffusion capacitance*
pp
D
n
D
p
nD
p
n
V
nnD
W
W
nnDp
ID
WI
D
WW
epWWqA
dxp)x(pqAQ
22
2
1
22
2
Φ
02
0
T
2
• Charge of diffusion region
nD
n
p
n ID
WQ
2
2
2n
20nn2n
2n
0n2nn
W-W
Wp-W)(Wpx+
W-W
p-)(Wp=(x)p
1)(e TD0 /ΦV
2
WW
pDqAI
n
n
pDDp
Diffusion capacitance is dominant when PN-juntion works under forward-
bias mode, because its current is supported by minority carrier
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Diffusion capacitance cont.
p
nTp
D
W
2
2
T
D
T
n
T
p
D
QQQI
np
T
DT
D
DT
D
Dd
I
dV
dI
dV
dQC
)e(IIDV
SD 1TΦ
n
p
TnD
W
2
2
Diffusion current
Transmit time
nD
n
p
n ID
WQ
2
2
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Junction and diffusion
capacitance• Forward-bias mode
• Diffusion cap. Is dominant
• small RC effect for ignoring Junction cap.
• Reverse-bias mode
• Minority carrier concentration is very small,
so its diffusion cap. Can be ignored
• Junction cap. Is dominant
• large RC effect
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PN junction switch model
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PN junction switching model
Vsrc
t = 0
V1
V2
VD
Rsrc
t = T
ID
Time
VD
ON OFF ON
Space charge
Excess charge
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Diode Model
mD
j
T
DTdiode
V
CIC
0Φ1
0
ID
RS
CD
+
-
VD
T
DT
D
DT
D
Dd
I
dV
dI
dV
dQC
More knowledage:
“Microelectronic Circuits:Analysis and
Design” Muhammad H.Rashid24/59
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outline
• PN junction principle
• CMOS transistor introduction
• Ideal I-V characteristics under static
conditions
• Dynamic Characteristics
• Nonideal I-V effects
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What is a Transistor?
VGS VT
Ron
S D
A Switch!
|VGS|
An MOS Transistor
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Terminal Voltages
• Mode of operation depends on Vgs, Vgd, Vds
• Vds = Vd – Vs = Vgs - Vgd
• Source and drain are symmetric diffusion terminals
• source is terminal at lower voltage
• Hence Vds 0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
• Cutoff
• Linear
• Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
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nMOS threshold voltage
• nMOS Cutoff
• No channel,Ids = 0
• Vt>Vgs>0
• depletion region(inversion) is formed below
the gate
• Vgs=Vt
• A strong inversion is built up, the potential at
the silicon surface reaches a critical value
• Further increases the gate voltage produce
no further changes in the depletion layer
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outline
• PN junction principle
• CMOS transistor introduction
• Ideal I-V characteristics under static conditions
• Velocity Saturation
• Dynamic Characteristics
• Nonideal I-V effects
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nMOS Linear
• Channel forms
• Current flows from d to s
• e- from s to d
• Ids increases with Vds
• Similar to linear resistor
+-
Vgs
> Vt
n+ n+
+-
Vgd
= Vgs
+-
Vgs
> Vt
n+ n+
+-
Vgs
> Vgd
> Vt
Vds
= 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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Cut-off
Weak inversion
Strong inversion
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Linear regime
Pinch off
Saturated state
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nMOS in linear area
])([)( Tgsxoi VxVVCxQ Charge per unit area:
WxQxvI inD )()(dx
dVxExv nnn )()(
WVxVVCdx
dVI TgsxonD ])([
DSV
Tgsxon
L
D WdVVxVVCdxI00
])([
s./vcm1800=μs,./vcm3800=μ 2
p
2
n
]2
V-)V-V[(V
L
W]=k
2
V-)V-V[(V
L
WC=μI
2
DSDSTgs
'
n
2
DSDSTgsxonD
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The Threshold Voltage
VT = VT0 + (|-2F + VSB| - |-2F|)where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the manufacturing process
Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.
VSB is the source-bulk voltage
F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is the thermal voltage; NA is the acceptor ion concentration; ni 1.5x1010 cm-3 at 300K
is the intrinsic carrier concentration in pure silicon)
= (2qsiNA)/Cox is the body-effect coefficient (impact of changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m)
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I-V character in resistive or linear region
Page 92
Linear dependence between Vds and ID
L
W
t
ε
L
WC
L
Wk
ox
oxnoxn
'n ===kn
ox
oxnoxnn
DSDSTGSn
DSDSTGSnD
tCk
VVVVk
VVVV
L
WkI
'
22'
2)(
2)(
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nMOS Saturation
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds
> Vgs
-Vt
p-type body
b
g
s d Ids
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I-V relation under Saturation
condition
• Vds=Vgs-VT
ox
ox
noxn
'
n t
εu=Cu=k
2
)(
2)(
22
TGSnVVV
DSDSTGSnD
VVk
VVVVkI
Tgsds
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I-V characteristic of saturation
])([)( Tgsxoi VxVVCxQ
WxQxvI inD )()(dx
dVxExv nnn )()(
WVxVVCdx
dVI TgsxonD ])([
TGS VV
Tgsxon
L
D WdVVxVVCdxI00
])([
Charge per unit area:
2TGS
'
nDsat V-V
L
W
2
k=I
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Current-Voltage Relations
Long-Channel Device
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS
(V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VTQuadraticRelationship
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Another method for giving I-V
Characteristics• In Linear region, Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?
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Channel Charge
• MOS structure looks like parallel plate capacitor while operating in
inversion
• Gate – oxide – channel
• Qchannel = CV
• C = Cg = ox WL/tox = CoxWL
• V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field between
source and drain
• v = E called mobility
• E = Vds/L
• Time for carrier to cross channel:
• t = L / v
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nMOS Linear I-V
• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross
DS
DS
TGS
DS
DS
TGSox
c
ds
)V2
VVk(V=
)V2
VV(V
L
WμC=
t
Q=I
--
--
L
w
t
εu=
L
wCu=
L
wk=k
ox
ox
noxn
'
nn
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nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
• When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
Ids=k(Vgs-Vt-Vdsat/2)Vdsat=k(Vgs-Vt)2/2
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summary
• Shockley 1st order transistor models
0 Vgs<Vt cutoff
• Ids= k(Vgs-Vt-Vdsat/2)Vdsat Vds<Vdsat linear
k(Vgs-Vt)2/2 Vds>Vdsat saturation
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outline
• PN junction principle
• CMOS transistor introduction
• Ideal I-V characteristics under static conditions
• Velocity Saturation
• Dynamic Characteristics
• Nonideal I-V effects
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Current-Voltage Relations
The Deep-Submicron Era
LinearRelationship
-4
VDS
(V)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Early Saturation
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Attention : velocity position
])([)( Tgsxoi VxVVCxQ Charge per unit area:
WxQxvI inD )()(dx
dVxExv nnn )()(
WVxVVCdx
dVI TgsxonD ])([
DSV
Tgsxon
L
D WdVVxVVCdxI00
])([
s./vcm1800=μs,./vcm3800=μ 2
p
2
n
)(2
)(2
DSATDSAT
DSATTGSoxnD VV
VVVL
WCI
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Velocity Saturation
csat
c
c
n
v
v
for
for 1
x (V/µm)xc
= 1.5
un
(m/s
)
usat
= 105
Constant mobility (slope = µ)
Constant velocity
The critical field depends upon the doping levels and
the vertical electrical field applied(1-5V/um)
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Velocity Saturation
)(2
)(
2)(
)(1
2
2
DSDS
DSTGSoxn
DSDSTGS
c
DS
oxnD
VV
VVVL
WC
VVVV
L
W
LV
CI
cLξV+1
1=κ(V)
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Velocity Saturation
)(2
)()(2
DSATDSAT
DSATTGSoxnDSATGToxsatD VV
VVVL
WCVVWCI
GTGTDSAT VVV )(
Current definition Assuming VGS is high enough
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Perspective
IDLong-channel device
Short-channel device
VDSVDSAT VGS - VT
VGS = VDD
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ID versus VGS
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VGS
(V)
I D(A
)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VGS
(V)
I D(A
)
quadratic
quadratic
linear
Long Channel Short Channel
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Another two assumptions
csat
c
c
n
v
v
for
for 1
L
V
V
VVV
c
GT
GT
GTGTDSAT
1
)(
csat
cn
v
v
for
for
n
SATcVDSAT
LvLV
GT
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VDSAT is nearly constant…
![Page 55: 2.CMOS Transistor Theory](https://reader031.vdocument.in/reader031/viewer/2022012505/617fef9cc4a8461fcf085e2b/html5/thumbnails/55.jpg)
Modify the velocity formula to be coherent with the
familiar long-channel equations
n
SATcDSAT
LvLV
2
2)(
)(2
)(
2
2
DSATTGSoxsat
DSATDSATTGSoxn
DSATDSAT
DSATTGSoxnD
VVVWCv
VVVV
L
WC
VV
VVVL
WCI
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ID versus VDS
-4
VDS
(V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10-4
VDS(V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
Long Channel Short Channel
Qua
dra
tic
depe
ndenc
e
Line
ar d
epen
denc
e
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A unified model for manual analysis
S D
G
B
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Simple Model versus SPICE
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5x 10
-4
VDS
(V)
I D(A
)
VelocitySaturated
Linear
Saturated
VDSAT=VGT
VDS=VDSAT
VDS=VGT
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A pMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0-1
-0.8
-0.6
-0.4
-0.2
0x 10
-4
VDS (V)
I D(A
)
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
VGS = -2.5V
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Assume all variables negative!
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Summary
• Strong Inversion VGS > VT
• Linear (Resistive) VDS < VDSAT
• Saturated (Constant Current) VDS VDSAT
• Weak Inversion (Sub-Threshold) VGS VT
• Exponential in VGS with linear IDS
dependence
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