700 MHz to 3000 MHz Dual Passive Receive Mixer with Integrated PLL and VCO
Data Sheet ADRF6612
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES RF frequency: 700 MHz to 3000 MHz, continuous LO input frequency: 200 MHz to 2700 MHz, high-side or low-
side injection IF range: 40 MHz to 500 MHz Power conversion gain of 9.0 dB Single sideband (SSB) noise figure of 11.3 dB Input IP3 of 30 dBm Input P1dB of 10.6 dBm Typical LO input drive of 0 dBm Single-ended, 50 Ω RF port Single-ended or balanced LO input port Serial port interface (SPI) control on all functions Exposed pad, 7 mm × 7 mm, 48-lead LFCSP
APPLICATIONS Multiband/multistandard cellular base station diversity
receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells
FUNCTIONAL BLOCK DIAGRAM
GND
LOO
UT+
VCO
VTU
NE
SPICONTROL
÷1 TO32
PLL REF BUFFERPFD/CP
FRACTIONAL DIVIDER
PLL3.3VLDO
VCOLDO
SPI2.5VLDO
DIV3.3VLDO
VCO
VCO
VCO
VCC10GND
GND
VCC1
EXTVCOIN+
EXTVCOIN–
DECL1DECL2DECL3DECL4DECL5
VCC9VCC8
RFBCT1RFIN1VCC7LDO2
RFIN2RFBCT2
VCC6VCC5VCC4
LOO
UT–
LDO
1
VCC
2
SDIO
SCLK C
S
IFO
UT2
+IF
OU
T2–
VCC
3D
NC
GN
D
VCC
12
LDO
4LD
O3
GN
D
CPO
UT
REF
IN
MU
XOU
T
IFO
UT+
IFO
UT–
VCC
11D
NC
GN
D
424347 37403839 414844454621
3
6
34
33
36
35
31
30
26
25
29
28
27
32
7
9
8
5
4
10
11
1214 15 16 17 18 19 22 23 20 21 2413
MU
X
1219
9-00
1
ADRF6612
Figure 1.
GENERAL DESCRIPTION The ADRF6612 is a dual radio frequency (RF) mixer and intermediate frequency (IF) amplifier with an integrated phase-locked loop (PLL) and voltage controlled oscillators (VCOs). The ADRF6612 uses revolutionary broadband square wave limiting local oscillator (LO) amplifiers to achieve an unprecedented RF bandwidth of 700 MHz to 3000 MHz. Unlike narrow-band sine wave LO amplifier solutions, the LO can be applied above or below the RF input over an extremely wide bandwidth. Energy storage elements are not utilized in the LO amplifier, thus dc current consumption also decreases with decreasing LO frequency.
The ADRF6612 utilizes highly linear, doubly balanced passive mixer cores with integrated RF and LO balancing circuits to allow single-ended operation. Integrated RF baluns allow optimal performance over the 700 MHz to 3000 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO to RF and LO to IF leakages, excellent RF to IF isolation, and excellent intermodulation performance over the full RF bandwidth.
The balanced mixer cores provide extremely high input linearity, allowing the device to be used in demanding
wideband applications where in band blocking signals may otherwise result in the degradation of dynamic range. Noise performance under blocking is comparable to narrow-band passive mixer designs. High linearity IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 9 dB, and can be matched to a wide range of output impedances.
The PLL architecture supports both integer-N and fractional-N operation and can generate the entire LO frequency range of 200 MHz to 2700 MHz using an external reference input frequency anywhere in the range of 12 MHz to 320 MHz. An external loop filter provides flexibility in trading off phase noise vs. acquisition time. To reduce fractional spurs in fractional-N mode, a sigma-delta (Σ-Δ) modulator controls the post-VCO programmable divider. The VCO consists of multiple VCO cores.
All features of the ADRF6612 are controlled via a 3-wire SPI resulting in optimum performance and minimum external components.
The ADRF6612 is fabricated using a BiCMOS, high performance IC process. The device is available in a 7 mm × 7 mm, 48-lead LFCSP package and operates over a −40°C to +85°C temperature range. An evaluation board is available.
ADRF6612 Data Sheet
Rev. A | Page 2 of 57
TABLE OF CONTENTS Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
RF Specifications .......................................................................... 3
Synthesizer/PLL Specifications ................................................... 4
VCO Specifications, Open-Loop ................................................ 7
Logic Input and Power Specifications ....................................... 8
Digital Logic Specifications ......................................................... 9
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Mixer, High Performance Mode ............................................... 13
Mixer, High Efficiency Mode .................................................... 22
Synthesizer ................................................................................... 23
Spurious Performance ............................................................... 29
Circuit Description......................................................................... 31
RF Subsystem .............................................................................. 31
External LO Generation ............................................................ 31
Internal LO Generation ............................................................. 31
Applications Information .............................................................. 35
Basic Connections Pin Description ............................................. 36
Mixer Optimization ....................................................................... 37
RF Input Balun Insertion Loss Optimization ......................... 37
IIP3 Optimization ...................................................................... 37
VGS Programming ..................................................................... 38
Low-Pass Filter Programming .................................................. 38
Register Summary .......................................................................... 40
Register Details ............................................................................... 41
Evaluation Board ............................................................................ 52
Outline Dimensions ....................................................................... 57
Ordering Guide .......................................................................... 57
REVISION HISTORY 5/2016—Rev. 0 to Rev. A Changes to Table 19 ........................................................................ 32 Changes to Address: 0x22, Reset: 0x000A, Name: VCO_CTRL1 Section and Table 34 ....................................................................... 45 Updated Outline Dimensions ....................................................... 57 Changes to Ordering Guide .......................................................... 57 12/2014—Revision 0: Initial Version
Data Sheet ADRF6612
Rev. A | Page 3 of 57
SPECIFICATIONS RF SPECIFICATIONS TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, frequency of the reference (fREF) = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RF balun (RFB) and low-pass filter (LPF) settings, unless otherwise noted.
Table 1. High Performance Mode Parameter Test Conditions/Comments Min Typ Max Unit
RF INTERFACE Return Loss Tunable to >20 dB broadband via serial port 17.9 dB Input Impedance 50 Ω RF Frequency Range (fRF) 700 3000 MHz
IF OUTPUT INTERFACE Output Impedance Differential impedance, f = 200 MHz 300||1.5 Ω||pF IF Frequency Range 40 500 MHz DC Bias Voltage1 Externally generated IFOUTx± V
EXTERNAL LO INPUT External LO Power Input −5 0 +5 dBm Return Loss −11 dB Input Impedance 50 Ω External VCO Input Frequency External VCO input supports divide by 1, 2, 4, 8, 16, and 32 250 5700 MHz LO Frequency Range Low-side or high-side LO, internally or externally
generated 250 2850 MHz
DYNAMIC PERFORMANCE Power Conversion Gain 4:1 IF port transformer and printed circuit board (PCB) loss
removed 9.0 dB
Voltage Conversion Gain ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω 15.0 dB SSB Noise Figure 11.3 dB IF Output Phase Noise Under Blocking 10 dBm blocker present 10 MHz above desired RF input, fRF =
1900 MHz, fBLOCK = 1910 MHz, fLO = 1697 MHz, IF = 203 MHz, IFBLOCKER = 213 MHz
−153 dBc/Hz
Input Third-Order Intercept (IIP3) fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each RF tone at −10 dBm
30 dBm
Input Second-Order Intercept (IIP2) fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each RF tone at −10 dBm
60 dBm
Input 1 dB Compression Point (P1dB) 10.6 dBm LO to IF Output Leakage Unfiltered IF output −35 dBm LO to RF Input Leakage −45 dBm RF to IF Output Isolation −22 dB IF/2 Spurious −10 dBm input power −72 dBc IF/3 Spurious −10 dBm input power −69 dBc
POWER INTERFACE VCC12, VCC7, VCC2, VCC1
Supply Voltage 3.55 3.7 3.85 V Quiescent Current 260 mA
VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10, VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−
Supply Voltage 3.55 5 5.25 V Quiescent Current 214 mA
LO OUTPUT (LOOUT+, LOOUT−) Frequency Range 200 2700 MHz Output Level Adjustable via SPI in four steps, in 50 Ω balanced load −5 +7 dBm Output Impedance Balanced 50 Ω
1 Supply voltage must be applied from the external circuit through choke inductors.
ADRF6612 Data Sheet
Rev. A | Page 4 of 57
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted.
Table 2. High Efficiency Mode Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE
Power Conversion Gain 4:1 IF port transformer and PCB loss removed 8.7 dB Voltage Conversion Gain ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω 14.7 dB SSB Noise Figure 10.7 dB Input Third-Order Intercept (IIP3) fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each
RF tone at −10 dBm 20.5 dBm
Input Second-Order Intercept (IIP2) fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each RF tone at −10 dBm
53 dBm
Input 1 dB Compression Point (P1dB) 8.2 dBm LO to IF Output Leakage Unfiltered IF output −45.0 dBm LO to RF Input Leakage −52.0 dBm RF to IF Output Isolation −22.8 dB IF/2 Spurious −10 dBm input power −58 dBc IF/3 Spurious −10 dBm input power −58 dBc
POWER INTERFACE VCC12, VCC7, VCC2, VCC1
Supply Voltage 3.55 3.7 3.85 V Quiescent Current 260 mA
VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC10, VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−
Supply Voltage 3.55 3.7 5.25 V Quiescent Current 210 mA
SYNTHESIZER/PLL SPECIFICATIONS High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF =122.88 MHz, fPFD = 1.536 MHz, fREF power = 4 dBm, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns, integer mode loop filter, unless otherwise noted.
Table 3. Integer Mode Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1 × LO
Frequency Range Internally generated LO 200 2700 MHz Figure of Merit (FOM)1 PREFIN = 6.5 dBm −223 dBc/Hz/Hz Phase and Frequency Detector (PFD)
Frequency (fPFD) 0.8 70 MHz
Reference Spurs fPFD = 1.536 MHz 1 × fPFD −105 dBc 4 × fPFD −105 dBc >4 × fPFD −90 dBc
CHARGE PUMP Pump Current Programmable to 250 µA, 500 µA, …, 8 mA 8 8.75 mA Output Compliance Range 0.7 2.5 V
REFERENCE CHARACTERISTICS REFIN, MUXOUT pins REFIN Input Frequency 12 320 MHz REFIN Input Capacitance 4 pF Reference Divider Value Programmable to 0.5, 1, 2, 3, …, 2047 0.5 2047 MUXOUT Output Level VOL (lock detect output selected) 0.25 V VOH (lock detect output selected) 2.7 V MUXOUT Duty Cycle Reference output selected 50 %
Data Sheet ADRF6612
Rev. A | Page 5 of 57
Parameter Test Conditions/Comments Min Typ Max Unit VCO_0
Phase Noise, Locked fLO = 5.1 GHz 1 kHz offset −87 dBc/Hz 50 kHz offset −94.9 dBc/Hz 100 kHz offset −103.3 dBc/Hz 1 MHz offset −132.9 dBc/Hz 10 MHz offset −154.1 dBc/Hz 40 MHz offset −155.2 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.87 °rms
VCO_1 Phase Noise, Locked fLO = 4.45 GHz 1 kHz offset −90 dBc/Hz 50 kHz offset −98.4 dBc/Hz 100 kHz offset −106.5 dBc/Hz 1 MHz offset −136.1 dBc/Hz 10 MHz offset −154.8 dBc/Hz 40 MHz offset −155.5 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.63 °rms
VCO_2 Phase Noise, Locked fLO = 3.8 GHz 1 kHz offset −90 dBc/Hz 50 kHz offset −98.1 dBc/Hz 100 kHz offset −109.8 dBc/Hz 1 MHz offset −137.1 dBc/Hz 10 MHz offset −155.7 dBc/Hz 40 MHz offset −156.2 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.61 °rms
VCO_3 Phase Noise, Locked fLO = 3.2 GHz 1 kHz offset −89 dBc/Hz 50 kHz offset −97.2 dBc/Hz 100 kHz offset −107 dBc/Hz 1 MHz offset −136.2 dBc/Hz 10 MHz offset −155.7 dBc/Hz 40 MHz offset −157.3 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.64 °rms
1 The FOM is computed as phase noise (dBc/Hz) − 10Log10(fPFD) − 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 122.88 MHz and fREF
power = 6.5 dBm with a 1.536 MHz fPFD. The FOM was computed at 50 kHz offset.
ADRF6612 Data Sheet
Rev. A | Page 6 of 57
High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF =122.88 MHz, fPFD = 30.72 MHz, fREF power = 4 dBm, CSCALE = 250 µA, bleed = 93.75 µA, ABLDLY = 0 ns, fractional mode loop filter, unless otherwise noted.
Table 4. Fractional Mode Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1 × LO
FOM1 PREFIN = 6.5 dBm 219 dBc/Hz/Hz REFERENCE CHARACTERISTICS REFIN, MUXOUT pins
VCO_0 Phase Noise, Locked fLO = 2.55 GHz 1 kHz offset −92.5 dBc/Hz 50 kHz offset −97.4 dBc/Hz 100 kHz offset −109.7 dBc/Hz 1 MHz offset −137.6 dBc/Hz 10 MHz offset −153.6 dBc/Hz 40 MHz offset −155.5 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.36 °rms
VCO_1 Phase Noise, Locked fLO = 2.22 GHz 1 kHz offset −93.6 dBc/Hz 50 kHz offset −101.8 dBc/Hz 100 kHz offset −112.5 dBc/Hz 1 MHz offset −140.5 dBc/Hz 10 MHz offset −154.3 dBc/Hz 40 MHz offset −155.3 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.32 °rms
VCO_2 fLO = 1.9 GHz Phase Noise, Locked 1 kHz offset −94.2 dBc/Hz 50 kHz offset −101.7 dBc/Hz 100 kHz offset −112.4 dBc/Hz 1 MHz offset −141.3 dBc/Hz 10 MHz offset −155.8 dBc/Hz 40 MHz offset −156.8 dBc/Hz 1 kHz to 40 MHz integration bandwidth 0.32 °rms Integrated Phase Noise
VCO_3 fLO = 1.6 GHz Phase Noise, Locked 1 kHz offset −93.1 dBc/Hz 50 kHz offset −99.8 dBc/Hz 100 kHz offset −110.9 dBc/Hz 1 MHz offset −140.2 dBc/Hz 10 MHz offset −155.7 dBc/Hz 40 MHz offset −157.2 dBc/Hz 1 kHz to 40 MHz integration bandwidth 0.33 °rms
1 The FOM is computed as phase noise (dBc/Hz) − 10Log10(fPFD) − 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 122.88 MHz and fREF
power = 6.5 dBm with a 30.72 MHz fPFD. The FOM was computed at 45 kHz offset.
Data Sheet ADRF6612
Rev. A | Page 7 of 57
VCO SPECIFICATIONS, OPEN-LOOP High performance mode, TA = 25°C, measured on LO output, unless otherwise noted.
Table 5. Parameter Test Conditions/Comments Min Typ Max Unit VCO_0 PHASE NOISE fVCO = 5.15 GHz 1 kHz offset −50 dBc/Hz 50 kHz offset −104.4 dBc/Hz 100 kHz offset −112.6 dBc/Hz 1 MHz offset −137.7 dBc/Hz 10 MHz offset −154 dBc/Hz 40 MHz offset −155.1 dBc/Hz VCO_1 PHASE NOISE fVCO = 4.3 GHz 1 kHz offset −54 dBc/Hz 50 kHz offset −106.1 dBc/Hz 100 kHz offset −115 dBc/Hz 1 MHz offset −138.9 dBc/Hz 10 MHz offset −155.8 dBc/Hz 40 MHz offset −155.2 dBc/Hz VCO_2 PHASE NOISE fVCO = 3.8 GHz 1 kHz offset −53.6 dBc/Hz 50 kHz offset −106.6 dBc/Hz 100 kHz offset −114.6 dBc/Hz 1 MHz offset −140.8 dBc/Hz 10 MHz offset −155.4 dBc/Hz 40 MHz offset −156.3 dBc/Hz VCO_3 PHASE NOISE fVCO = 3.2 GHz 1 kHz offset −48.5 dBc/Hz 50 kHz offset −106 dBc/Hz 100 kHz offset −115.3 dBc/Hz 1 MHz offset −140.2 dBc/Hz 10 MHz offset −157.7 dBc/Hz 40 MHz offset −156.3 dBc/Hz
ADRF6612 Data Sheet
Rev. A | Page 8 of 57
LOGIC INPUT AND POWER SPECIFICATIONS TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted.
Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS SCLK, SDIO, CS
Input High Voltage, VIH 1.4 3.3 V Input Low Voltage, VIL 0 0.7 V Input Current, IINH/IINL 0.1 µA
POWER SUPPLIES High Performance Mode
Voltage Range VCC3, VCC4, VCC5, VCC6, VCC8,
VCC9, VCC10, VCC11, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−
4.75 5 5.25 V
VCC12, VCC7, VCC2, VCC1 3.55 3.7 5.25 V Power Dissipation Internal LO mode (internal PLL)
External LO output enabled 2.7 W External LO output disabled 2.5 W
High Efficiency Mode Voltage Range
VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9, VCC10, VCC11,VCC12, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−
3.55 3.7 3.85 V
Power Dissipation Internal LO mode (internal PLL) External LO output enabled 2.0 W External LO output disabled 1.8 W
Data Sheet ADRF6612
Rev. A | Page 9 of 57
DIGITAL LOGIC SPECIFICATIONS
Table 7. Parameter Symbol Test Conditions/Comments Min Typ Max Units Input Voltage High VIH 1.4 V Input Voltage Low VIL 0.70 V Output Voltage High VOH IOH = −100 µA 2.3 V Output Voltage Low VOL IOL = 100 µA 0.2 V Serial Clock Period tCLK 38 ns Setup Time Between Data and Rising Edge of SCLK tDS 8 ns Hold Time Between Data and Rising Edge of SCLK tDH 8 ns Setup Time Between Falling Edge of CS and SCLK tS 10 ns
Hold Time Between Rising Edge of CS and SCLK tH 10 ns
Minimum Period for SCLK to Be in a Logic High State tHIGH 10 ns Minimum Period for SCLK to Be in a Logic Low State tLOW 10 ns Maximum Delay Between Falling Edge of SCLK and
Output Data Valid for a Read Operation tACCESS 231 ns
Maximum Delay Between CS Deactivation and SDIO Bus Return to High Impedance
tZ 5 ns
tS
tDS
tDH
tHIGH
tLOW
tCLK tH
DON'T CARE
DON'T CARE
A5 A4 A3 A2 A1 A0 D15 D14 D13 D3 D2 D1 D0 DON'T CARE
DON'T CARESCLK
SDIO R/W
tZ
tACCESS
A6
CS
1219
9-00
2
Figure 2. Setup and Hold Timing Measurements
ADRF6612 Data Sheet
Rev. A | Page 10 of 57
ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating Supply Voltage (VCC1, VCC2, VCC3,
VCC4, VCC5, VCC6, VCC7, VCC8, VCC9, VCC10, VCC11,VCC12, IFOUT1+, IFOUT1−, IFOUT2+, IFOUT2−)
−0.5 V to +5.5 V
Digital Input/Output (SCLK, SDIO, CS) −0.3 V to +3.6 V
RFINx 20 dBm EXTVCOIN+, EXTVCOIN− 13 dBm Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE θJC is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 9. Thermal Resistance Package Type θJC Unit 48-Lead LFCSP 1.62 °C/W
ESD CAUTION
Data Sheet ADRF6612
Rev. A | Page 11 of 57
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
123456789
101112
3536
34333231302928272625
ADRF6612TOP VIEW
(Not to Scale)
LOO
UT+
LOO
UT–
LDO
1VC
C2
SDIO
SCLK C
SVC
C3
DN
CIF
OU
T2+
IFO
UT2
–G
ND
GN
DC
POU
TVC
C12
LDO
4LD
O3
REF
INM
UXO
UT
VCC
11D
NC
IFO
UT1
+IF
OU
T1–
GN
D
GNDVCOVTUNE
GNDEXTVCOIN+EXTVCOIN–
GNDVCC1
DECL1DECL2DECL3DECL4DECL5
RFIN1VCC10VCC9VCC8VCC7LDO2VCC6VCC5VCC4RFIN2RFBCT2
RFBCT1
NOTES1. DNC = DO NOT CONNECT.2. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE WITH LOW THERMAL IMPEDANCE. 12
199-
003
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 GND Common Ground Connection for External Loop Filter. 2 VCOVTUNE Control Voltage for Internal VCO. 3, 6 GND Common Ground for External VCO. 4, 5 EXTVCOIN+, EXTVCOIN− Inputs from External VCO to Internal Divider. 7 VCC1 3.7 V VCO Supply. 8, 9 DECL1, DECL2 LDO Output Decouplers for VCO. 10, 11 DECL3, DECL4 External Decouplers for VCO Buffer. 12 DECL5 External Decoupler for VCO Circuitry. 13, 14 LOOUT+, LOOUT− Differential Outputs of Internally Generated LO. 15 LDO1 External Decoupling for Internal 2.5 V SPI Port LDO. 16 VCC2 3.7 V Supply for Programmable SPI Port. 17 SDIO Serial Data Input/Output for Programmable SPI Port. 18 SCLK Clock for Programmable SPI Port. 19 CS SPI Chip Select, Asserted Low.
20, 41 VCC3, VCC11 5 V Biases for Channel 1 and Channel 2 IF. 21, 40 DNC Do Not Connect. Do not connect this pin externally. 22, 23 IFOUT2+, IFOUT2− Channel 2 Differential IF Outputs. 24, 37 GND, GND Ground Connections for Channel 1 and Channel 2 IF Stage. 25 RFBCT2 Balun Center Tap Connection for Channel 2 RF Input. 26 RFIN2 Channel 2 RF Input. 27, 28, 29 VCC4, VCC5, VCC6 5 V Supplies for Mixer LO Amplifiers. 30 LDO2 External Decoupling for Internal 3.3 V PLL/Divider LDO. 31 VCC7 3.7 V Supply for Mixer LO Divider Chain. 32, 33, 34 VCC8, VCC9, VCC10 5 V Supplies for Mixer LO Amplifiers. 35 RFIN1 Channel 1 RF Input. 36 RFBCT1 Balun Center Tap Connection for Channel 1 RF Input. 38, 39 IFOUT1−, IFOUT1+ Channel 1 Differential IF Outputs. 42 MUXOUT Internal Multiplexer Output.
ADRF6612 Data Sheet
Rev. A | Page 12 of 57
Pin No. Mnemonic Description 43 REFIN Reference Input for Internal PLL (Single-Ended, CMOS). 44 LDO3 External Decoupling for Internal 2.5 V PLL LDO. 45 LDO4 External Decoupling for Internal 3.3 V PLL LDO. 46 VCC12 3.7 V Supply for Internal PLL. 47 CPOUT Charge Pump Output. 48 GND Common Ground for External Charge Pump. EPAD Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance.
Data Sheet ADRF6612
Rev. A | Page 13 of 57
TYPICAL PERFORMANCE CHARACTERISTICS MIXER, HIGH PERFORMANCE MODE TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. For integer mode: fPFD = 1.536 MHz, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns. For fractional mode: fPFD = 30.72 MHz, CSCALE = 250 µA, bleed = 93.75 µA, ABLDLY = 0.0 ns.
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
POW
ER D
ISSI
PATI
ON
(W)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
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Figure 4. Power Dissipation vs. RF Frequency over Three Temperatures
4.04.55.05.56.06.57.07.58.08.59.09.5
10.010.511.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
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5
Figure 5. Power Conversion Gain vs. RF Frequency over Three Temperatures,
IF Balun and Board Loss Removed
10121416182022242628303234363840
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
3 (d
Bm)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
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6
Figure 6. Input IP3 vs. RF Frequency over Three Temperatures
30
35
40
45
50
55
60
65
70
75
80
85
90
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
2 (d
Bm)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-00
7
Figure 7. Input IP2 vs. RF Frequency over Three Temperatures
5
7
9
11
13
15
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T P1
dB (d
Bm)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-00
8
Figure 8. Input P1dB vs. RF Frequency over Three Temperatures
8
9
10
11
12
13
14
15
16
17
18
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
SSB
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (MHz)
–40°C LOCKED–40°C EXTERNAL LO+25°C LOCKED+25°C EXTERNAL LO+85°C LOCKED+85°C EXTERNAL LO
1219
9-10
9
Figure 9. SSB Noise Figure vs. RF Frequency over Three Temperatures
ADRF6612 Data Sheet
Rev. A | Page 14 of 57
1.5
1.7
1.9
2.1
2.3
2.5
2.7
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
POW
ER D
ISSI
PATI
ON
(W)
TEMPERATURE (°C)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
0
Figure 10. Power Dissipation vs. Temperature for Three RF Frequencies
3.03.54.04.55.05.56.06.57.07.58.08.59.09.5
10.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
CONV
ERSI
ON
GAI
N (d
B)
TEMPERATURE (°C)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
1
Figure 11. Power Conversion Gain vs. Temperature for Three RF Frequencies
20212223242526272829303132333435
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
INPU
T IP
3 (d
Bm)
TEMPERATURE (°C)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
2
Figure 12. Input IP3 vs. Temperature for Three RF Frequencies
40424446485052545658606264666870
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
INPU
T IP
2 (d
Bm)
TEMPERATURE (°C)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
3
Figure 13. Input IP2 vs. Temperature for Three RF Frequencies
TEMPERATURE (°C)
5
6
7
8
9
10
11
12
13
14
15
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
INPU
T P1
dB (d
Bm)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2700MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2700MHz, HIGH-SIDE LO
1219
9-31
4
Figure 14. Input P1dB vs. Temperature for Three RF Frequencies
8
9
10
11
12
13
14
15
16
17
18
–40 –20 0 20 40 60 80
SSB
NO
ISE
FIG
UR
E (d
B)
TEMPERATURE (°C)
RF = 900MHzRF = 1900MHzRF = 2500MHz
1219
9-11
5
Figure 15. SSB Noise Figure vs. Temperature for Three RF Frequencies
Data Sheet ADRF6612
Rev. A | Page 15 of 57
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
40 80 120 160 200 240 280 320 360 400 440 480
POW
ER D
ISSI
PATI
ON
(W)
IF FREQUENCY (MHz)
RF = 2500MHz, LOW-SIDE LORF = 2500MHz, HIGH-SIDE LO
RF = 1900MHz, LOW-SIDE LORF = 1900MHz, HIGH-SIDE LO
RF = 900MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LO
1219
9-01
6
Figure 16. Power Dissipation vs. IF Frequency for Three RF Frequencies
3.03.54.04.55.05.56.06.57.07.58.08.59.09.5
10.0
40 80 120 160 200 240 280 320 360 400 440 480
CONV
ERSI
ON
GAI
N (d
B)
IF FREQUENCY (MHz)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
7
Figure 17. Power Conversion Gain vs. IF Frequency for Three RF Frequencies
10
12
14
16
18
20
22
24
26
28
30
32
34
36
40 80 120 160 200 240 280 320 360 400 440 480
INPU
T IP
3 (d
Bm)
IF FREQUENCY (MHz)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
8
Figure 18. Input IP3 vs. IF Frequency for Three RF Frequencies
30
35
40
45
50
55
60
65
70
75
80
85
40 80 120 160 200 240 280 320 360 400 440 480
INPU
T IP
2 (d
Bm)
IF FREQUENCY (MHz)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-01
9
Figure 19. Input IP2 vs. IF Frequency for Three RF Frequencies
5
6
7
8
9
10
11
12
13
14
15
40 80 120 160 200 240 280 320 360 400 440 480
INPU
T P1
dB (d
Bm)
IF FREQUENCY (MHz)
RF = 900MHz, LOW-SIDE LORF = 1900MHz, LOW-SIDE LORF = 2500MHz, LOW-SIDE LORF = 900MHz, HIGH-SIDE LORF = 1900MHz, HIGH-SIDE LORF = 2500MHz, HIGH-SIDE LO
1219
9-02
0
Figure 20. Input P1dB vs. IF Frequency for Three RF Frequencies
8
9
10
11
12
13
14
15
16
17
18
50 100 150 200 250 300 350 400 450
SSB
NO
ISE
FIG
UR
E (d
B)
IF FREQUENCY (MHz)
–40°C, LOW SIDE LO
–40°C, HIGH-SIDE LO
+25°C, LOW SIDE LO
+25°C, HIGH-SIDE LO
+85°C, LOW SIDE LO
+85°C, HIGH-SIDE LO
1219
9-12
1
Figure 21. SSB Noise Figure vs. IF Frequency for Three RF Frequencies
ADRF6612 Data Sheet
Rev. A | Page 16 of 57
–90–88–86–84–82–80–78–76–74–72–70–68–66–64–62–60–58–56–54–52–50
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
IF/2
SPU
RIO
US
(dB
)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-02
2
Figure 22. IF/2 Spurious vs. RF Frequency over Three Temperatures
–90–88–86–84–82–80–78–76–74–72–70–68–66–64–62–60–58–56–54–52–50
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
IF/3
SPU
RIO
US (d
B)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-12
3
Figure 23. IF/3 Spurious vs. RF Frequency over Three Temperatures
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF
TO IF
ISO
LATI
ON
(dB
c)
RF FREQUENCY (MHz) 1219
9–02
4–46–44–42–40–38–36–34–32–30–28–26–24–22–20–18–16–14–12–10–8–6–4–20
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
Figure 24. RF to IF Isolation vs. RF Frequency over Three Temperatures
–52
–48
–44
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LOTO
IF L
EAKA
GE
(dBm
)
LO FREQUENCY (MHz)
TA = –40°CTA = +25°CTA = +85°C
1219
9-02
5
Figure 25. LO to IF Leakage vs. LO Frequency over Three Temperatures
–68–64–60–56–52–48–44–40–36–32–28–24–20–16–12
–8–40
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LOTO
RF
LEAK
AGE
(dBm
)
LO FREQUENCY (MHz) 1219
9-02
6
TA = –40°CTA = +25°CTA = +85°C
Figure 26. LO to RF Leakage vs. LO Frequency over Three Temperatures
–64–60–56–52–48–44–40–36–32–28–24–20–16–12
–8–40
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
2 ×
LO L
EAKA
GE
(dBm
)
LO FREQUENCY (MHz)
2 × LO TO IF
TA = –40°CTA = +25°CTA = +85°C
2 × LO TO RF
1219
9-02
7
Figure 27. 2 × LO Leakage vs. LO Frequency (2 × LO to RF and 2 × LO to IF)
Data Sheet ADRF6612
Rev. A | Page 17 of 57
–64–60–56–52–48–44–40–36–32–28–24–20–16–12
–8–40
300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
3 ×
LO L
EAK
AG
E (d
Bm
)
LO FREQUENCY (MHz)
TA = –40°CTA = +25°CTA = +85°C
1219
9-02
8
3 × LO TO IF
3 × LO TO RF
Figure 28. 3 × LO Leakage vs. LO Frequency
(3 × LO to RF and 3 × LO to IF)
RETU
RN L
OSS
(dBm
)
RF FREQUENCY (MHz) 1219
9-12
9–35
–30
–25
–20
–15
–10
–5
0
500 1000 1500 2000 2500 3000
HIGH-SIDE LOLOW-SIDE LO
Figure 29. RF Port Return Loss, Fixed IF LO Return Loss
–30
–25
–20
–15
–10
–5
0
100 600 1100 1600 2100 2600
RETU
RN L
OSS
(dB)
FREQUENCY (MHz) 1219
9-13
0
Figure 30. LO Return Loss
100
7.70 7.75 7.80 7.85 7.90 7.95
CONVERSION GAIN (dB)
8.00 8.05 8.10
80
60
40
20
0
PERC
ENT
(%)
MEAN: 7.94SD: 0.07%
1219
9-13
1
Figure 31. Conversion Gain Distribution
MEAN: 31.23SD: 0.34%
100
27 28 29 30
INPUT IP3 (dBm)
31 32 353433
80
60
40
20
0
PER
CEN
T (%
)
1219
9-13
2
Figure 32. Input IP3 Distribution
MEAN: 10.59SD: 0.39%
100
10.0 10.1 10.2 10.3 10.4 10.5
INPUT P1dB (dBm)
10.6 10.7 11.010.910.8
80
60
40
20
0
PER
CEN
T (%
)
1219
9-13
3
Figure 33. Input P1dB Distribution
ADRF6612 Data Sheet
Rev. A | Page 18 of 57
RIN1
(Ω)
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
10
8
6
4
2
0
CIN1
(pF)
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz) 1219
9-33
4
Figure 34. IF Output Impedance (R Parallel C Equivalent)
0
1
2
3
4
5
6
7
8
9
10
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (MHz) 1219
9-03
5
BAL_COUT = 0BAL_COUT = 2BAL_COUT = 4BAL_COUT = 6BAL_COUT = 8BAL_COUT = 10BAL_COUT = 12BAL_COUT = 14
Figure 35. Conversion Gain vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
56789
1011121314151617181920
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T P1
dB (d
Bm)
RF FREQUENCY (MHz) 1219
9-03
6
BAL_COUT = 0BAL_COUT = 2BAL_COUT = 4BAL_COUT = 6BAL_COUT = 8BAL_COUT = 10BAL_COUT = 12BAL_COUT = 14
Figure 36. Input P1dB vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
20
25
30
35
40
45
50
55
60
65
70
75
80
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
IF C
HANN
EL-T
O-C
HANN
EL
ISO
LATI
ON
(dBc
)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-13
7
Figure 37. IF Channel-to-Channel Isolation vs. RF Frequency over Three Temperatures
202122232425262728293031323334353637383940
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
3 (d
Bm
)
RF FREQUENCY (MHz)
BAL_COUT = 0BAL_COUT = 2BAL_COUT = 4BAL_COUT = 6BAL_COUT = 8BAL_COUT = 10BAL_COUT = 12BAL_COUT = 14
1219
9-03
8
Figure 38. Input IP3 vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
8
9
10
11
12
13
14
15
16
17
18
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
SSB
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (MHz) 1219
9-13
9
BAL_COUT = 0BAL_COUT = 2BAL_COUT = 4BAL_COUT = 6BAL_COUT = 8BAL_COUT = 10BAL_COUT = 12BAL_COUT = 14
Figure 39. SSB Noise Figure vs. RF Frequency for All RFB Settings,
VGS and LPF Use Optimum Settings
Data Sheet ADRF6612
Rev. A | Page 19 of 57
0
1
2
3
4
5
6
7
8
9
10
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (MHz)
VGS = 0VGS = 1VGS = 2VGS = 3VGS = 4VGS = 5VGS = 6VGS = 7
1219
9-04
0
Figure 40. Conversion Gain vs. RF Frequency
for All VGS Settings, RFB and LPF Use Optimum Settings
181920212223242526272829303132333435363738
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
3 (d
Bm)
RF FREQUENCY (MHz)
VGS = 0VGS = 1VGS = 2VGS = 3VGS = 4VGS = 5VGS = 6VGS = 7
1219
9-14
1
Figure 41. Input IP3 vs. RF Frequency for All VGS Settings,
RFB and LPF Use Optimum Settings
3.03.54.04.55.05.56.06.57.07.58.08.59.09.5
10.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (MHz)
LPF = 0LPF = 2LPF = 4LPF = 6
1219
9-14
6
Figure 42. Conversion Gain vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
8.08.59.09.5
10.010.511.011.512.012.513.013.514.014.515.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T P1
dB (d
Bm
)
RF FREQUENCY (MHz)
VGS = 0VGS = 1VGS = 2VGS = 3VGS = 4VGS = 5VGS = 6VGS = 7
1219
9-04
3
Figure 43. Input P1dB vs. RF Frequency for All VGS Settings,
RFB and LPF Use Optimum Settings
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
SSB
NO
ISE
FIG
UR
E (d
B)
RF FREQUENCY (MHz)
VGS = 0VGS = 1VGS = 2VGS = 3VGS = 4VGS = 5VGS = 6VGS = 7
1219
9-14
4
Figure 44. SSB Noise Figure vs. RF Frequency for All VGS Settings,
RFB and LPF Use Optimum Settings
5
6
7
8
9
10
11
12
13
14
15
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T P1
dB (d
Bm)
RF FREQUENCY (MHz)
LPF = 0LPF = 2LPF = 4LPF = 6
1219
9-14
9
Figure 45. Input P1dB vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
ADRF6612 Data Sheet
Rev. A | Page 20 of 57
1011121314151617181920212223242526272829303132333435
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
3 (d
Bm)
RF FREQUENCY (MHz)
LPF = 0LPF = 2LPF = 4LPF = 6
1219
9-14
7
Figure 46. Input IP3 vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
TEMPERATURE (°C)
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
–40 –20 0 20 40 60 80
POW
ER D
ISSI
PATI
ON
(W)
IFMAIN = 3IFMAIN = 4IFMAIN = 5IFMAIN = 6IFMAIN = 7
IFMAIN = 8IFMAIN = 9IFMAIN = 10IFMAIN = 11IFMAIN = 12
IFMAIN = 13IFMAIN = 14IFMAIN = 15
1219
9-34
7
Figure 47. Power Dissipation vs. Temperature for IF Main Settings
TEMPERATURE (°C)
2.16
2.18
2.20
2.22
2.24
2.26
2.28
2.30
2.32
2.34
2.36
2.38
–40 –20 0 20 40 60 80
POW
ER D
ISSI
PATI
ON
(W)
IFLIN = 0IFLIN = 1IFLIN = 2IFLIN = 3IFLIN = 4IFLIN = 5IFLIN = 6IFLIN = 7
IFLIN = 8IFLIN = 9IFLIN = 10IFLIN = 11IFLIN = 12IFLIN = 13IFLIN = 14IFLIN = 15
1219
9-34
8
Figure 48. Power Dissipation vs. Temperature for IF LIN Settings
8
9
10
11
12
13
14
15
16
17
18
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
SSB
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (MHz)
LPF = 0LPF = 2LPF = 4LPF = 6
1219
9-15
0
Figure 49. SSB Noise Figure vs. RF Frequency for All LPF Settings,
RFB and VGS Use Optimum Settings
TEMPERATURE (°C)
10
15
20
25
30
35
40
–40 –20 0 20 40 60 80
INPU
T IP
3 (d
Bm
)
IFMAIN = 3IFMAIN = 4IFMAIN = 5IFMAIN = 6IFMAIN = 7IFMAIN = 8IFMAIN = 9
IFMAIN = 10IFMAIN = 11IFMAIN = 12IFMAIN = 13IFMAIN = 14IFMAIN = 15
1219
9-35
0
Figure 50. Input IP3 vs. Temperature for IF Main Settings
22
24
26
28
30
32
34
36
–40 –20 0 20 40 60 80
INPU
T IP
3 (d
Bm)
TEMPERATURE (°C)
IFLIN = 0IFLIN = 1IFLIN = 2IFLIN = 3IFLIN = 4IFLIN = 5IFLIN = 6IFLIN = 7
IFLIN = 8IFLIN = 9IFLIN = 10IFLIN = 11IFLIN = 12IFLIN = 13IFLIN = 14IFLIN = 15
1219
9-35
1
Figure 51. Input IP3 vs. Temperature for IF LIN Settings
Data Sheet ADRF6612
Rev. A | Page 21 of 57
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
0.001 0.01 0.1 1 10
PHA
SE N
OIS
E (d
Bc/
Hz)
OFFSET FREQUENCY (MHz)
890MHz +10dBm1910MHz +10dBm2510MHz +10dBm
1219
9-35
2
Figure 52. Phase Noise at IF Output vs. Offset Frequency with 10 dBm Blocker
in Integer Mode
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
0.001 0.01 0.1 1 10
PHA
SE N
OIS
E (d
Bc/
Hz)
OFFSET FREQUENCY (MHz)
890MHz +10dBm1910MHz +10dBm2510MHz +10dBm
1219
9-35
3
Figure 53. Phase Noise at IF Output vs. Offset Frequency with 10 dBm Blocker
in Fractional Mode
ADRF6612 Data Sheet
Rev. A | Page 22 of 57
MIXER, HIGH EFFICIENCY MODE TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted.
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
POW
ER D
ISSI
PATI
ON
(W)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = 25°C, HIGH-SIDE LOTA = 85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = 25°C, LOW-SIDE LOTA = 85°C, LOW-SIDE LO
1219
9-15
1
Figure 54. Power Dissipation vs. RF Frequency over Three Temperatures
3.03.54.04.55.05.56.06.57.07.58.08.59.09.5
10.010.511.011.512.0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
CONV
ERSI
ON
GAI
N (d
B)
RF FREQUENCY (MHz)
TA = –40°C, HIGH_LOTA = +25°C,HIGH_LOTA = +85°C, HIGH_LOTA = –40°C, LOW_LOTA = +25°C, LOW_LOTA = +85°C, LOW_LO
1219
9-15
2
Figure 55. Conversion Gain vs. RF Frequency over Three Temperatures
RF FREQUENCY (MHz)
579
11131517192123252729313335
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
3 (d
Bm)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-15
3
Figure 56. Input IP3 vs. RF Frequency over Three Temperatures
30
35
40
45
50
55
60
65
70
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T IP
2 (d
Bm
)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-35
7
Figure 57. Input IP2 vs. RF Frequency over Three Temperatures
3
4
5
6
7
8
9
10
11
12
13
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
INPU
T P1
dB (d
Bm)
RF FREQUENCY (MHz)
TA = –40°C, HIGH-SIDE LOTA = +25°C, HIGH-SIDE LOTA = +85°C, HIGH-SIDE LOTA = –40°C, LOW-SIDE LOTA = +25°C, LOW-SIDE LOTA = +85°C, LOW-SIDE LO
1219
9-15
5
Figure 58. Input P1dB vs. RF Frequency over Three Temperatures
8
9
10
11
12
13
14
15
16
17
18
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
SSB
NOIS
E FI
GUR
E (d
B)
RF FREQUENCY (MHz)
–40°C LOCKED–40°C EXTERNAL LO+25°C LOCKED+25°C EXTERNAL LO+85°C LOCKED+85°C EXTERNAL LO
1219
9-15
6
Figure 59. SSB Noise Figure vs. RF Frequency over Three Temperatures
Data Sheet ADRF6612
Rev. A | Page 23 of 57
SYNTHESIZER VS = high performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fPFD = 1.536 MHz, fREF power = 4 dBm, integer mode loop filter, unless otherwise noted.
–180
–160
–140
–120
–100
–80
–60
–40
1k 10k 100k 1M 10M 100M
OPE
N-L
OO
P PH
ASE
NO
ISE
(dB
c/H
z)
OFFSET FREQUENCY (Hz) 1219
9-15
7
Figure 60. VCO_0 Open-Loop Phase Noise vs. Offset Frequency, fVCO_0 = 5.1 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
1k 10k 100k 1M 10M 100M–180
–160
–140
–120
–100
–80
–60
–40
OPE
N-LO
OP
PHAS
E NO
ISE
(dBc
/Hz)
OFFSET FREQUENCY (Hz) 1219
9-15
8
Figure 61. VCO_1 Open-Loop Phase Noise vs. Offset Frequency, fVCO_1 = 4.5 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
1k 10k 100k 1M 10M 100M–180
–160
–140
–120
–100
–80
–60
–40
OPE
N-L
OO
P PH
ASE
NO
ISE
(dB
c/H
z)
OFFSET FREQUENCY (Hz) 1219
9-15
9
Figure 62. VCO_2 Open-Loop Phase Noise vs. Offset Frequency, fVCO_2 = 3.8 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
0.001 0.01 0.1 1 10 100
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
OFFSET FREQUENCY (MHz)
LO_DIV = /2LO_DIV = /4LO_DIV = /8
1219
9-06
0
Figure 63. VCO_0 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fVCO_0 = 5.1 GHz
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
0.001 0.01 0.1 1 10 100
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
OFFSET FREQUENCY (MHz)
LO_DIV = /2LO_DIV = /4LO_DIV = /8
1219
9-06
1
Figure 64. VCO_1 Closed-Loop Phase Noise for Various LO_DIV Dividers vs.
Offset Frequency, fVCO_1 = 4.5 GHz
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
0.001 0.01 0.1 1 10 100
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
OFFSET FREQUENCY (MHz)
LO_DIV = /2LO_DIV = /4LO_DIV = /8
1219
9-06
2
Figure 65. VCO_2 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fVCO_2 = 3.8 GHz
ADRF6612 Data Sheet
Rev. A | Page 24 of 57
1k 10k 100k 1M 10M 100M–160
–140
–120
–100
–80
–60
–40
OPE
N-L
OO
P PH
ASE
NO
ISE
(dB
c/H
z)
OFFSET FREQUENCY (Hz) 1219
9-16
3
Figure 66. VCO_3 Open-Loop Phase Noise vs. Offset Frequency,
fVCO_3 = 3.2 GHz, Divide by Two Selected, VCOVTUNE = 1.5 V
–230
–225
–220
–215
–210
–205
–200
1430 1630 1830 2030 2230 2430 2630 2830
FOM
(dBc
/Hz/
Hz)
LO FREQUENCY (MHz)
–40°C+25°C+85°C
1219
9-36
7
Figure 67. PLL Figure of Merit (FOM) vs. LO Frequency, Integer Mode
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
1430 1630 1830 2030 2230 2430 2630 2830
OPE
N-LO
OP
PHAS
E NO
ISE
(dBc
/Hz)
LO FREQUENCY (MHz)
10MHz OFFSET
500kHz OFFSET
100kHz OFFSET
1kHz OFFSET
–40°C+25°C+85°C
1219
9-16
5
Figure 68. Open-Loop Phase Noise vs. LO Frequency,
Divide by Two Selected
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
0.001 0.01 0.1 1 10 100
CLO
SED-
LOO
P PH
ASE
NOIS
E (d
Bc/H
z)
OFFSET FREQUENCY (MHz)
LO_DIV = /2LO_DIV = /4LO_DIV = /8
1219
9-06
6
Figure 69. VCO_3 Closed-Loop Phase Noise for Various LO_DIV Dividers vs.
Offset Frequency, fVCO_3 = 3.2 GHz
–230
–225
–220
–215
–210
–205
–200
1430 1630 1830 2030 2230 2430 2630 2830
FOM
(dBc
/Hz/
Hz)
LO FREQUENCY (MHz)
–40°C+25°C+85°C
1219
9-47
0
Figure 70. PLL Figure of Merit (FOM) vs. LO Frequency, Fractional Mode Offset =
45 kHz, Bleed = 125 µA
–170
–160
–150
–140
–130
–120
–110
–100
–90
1430 1630 1830 2030 2230 2430 2630 2830
OPE
N-L
OO
P PH
ASE
NO
ISE
(dB
c/H
z)
LO FREQUENCY (MHz)
–40°C+25°C+85°C
50kHz OFFSET
200kHz OFFSET
1MHz OFFSET
40MHz OFFSET
1219
9-16
8
Figure 71. Open-Loop Phase Noise vs. LO Frequency,
Divide by Two Selected
Data Sheet ADRF6612
Rev. A | Page 25 of 57
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
1430
PHA
SE N
OIS
E (d
Bc/
Hz)
LO FREQUENCY (MHz)
–40°C+25°C+85°C 1kHz OFFSET
100kHz OFFSET
500kHz OFFSET
10 MHz OFFSET
1630 1830 2030 2230 2430 2630
1219
9-06
9
Figure 72. Integer Loop Filter Phase Noise, Divide by Two Selected,
Offset = 1 kHz, 100 kHz, 500 kHz, and 10 MHz
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
2860 3360 3860 4360 4860 5360
INTE
GRA
TED
PHAS
E NO
ISE,
WIT
H SP
URS
(°rm
s)
VCO FREQUENCY (MHz)
–40°C+25°C+85°C
LO_DIV = /8
LO_DIV = /2
LO_DIV = /4
1219
9-07
0
Figure 73. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency,
Divide by Two, Four, and Eight, Including Spurs
–135
–125
–115
–105
–95
–85
–75
2860 3360 3860 4360 4860 5360
REFE
RENC
E SP
URS
(dBc
), 1
× PF
D O
FFSE
T
VCO FREQUENCY (MHz)
–40°C LO_DIV = /8+25°C LO_DIV = /8+85°C LO_DIV = /8
–40°C LO_DIV = /2+25°C LO_DIV = /2+85°C LO_DIV = /2–40°C LO_DIV = /4+25°C LO_DIV = /4+85°C LO_DIV = /4
1219
9-07
1
Figure 74. fPFD Reference Spurs vs. VCO Frequency,
1 × PFD Offset, Measured at LO Output, Integer Mode
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
PHAS
E NO
ISE
(dBc
/Hz)
LO FREQUENCY (Hz)
–40°C+25°C+85°C
50 kHz OFFSET
200 kHz OFFSET
1MHz OFFSET
40MHz OFFSET
1430 1630 1830 2030 2230 2430 2630
1219
9-07
2
Figure 75. Integer Loop Filter Phase Noise, Divide by Two Selected,
Offset = 50 kHz, 200 kHz, 1 MHz, and 40 MHz
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
2860 3360 3860 4360 4860 5360
INTE
GRA
TED
PH
ASE
NO
ISE,
WIT
HO
UT
SPU
RS
(°rm
s)
VCO FREQUENCY (MHz)
–40°C+25°C+85°C
LO_DIV = /8
LO_DIV = /2
LO_DIV = /4
1219
9-07
3
Figure 76. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency,
Divide by Two, Four, and Eight, Excluding Spurs
–135
–125
–115
–105
–95
–85
–75
2860 3360 3860 4360 4860 5360
REF
EREN
CE
SPU
RS
(dB
c), 2
× P
FD O
FFSE
T
VCO FREQUENCY (MHz)
–40°C LO_DIV = /8+25°C LO_DIV = /8+85°C LO_DIV = /8
–40°C LO_DIV = /2+25°C LO_DIV = /2+85°C LO_DIV = /2–40°C LO_DIV = /4+25°C LO_DIV = /4+85°C LO_DIV = /4
1219
9-07
4
Figure 77. fPFD Reference Spurs vs. VCO Frequency,
2 × PFD Offset, Measured at LO Output, Integer Mode
ADRF6612 Data Sheet
Rev. A | Page 26 of 57
–135
–125
–115
–105
–95
–85
–75
2860 3360 3860 4360 4860 5360
REF
EREN
CE
SPU
RS
(dB
c), 3
× P
FD O
FFSE
T
VCO FREQUENCY (MHz)
–40°C LO_DIV = /8+25°C LO_DIV = /8+85°C LO_DIV = /8
–40°C LO_DIV = /2+25°C LO_DIV = /2+85°C LO_DIV = /2–40°C LO_DIV = /4+25°C LO_DIV = /4+85°C LO_DIV = /4
1219
9-07
5
Figure 78. fPFD Reference Spurs vs. VCO Frequency,
3 × PFD Offset, Measured at LO Output, Integer Mode
–90
–85
–80
–75
–70
–65
–60
1430 1630 1830 2030 2230 2430 2630 2830
REF
EREN
CE
SPU
RS
(dB
c), 1
× P
FD O
FFSE
T
LO FREQUENCY (MHz)
–40°C+25°C+85°C
1219
9-37
9
Figure 79. fPFD Reference Spurs vs. LO Frequency,
1 × PFD Offset, Measured at LO Output, Fractional Mode
1430 1630 1830 2030 2230 2430 2630 2830–90
–88
–86
–84
–82
–80
–78
–76
–74
–72
–70
REFE
RENC
E SP
URS
(dBc
), 3
× PF
D O
FFSE
T
LO FREQUENCY (MHz)
–40°C+25°C+85°C
1219
9-38
0
Figure 80. fPFD Reference Spurs vs. LO Frequency,
3 × PFD Offset, Measured at LO Output, Fractional Mode
–135
–125
–115
–105
–95
–85
–75
2860 3360 3860 4360 4860 5360
REF
EREN
CE
SPU
RS
(dB
c), 4
× P
FD O
FFSE
T
VCO FREQUENCY (MHz)
–40°C LO_DIV = /8+25°C LO_DIV = /8+85°C LO_DIV = /8
–40°C LO_DIV = /2+25°C LO_DIV = /2+85°C LO_DIV = /2–40°C LO_DIV = /4+25°C LO_DIV = /4+85°C LO_DIV = /4
1219
9-07
8
Figure 81. fPFD Reference Spurs vs. VCO Frequency,
4 × PFD Offset, Measured at LO Output, Integer Mode
1430 1630 1830 2030 2230 2430 2630 2830–80
–78
–76
–74
–72
–70
–68
–66
–64
–62
–60
REF
EREN
CE
SPU
RS
(dB
c), 2
× P
FD O
FFSE
T
LO FREQUENCY (MHz)
–40°C+25°C+85°C
1219
9-38
2
Figure 82. fPFD Reference Spurs vs. LO Frequency,
2 × PFD Offset, Measured at LO Output, Fractional Mode
1430 1630 1830 2030 2230 2430 2630 2830
LO FREQUENCY (MHz)
–90
–88
–86
–84
–82
–80
–78
–76
REFE
RENC
E SP
URS
(dBc
), 4
× PF
D O
FFSE
T –40°C+25°C+85°C
1219
9-38
3
Figure 83. fPFD Reference Spurs vs. LO Frequency,
4 × PFD Offset, Measured at LO Output, Fractional Mode
Data Sheet ADRF6612
Rev. A | Page 27 of 57
–140
–120
–100
–80
–60
–40
–20
0
1430 1630 1830 2030 2230 2430 2630 2830
REFE
RENC
E SP
URS
(dBc
), 1
× PF
D O
FFSE
T
LO FREQUENCY (MHz)
IF AT –40°CIF AT +25°CIF AT +85°CLO AT –40°CLO AT +25°CLO AT +85°C
1219
9-38
4
Figure 84. fPFD Reference Spurs vs. LO Frequency, Divide by Two Selected, 1 × PFD
Offset, Measured on LO Output and IF Output
–12
–10
–8
–6
–4
–2
0
2
4
3
8
10
350 850 1350 1850 2350 2850
LO A
MPL
ITU
DE
(dB
m)
LO FREQUENCY (MHz) 1219
9-50
0LO_DRV_LVL = 0 AT –40°CLO_DRV_LVL = 0 AT +25°CLO_DRV_LVL = 0 AT +85°C
LO_DRV_LVL = 1 AT –40°CLO_DRV_LVL = 1 AT +25°CLO_DRV_LVL = 1 AT +85°C
LO_DRV_LVL = 2 AT –40°CLO_DRV_LVL = 2 AT +25°CLO_DRV_LVL = 2 AT +85°C
LO_DRV_LVL = 3 AT –40°CLO_DRV_LVL = 3 AT +25°CLO_DRV_LVL = 3 AT +85°C
Figure 85. LO Amplitude vs. LO Frequency, LO_DRV_LVL = 0, 1, 2, and 3
125
135
145
155
165
175
185
195
205
215
225
350 850 1350 1850 2350 2850
VCC
7 SU
PPLY
CU
RR
ENT
(mA
)
LO FREQUENCY (MHz)
LO_DRV_LVL = 0 AT –40°CLO_DRV_LVL = 0 AT +25°CLO_DRV_LVL = 0 AT +85°C
LO_DRV_LVL = 1 AT –40°CLO_DRV_LVL = 1 AT +25°CLO_DRV_LVL = 1 AT +85°C
LO_DRV_LVL = 2 AT –40°CLO_DRV_LVL = 2 AT +25°CLO_DRV_LVL = 2 AT +85°C
LO_DRV_LVL = 3 AT –40°CLO_DRV_LVL = 3 AT +25°CLO_DRV_LVL = 3 AT +85°C
1219
9-38
6
Figure 86. Supply Current for VCC7 vs. LO Frequency,
LO_DRV_LVL = 0, 1, 2, and 3
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
ISO
LATI
ON
(dB)
RF FREQUENCY (MHz) 1219
9-38
7
Figure 87. RF to LO Output Feedthrough, LO_DRV_LVL = 0
1480
1485
1490
1495
1500
1505
1510
1515
1520
0 10 20 30 40 50 60 70 80 90 100
LO F
REQ
UENC
Y (M
Hz)
LOCK TIME (ms) 1219
9-38
8
Figure 88. LO Frequency Settling Time, Integer Mode Loop Filter,
Integer Mode
1480
1485
1490
1495
1500
1505
1510
1515
1520
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LO F
REQ
UENC
Y (M
Hz)
LOCK TIME (ms) 1219
9-38
9
Figure 89. LO Frequency Settling Time, Fractional Loop Filter, Fractional Mode
ADRF6612 Data Sheet
Rev. A | Page 28 of 57
0
0.5
1.0
1.5
2.0
2.5
1430 1630 1830 2030 2230 2430 2630 2830
V TU
NE
(V)
LO FREQUENCY (MHz)
VTUNE +85°CVTUNE –40°C
1219
9-18
7
Figure 90. VTUNE vs. LO Frequency for Lock at Cold Drift to Hot
0
0.5
1.0
1.5
2.0
2.5
1430 1630 1830 2030 2230 2430 2630 2830
V TU
NE
(V)
LO FREQUENCY (MHz)
VTUNE +85°CVTUNE –40°C
1219
9-18
8
Figure 91. VTUNE vs. LO Frequency for Lock at Hot Drift to Cold
–140
–130
–120
–110
–100
–90
–80
–70
–60
–100 –80 –60 –40 –20 0 20 40 60 80 100
PFD
SPUR
S (d
Bc)
OFFSET FREQUENCY (MHz)
3.18GHz3.81GHz4.45GHz5.08GHz
1219
9-18
9
Figure 92. PFD Spurs vs. Offset Frequency for 4 VCOs, Integer Mode
Data Sheet ADRF6612
Rev. A | Page 29 of 57
SPURIOUS PERFORMANCE (N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm.
High Performance Mode
VS = high performance mode, TA = 25°C, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted.
Table 11. RF = 900 MHz, LO = 697 MHz M 0 1 2 3 4 5 6 7 8 9
N
0 −27.1 −32.1 −39.1 −27.0 −54.2 −48.5 −69.3 −65.6
1 −35.5 0.0 −52.5 −18.4 −56.6 −43.6 −66.7 −53.5 −87.4 −73.5
2 −55.3 −68.9 −68.8 −73.4 −64.9 <−100 −68.3 <−100 −80.6 <−100
3 −88.2 −88.4 <−100 −79.5 <−100 −94.1 <−100 <−100 <−100 <−100 4 <−100 −56.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 −43.6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 −66.7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 −53.5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100
Table 12. RF = 1900 MHz, LO = 1697 MHz M 0 1 2 3 4 5 6 7 8 9
N
0 −37.0 −31.2 −64.2 1 −30.2 0.0 −47.9 −52.1 −74.4 2 −70.8 −71.9 −81.6 −81.2 −67.2 <−100
3 <−100 <−100 −93.5 −75.2 <−100 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 8 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100
Table 13. RF = 2500 MHz, LO = 2297 MHz M 0 1 2 3 4 5 6 7 8 9
N
0 −40.7 −44.1
1 −29.0 0.0 −49.4 −58.7
2 −81.0 −87.3 −75.4 −79.0 −84.7
3 <−100 −91.9 −74.7 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 −92.5 <−100 <−100
7 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100
9 <−100 <−100
ADRF6612 Data Sheet
Rev. A | Page 30 of 57
High Efficiency Mode
VS = high efficiency mode, TA = 25°C, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted.
Table 14. RF = 900 MHz, LO = 697 MHz M 0 1 2 3 4 5 6 7 8 9
N
0 −30.4 −34.1 −46.7 −29.6 −57.4 −51.2 −74.7 −62.7
1 −37.7 0.0 −52.6 −19.2 −61.6 −44.3 −64.0 −53.6 −91.8 −73.2
2 −70.3 −66.4 −68.8 −71.9 −59.9 −93.0 −67.8 <−100 −79.0 <−100
3 −86.4 −81.0 −96.4 −74.7 <−100 −85.0 <−100 <−100 <−100 <−100 4 <−100 <−100 −97.9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100
Table 15. RF = 1900 MHz, LO = 1697 MHz M 0 1 2 3 4 5 6 7 8 9
N
0 −41.4 −35.1 −69.0 1 −30.5 0.0 −46.9 −52.2 −74.4 2 −71.5 −67.7 −74.6 −71.3 −63.6 <−100
3 <−100 <−100 −89.9 −67.7 <−100 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 8 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100
Table 16. RF = 2500 MHz, LO = 2297 MHz M 0 1 2 3 4 5 6 7 8 9
N
0 −42.3 −48.6
1 −29.1 0.0 −48.6 −59.4
2 −75.6 −88.8 −71.6 −70.8 −77.0
3 −59.4 −86.2 −66.9 <−100 <−100
4 −77.0 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100
9 <−100 <−100
Data Sheet ADRF6612
Rev. A | Page 31 of 57
CIRCUIT DESCRIPTION The ADRF6612 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. The wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components.
The RF subsystem consists of an integrated, tunable, low loss RF balun, a double balanced, passive MOSFET mixer, a tunable sum termination network, and an IF amplifier.
The LO subsystem consists of a multistage, limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A schematic of the device is shown in Figure 94.
RF SUBSYSTEM The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a tunable, low loss, unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended to use a blocking capacitor to avoid running excessive dc current through the device. The RF balun can easily support an RF input frequency range of 700 MHz to 3000 MHz. This balun is tuned over the frequency range by a SPI controlled switched capacitor network at the output of the RF balun.
The resulting balanced RF signal is applied to a passive mixer that commutates the RF input in accordance with the output of the LO subsystem. The passive mixer is a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms.
The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced open-collector output of the IF amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an analog-to-digital converter (ADC) input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer or an LC impedance matching network.
EXTERNAL LO GENERATION The ADRF6612 LO can be generated by an externally applied source or by using the internal PLL synthesizer.
To select the external LO mode, write the value 011 to Register 0x22, Bits[2:0] and apply the differential LO signal to Pin 4 (EXTVCOIN+) and Pin 5 (EXTVCOIN−).
Internal dividers allow the externally applied LO signal to be divided before this signal arrives at the mixer LO input. The divider value is set by Register 0x21, Bits[5:3] and has possible values of 1, 2, 4, and 8. With the divider set to 1, the externally applied LO input frequency range is 250 MHz to 2850 MHz. When using a divider value of other than 1, the maximum externally applied LO frequency is 5700 MHz.
The external LO input pins present a broadband differential 50 Ω input impedance. The EXTVCOIN+ and EXTVCOIN− input pins must be ac-coupled. When not in use, EXTVCOIN+ and EXTVCOIN− can be left unconnected.
INTERNAL LO GENERATION Reference Input Circuitry
The ADRF6612 includes an on-chip PLL for LO synthesis. The PLL, shown in Figure 93, consists of a reference input and input dividers, a PFD, a charge pump, VCOs, and a programmable fractional/integer divider with a 2× prescaler.
The reference path takes in a reference clock and divides it by a factor of 1 to 8191 before passing it to the PFD. The PFD compares this signal to the divided down signal from the VCO. Depending on the PFD polarity selected, the PFD sends an up or down signal to the charge pump if the VCO signal is slow or fast compared to the reference frequency. The charge pump sends a current pulse to the off-chip loop filter to increase or decrease the tuning voltage (VCOVTUNE).
In band (within the band of the loop filter) phase noise performance is typically limited by the reference source. Due to the inherent phase noise reduction when performing frequency division, improved in band phase noise performance can be achieved with higher reference divide values. However, the divide chain adds its own small amount of phase noise, so there is a limit on how much improvement can be gained by increasing the divider value.
ADRF6612 Data Sheet
Rev. A | Page 32 of 57
1 TO 8191(REG 0x21[11:0])
N = INT + FRACMOD
(REG 0x02, REG 0x03,REG 0x04)
PFD
MIXER 1 LO
MIXER 2 LO EXTERNALLO INPUT
CHARGEPUMP
2×PRESCALER
CPOUT
C18 C20 C22R7
R8 R10
C23
VCOVTUNELOOP FILTER
GNDCP
REFIN
LO DIVIDER(1, 2, 4, 8, 16, 32)(REG 0x22[5:3])
1219
9-09
0
Figure 93. LO Generation Block Diagram
Loop Filters
Defining a loop filter for the ADRF6612 depends on several dynamics, these being the PLL REFIN and PFD frequency and desired PFD and fractional spur levels. Higher reference and PFD frequencies spread the PFD spurs over a wider bandwidth (wider separation between spurs), but also lead to higher levels of spurs coupling through the reference divider chain. Lower reference and PFD frequencies lower the spacing between PFD spurs, but the spur levels can be significantly improved by using lower frequencies. At lower PFD frequencies, it may also be possible to achieve the desired synthesizer frequency step size using the integer divider mode, therefore eliminating the risk of fractional spurs. Table 17 shows the recommended loop filter components and dynamic loop settings when using integer mode and PFD frequencies at less than 10 MHz.
Table 17. Integer Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components PLL Dynamic Settings C18 1500 pF R7 910 Ω C20 33 nF R8 1.8 kΩ C22 560 pF R10 20 kΩ C23 39 pF CSCALE 8000 µA Bleed Current 0 µA ABDLY 0.9 nS
If a smaller frequency step size is desired, the ADRF6612 can be used in fractional mode. The 16-bit FRAC_DIV and MOD_DIV values available in the ADRF6612 mean that small step sizes can be achieved with high PFD frequencies. PFD spurs may be higher in amplitude, but are spaced further apart. Fractional spurs may be present as well.
Table 18. Fractional Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components PLL Dynamic Settings C18 1000 pF R7 700 Ω C20 33 nF R8 1.8 kΩ C22 560 pF R10 20 kΩ C23 39 pF CSCALE 500 µA Bleed Current 93.75 µA ABDLY 0 nS
VCOs and Dividers
The ADRF6612 has four internal VCOs. Considering the range of these VCOs, the fixed 2× prescaler after the VCO, and the LO_DIV (1, 2, 4, 8, 16, and 32) range, the total LO range allows RF generation of 200 MHz to 2700 MHz.
Table 19. VCO Range VCO_SEL (Register 0x22, Bits[2:0])1 Frequency Range (GHz) 1 000 VCO_0 = 4.6 to 5.7 001 VCO_1 =4.02 to 4.6 010 VCO_2 =3.5 to 4.02 011 VCO_3 =2.85 to 3.5
1 For VCO_0, VCO_1, VCO_2, and VCO_3, set VTUNE_DAC_SLOPE (Register 0x49, Bits[13:9]) = 11 (decimal), VTUNE_DAC_OFFSET (Register 0x49, Bits[8:0]) = 184 (decimal), VCO_LDO_R2 (Register 0x22, Bits[11:8]) = 0 (decimal), and VCO_LDO_R4 (Register 0x22, Bits[15:12]) = 5 (decimal).
The N-divider divides down the differential VCO signal to the PFD frequency. The N-divider can be configured for fractional mode or integer mode by addressing the DIV_MODE bit (Register 0x02, Bit 15). The default configuration is set for fractional mode.
Data Sheet ADRF6612
Rev. A | Page 33 of 57
The following equations can be used to determine the N value and the PLL frequency:
Nf
f VCOPFD ×
=2
MOD
FRACINTN +=
LO_DIVIDERNf
f PFDLO
××=
2
where: fPFD is the phase frequency detector frequency. fVCO is the voltage controlled oscillator frequency. N is the fractional divide ratio. INT is the integer divide ratio programmed in Register 0x02. FRAC is the fractional divide ratio programmed in Register 0x03. MOD is the modulus divide ratio programmed in Register 0x04. fLO is the LO frequency going to the mixer core when the loop is locked. LO_DIVIDER is the final divider block that divides the VCO frequency down by 1, 2, 4, or 8 before it reaches the mixer (see Table 20). This control is located in the LO_DIV bits (Register 0x22, Bits[5:3]).
Table 20. LO Divider LO_DIV (Register 0x22, Bits[5:3]) LO_DIVIDER 00 1 01 2 10 4 11 8
The lock detect signal is available as one of the selectable outputs through the MUXOUT pin; a logic high indicates that the loop is locked. The MUXOUT pin is controlled by the REF_MUX_SEL bits (Register 0x21, Bits[14:13]); the PLL lock detect signal is the default configuration.
To ensure that the PLL locks to the desired frequency, follow the proper write sequence of the PLL registers. The PLL registers must be configured accordingly to achieve the desired frequency, and the last writes must be to Register 0x02 (INT_DIV in Table 25),
Register 0x03 (FRAC_DIV in Table 25), or Register 0x04 (MOD_DIV in Table 25). When one of these registers is programmed, an internal VCO calibration is initiated, which is the last step in locking the PLL.
The time it takes to lock the PLL after the last register is written can be broken down into two parts: VCO band calibration and loop settling.
After the last register is written, the PLL automatically performs a VCO band calibration to choose the correct VCO band. This calibration takes approximately 5120 PFD cycles. For a 40 MHz fPFD, this corresponds to 128 µs. After calibration is complete, the feedback action of the PLL causes the VCO to eventually lock to the correct frequency. The speed with which this locking occurs depends on the nonlinear cycle-slipping behavior, as well as the small-signal settling of the loop. For an accurate estimation of the lock time, download the ADIsimPLL™ tool, which correctly captures these effects. In general, higher bandwidth loops tend to lock faster than lower bandwidth loops.
Additional LO Controls
To access the LO signal going to the mixer core through the LOOUT+ and LOOUT− pins (Pin 13 and Pin 14), enable the LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct monitoring of the LO signal to the mixer for debug purposes; or the LO signal can be used to daisy-chain many devices synchronously. One ADRF6612 can serve as the master where the LO signal is sourced, and the subsequent slave devices share the same LO signal from the master. This flexibility substantially eases the LO requirements of a system with multiple LOs.
The LO output drive level is controlled by the LO_DRV_LVL bits (Register 0x22, Bits[7:6]). Table 21 shows the available drive levels.
Table 21. LO Drive Levels LO_DRV_LVL (Register 0x22, Bits[7:6]) Amplitude (dBm) 00 −4 01 0.5 10 3 11 4.5
ADRF6612 Data Sheet
Rev. A | Page 34 of 57
EXTVCOIN+
EXTVCOIN–
DECL3
DEC
L1
DEC
L2
LOO
UT+
LOO
UT–
LDO
1
VCC2
SDIO
SCLK C
S
IFO
UT2
+IF
OU
T2–
VCC3
DN
C
VCC6
VCC4
VCC5
RFBCT2RFIN2
LDO
2
VCC8
VCC
10
RFBCT1
RFIN1
IFO
UT1
+IF
OU
T1–
VCC
11
DN
C
CPO
UT
REF
IN
MU
XOU
T
LDO3
VCC
12
VCO
VTU
NE
SPICONTROL
DIVIDE BY1 TO 32
PLLCHARGE PUMP
3.3V LDO
VCOLDO
SPI2.5VLDO
LO DIV3.3VLDO
VCO
VCO
VCO
4
5
9
10
11
12
151413
16
17 18 19 22 23
40
21
39 3841
20
424347
37
2
44
45
46
27
28
29
25
26
30
35
36
32
34
VCC7 31
3 6 24
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
1 48
VCC
9
33
INTN-DIVIDER
2.5VLDO
7
N-DIVIDER
REFINDIVIDER
PFD
LOCKDETECT
VPTATSCAN
EXPOSEDPAD VCO
BUFFERLDO
VCO BANDSWITCH LDO
VCC1DECL4
DECL5
LDO4
8
1219
9-09
1
Figure 94. Simplified Schematic
Data Sheet ADRF6612
Rev. A | Page 35 of 57
APPLICATIONS INFORMATION The ADRF6612 mixer is designed to downconvert radio frequencies (RF) primarily between 700 MHz and 2800 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 95 depicts the basic connections of the mixer.
It is recommended to ac couple the RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. A RFIN capacitor value of 22 pF is recommended.
EXTVCOIN+
EXTVCOIN–
DECL3
DEC
L1
DEC
L2
LOO
UT+
LOO
UT–
LDO
1
VCC2
SDIO
SCLK C
S
IFO
UT2
+IF
OU
T2–
VCC3
DN
C
VCC6
VCC4
VCC5
RFBCT2RFIN2
LDO
2
VCC8
VCC
10
RFBCT1
RFIN1
IFO
UT1
+IF
OU
T1–
VCC
11
DN
C
CPO
UT
REF
IN
MU
XOU
T
LDO3
VCC
12
VCO
VTU
NE
SPICONTROL
DIVIDE BY1 TO 32
PLLCHARGE PUMP
3.3V LDO
VCOLDO
SPI2.5VLDO
LO DIV3.3VLDO
VCO
VCO
VCO
4
5
910
11
12
151413
16
17 18 19 22 23
40
21
39 3841
20
424347
37
2
44
45
46
27
28
29
25
26
30
35
36
32
34
VCC731
3 6 24
GND
1 48
VCC
9
33
INTN-DIVIDER
2.5VLDO
7
N-DIVIDER
REFINDIVIDER
PFD
LOCKDETECT
VPTATSCAN
10µF(0603)
0.1µF(0402) 6.8pF
(0402)
22pF(0402)
2700pF(0402)
3.16kΩ(0402)
10kΩ(0402)
10kΩ(0402)
22pF(0402)
+5V
150pF(0402)
150pF(0402)
150pF(0402)
330nH 330nH
RFIN1
RFIN2
IFOUT1
REFIN
1000pF(0402)
50Ω(0402)
100pF(0402)
LOIN100pF(0402)100pF(0402)
EXPOSEDPAD
VCOBUFFER
LDO
VCO BANDSWITCH LDO
22pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10µF(0603)
10pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
10µF(0603)
10µF(0603)
10µF(0603)
10µF(0603)
10µF(0603)
10nF(0603)
10nF(0603)
10µF(0603)
10µF(0603)
10µF(0603)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
VCC110µF
(0603)0.1µF
(0402)
100pF(0402)
100pF(0402)
100pF(0402)
DECL4100pF(0402)
DECL5100pF(0402)
LDO4100pF(0402)
10pF(0402)
10pF(0402)
10pF(0402)
100pF(0402)
100pF(0402)
100pF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
10µF(0603)
0.1µF(0402)
8
+5V
150pF(0402)
150pF(0402)
150pF(0402)
330nH 330nH
IFOUT2LOOUT
22pF(0402)
1219
9-08
2
Figure 95. Basic Connections Diagram
ADRF6612 Data Sheet
Rev. A | Page 36 of 57
BASIC CONNECTIONS PIN DESCRIPTION Table 22. Basic Connections Pin No. Mnemonic Description Basic Connection
5 V Power Decouple to GND with a 10 µF, a 0.1 µF, and a 10 pF capacitor as close to the pin as possible.
7 VCC1 5 V VCO supply 16 VCC2 5 V supply for SPI port 20, 41 VCC3, VCC11 5 V biases for IF Channel 2 and IF Channel 1 27, 28, 29, 32, 33,
34 VCC4, VCC5, VCC6, VCC8, VCC9, VCC10
5 V supplies for mixer LO amplifier
31 VCC7 5 V supply for mixer LO divider chain 46 VCC12 5 V supply for internal PLL
Internal LDO Nodes Decouple to GND with a 10 µF and a 100 pF capacitor, as close to the pin as possible.
8, 9 DECL1, DECL2 VCO LDO outputs 10, 11, 12 DECL3, DECL4, DECL5 External decoupling for VCO circuitry 15 LDO1 External decoupling for internal 2.5 V SPI
LDO
30 LDO2 External decoupling for internal 3.3 V PLL/divider LDO
44 LDO3 External decoupling for internal 2.5 V PLL LDO
45 LDO4 External decoupling for internal 3.3 V PLL LDO
GND Connect directly to the PCB ground through a low impedance connection.
1 GND External loop filter ground 3, 6 GND Common ground for external loop filter 24, 37 GND If stage, Channel 2 and Channel 1 ground 48 GND External charge pump ground
SPI 17 SDIO SPI port data input/output 18 SCLK SPI port clock 19 CS SPI port chip select
RF, Mixer, IF Path 4, 5 EXTVCOIN+,
EXTVCOIN− External VCO or LO inputs DC block with 100 pF capacitors.
13, 14 LOOUT+, LOOUT− Differential LO outputs DC block with 100 pF capacitors. 22, 23 IFOUT2+, IFOUT2− Channel 2 differential IF outputs Bias to 5 V supply with 330 nH inductors and dc block
with 150 pF capacitors. 25 RFBCT2 Internal mixer bias control for Channel 2 RF
input Decouple to GND with a 10 pF and a 10 nF capacitor, as close to the pin as possible.
26 RFIN2 Channel 2 single-ended RF input DC block with a 22 pF capacitor. 36 RFBCT1 Internal mixer bias control for Channel 1 RF
input Decouple to GND with a 10 pF and a 10 nF capacitor, as close to the pin as possible.
35 RFIN1 Channel 1 single-ended RF input DC block with a 22 pF capacitor. 38, 39 IFOUT1−, IFOUT1+ Channel 1 differential IF outputs Bias to 5 V supply with 330 nH inductors and dc block
with 150 pF capacitors. PLL/VCO
2 VCOVTUNE Control voltage for internal VCO Output from external loop filter. 43 REFIN External reference for internal PLL 47 CPOUT Charge pump output Input to external loop filter.
Other 42 MUXOUT Output for various internal analog signals,
including PLL lock detect and VPTAT Can be read directly from the pin; the user must be careful of loading effects, not a low impedance output.
21, 40 DNC Do not connect
Data Sheet ADRF6612
Rev. A | Page 37 of 57
MIXER OPTIMIZATION RF INPUT BALUN INSERTION LOSS OPTIMIZATION At lower input frequencies, more capacitance is needed. This increase is achieved by programming higher codes into BAL_COUT. At high frequencies, less capacitance is required; therefore, lower BAL_COUT codes are appropriate.
As shown in Figure 96 and Figure 97, this tuning range can be further optimized by adding capacitance across the RF input in conjunction with tuning BAL_COUT. This can help to increase the low frequency range of the device significantly.
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
500 900 1300 1700 2100 2500 2900
RETU
RN L
OSS
(dB)
RF FREQUENCY (MHz)
NO CAP1pF2pF3.3pF
4pF5.6pF6.8pF
1219
9-09
6
Figure 96. Return Loss; Optimum COUT vs. Tuning Capacitor on RFIN Using a
High Side LO
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
500 900 1300 1700 2100 2500 2900
RETU
RN L
OSS
(dB)
RF FREQUENCY (MHz)
NO CAP1pF2pF3.3pF
4pF5.6pF6.8pF
1219
9-09
7
Figure 97. Return Loss; Optimum COUT vs. Tuning Capacitor on RFIN Using a
Low Side LO
IIP3 OPTIMIZATION In applications in which performance is critical, the ADRF6612 offers IIP3 optimization. The IF amplifier bias current can be reduced to trade performance vs. power consumption. This saves on the overall power at the expense of degraded performance.
Figure 98 to Figure 101 show the IIP3 sweeps for all combinations of IFA main bias and linearity bias. The IIP3 vs. IFA main bias and linearity bias figures show both a surface and a contour plot in one figure. The contour plot is located directly underneath the surface plot. The best approach for reading the figure is to localize the
peaks on the surface plot, which indicate maximum IIP3, and to follow the same color pattern to the contour plot to determine the optimized IFA main bias and linearity bias settings.
0
5
10
15
20
25
30
35
0 2 4 6 8 10 12 14 16
IIP3
(dB
m)
IFA_MAIN
IFA_LIN = 0IFA_LIN = 1IFA_LIN = 2IFA_LIN = 3IFA_LIN = 4IFA_LIN = 5IFA_LIN = 6IFA_LIN = 7
IFA_LIN = 8IFA_LIN = 9IFA_LIN = 10IFA_LIN = 11IFA_LIN = 12IFA_LIN = 13IFA_LIN = 14
1219
9-40
0
Figure 98. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level
at IF Frequency = 50 MHz
0
5
10
15
20
25
30
35
0 2 4 6 8 10 12 14 16
IIP3
(dB
m)
IFA_MAIN
IFA_LIN = 0IFA_LIN = 1IFA_LIN = 2IFA_LIN = 3IFA_LIN = 4IFA_LIN = 5IFA_LIN = 6IFA_LIN = 7
IFA_LIN = 8IFA_LIN = 9IFA_LIN = 10IFA_LIN = 11IFA_LIN = 12IFA_LIN = 13IFA_LIN = 14
1219
9-40
1
Figure 99. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level
at IF Frequency = 100 MHz
0
5
10
15
20
25
30
35
0 2 4 6 8 10 12 14 16
IIP3
(dB
m)
IFA_MAIN
IFA_LIN = 0IFA_LIN = 1IFA_LIN = 2IFA_LIN = 3IFA_LIN = 4IFA_LIN = 5IFA_LIN = 6IFA_LIN = 7
IFA_LIN = 8IFA_LIN = 9IFA_LIN = 10IFA_LIN = 11IFA_LIN = 12IFA_LIN = 13IFA_LIN = 14
1219
9-40
2
Figure 100. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level
at IF Frequency = 150 MHz
ADRF6612 Data Sheet
Rev. A | Page 38 of 57
0
5
10
15
20
25
30
35
0 2 4 6 8 10 12 14 16
IIP3
(dB
m)
IFA_MAIN
IFA_LIN = 0IFA_LIN = 1IFA_LIN = 2IFA_LIN = 3IFA_LIN = 4IFA_LIN = 5IFA_LIN = 6IFA_LIN = 7
IFA_LIN = 8IFA_LIN = 9IFA_LIN = 10IFA_LIN = 11IFA_LIN = 12IFA_LIN = 13IFA_LIN = 14
1219
9-40
3
Figure 101. IIP3 vs. Main (IFA_MAIN) and Linearity Bias (IFA_LIN) Level
at IF Frequency = 200 MHz
VGS PROGRAMMING The ADRF6612 allows programmability for internal gate-to-source voltages for optimizing mixer performance over the desired frequency bands. The ADRF6612 default VGS setting is 0. Both channels of the ADRF6612 are programmed together using the same VGS setting. Power conversion gain, input IP3 NF, and input P1dB can be optimized, as shown in Figure 40, Figure 41, Figure 43, and Figure 44.
LOW-PASS FILTER PROGRAMMING The ADRF6612 allows programmability for the low-pass filter terminating the mixer output. This filter helps to block sum term mixing products at the expense of some noise figure and gain and can significantly increase input IP3. The ADRF6612 default LPF setting is 0. Both channels of the ADRF6612 are programmed together using the same LPF settings. Power conversion gain, input IP3, NF, and input P1dB can be optimized, as shown in Figure 42, Figure 45, Figure 46, and Figure 49.
Data Sheet ADRF6612
Rev. A | Page 39 of 57
Table 23. Recommended Optimum Settings for High Performance Mode (in Decimal) RF Frequency (MHz) LO Frequency (MHz) IFA_MAINBIAS IFA_LINBIAS BAL_COUT LPF VGS 700 497 5 11 14 4 0 800 597 5 11 14 4 0 900 697 5 11 10 4 0 1000 797 5 11 10 4 0 1100 897 5 15 10 4 0 1200 997 5 15 10 4 0 1300 1097 5 15 10 4 0 1400 1197 5 15 6 4 0 1500 1297 5 15 6 4 0 1600 1397 5 15 4 4 0 1700 1497 5 15 4 4 0 1800 1597 5 15 4 4 0 1900 1697 5 15 4 4 0 2000 1797 5 15 4 4 0 2100 1897 5 15 4 4 0 2200 1997 5 15 4 4 0 2300 2097 5 15 2 4 0 2400 2197 5 15 2 4 0 2500 2297 5 15 2 4 0 2600 2397 5 15 2 4 0 2700 2497 5 15 2 4 0 2800 2597 5 15 2 4 0 2900 2697 5 15 0 4 0 3000 2797 5 15 0 4 0
Table 24. Recommended Optimum Settings for High Efficiency Mode (in Decimal) RF Frequency (MHz) LO Frequency (MHz) IFA_MAINBIAS IFA_LINBIAS BAL_COUT LPF VGS 700 497 5 15 14 4 0 800 597 5 15 14 4 0 900 697 5 15 10 4 0 1000 797 5 15 10 4 0 1100 897 5 15 10 4 0 1200 997 5 15 10 4 0 1300 1097 5 15 10 4 0 1400 1197 7 15 6 4 0 1500 1297 7 15 6 4 0 1600 1397 7 15 4 4 0 1700 1497 7 15 4 4 0 1800 1597 7 15 4 4 0 1900 1697 7 15 4 4 0 2000 1797 7 15 4 4 0 2100 1897 7 15 4 4 0 2200 1997 7 15 4 4 0 2300 2097 13 15 2 4 0 2400 2197 13 15 2 4 0 2500 2297 13 15 2 4 0 2600 2397 13 15 2 4 0 2700 2497 13 15 2 4 0 2800 2597 13 15 2 4 0 2900 2697 13 15 0 4 0 3000 2797 13 15 0 4 0
ADRF6612 Data Sheet
Rev. A | Page 40 of 57
REGISTER SUMMARY Table 25. Register Summary Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 SOFT_RESET [15:8] SOFT_RESET[15:8] 0x0000 R
[7:0] SOFT_RESET[7:0]
0x01 ENABLES [15:8] LO_LDO_EN LO2_ENP BALUN_EN LO1_ENP DIV2P5_EN PWRUPRX LO_PATH_EN 0x0000 RW
[7:0] LO_DRV_EN VCOBUF_LDO_EN REF_BUF_EN VCO_EN DIV_EN CP_EN VCO_LDO_EN LDO_3P3_EN
0x02 INT_DIV [15:8] DIV_MODE INT_DIV[14:8] 0x0058 RW
[7:0] INT_DIV[7:0]
0x03 FRAC_DIV [15:8] FRAC_DIV[15:8] 0x0250 RW
[7:0] FRAC_DIV[7:0]
0x04 MOD_DIV [15:8] MOD_DIV[15:8] 0x0600 RW
[7:0] MOD_DIV[7:0]
0x10 IF_BIAS [15:8] IFA_LIN_HIEFFP IFA_MAIN_HIEFFP IFA_LINSLOPE IFA_MAINSLOPE IFA_LINBIAS[3:2] 0x02B5 RW
[7:0] IFA_LINBIAS[1:0] IFA_LINBIAS_EN IFA_MAINBIAS IFA_MAINBIAS_EN
0x20 CP_CTRL [15:8] UNUSED CSCALE 0x0026 RW
[7:0] BLEED_POLARITY BLEED
0x21 PFD_CTRL1 [15:8] UNUSED REF_MUX_SEL PFD_POLARITY REFSEL[11:8] 0x0003 RW
[7:0] REFSEL[7:0]
0x22 VCO_CTRL1 [15:8] VCO_LDO_R4 VCO_LDO_R2 0x000A RW
[7:0] LO_DRV_LVL LO_DIV VCO_SEL
0x30 BALUN_CTRL [15:8] UNUSED VGS LPF 0x0000 RW
[7:0] BAL_COUT RESERVED
0x40 PFD_CTRL2 [15:8] UNUSED ABLDLY[3] 0x0010 RW
[7:0] ABLDLY[2:0] CPCTRL CLKEDGE
0x42 DITH_CTRL1 [15:8] UNUSED[11:4] 0x000E RW
[7:0] UNUSED[3:0] DITH_EN DITH_MAG DITH_VAL_H
0x43 DITH_CTRL2 [15:8] DITH_VAL_L[15:8] 0x0001 RW
[7:0] DITH_VAL_L[7:0]
0x44 SYNTH_FCNTN_CTRL [15:8] UNUSED[9:2] 0x0000 RW
[7:0] UNUSED[1:0] DIV_SDM_DIS VCOCNT_CG_DIS BANDCAL_CG_DIS SDM_CG_DIS SDM_DIVD_CLR BANDCAL_DIVD_CLR
0x45 VCO_CTRL2 [15:8] UNUSED 0x0020 RW
[7:0] VCO_BAND_SRC BAND
0x46 VCO_CTRL3 [15:8] UNUSED 0x0000 RW
[7:0] VCO_CNTR_DONE VCO_BAND
0x47 VCO_CNTR_CTRL [15:8] UNUSED[11:4] 0x0000 RW
[7:0] UNUSED[3:0] VCO_CNTR_REFCNT VCO_CNTR_CLR VCO_CNTR_EN
0x48 VCO_CNTR_RB [15:8] VCO_CNTR_RB[15:8] 0x0000 R
[7:0] VCO_CNTR_RB[7:0]
0x49 VTUNE_DAC_CTRL [15:8] UNUSED VTUNE_DAC_SLOPE VTUNE_DAC_OFFSET[8] 0x0000 RW
[7:0] VTUNE_DAC_OFFSET[7:0]
0x4A VCO_BUF_LDO [15:8] UNUSED 0x0000 RW
[7:0] VCOBUF_LDO_R4 VCOBUF_LDO_R2
0x7C VARIATION1 [15:8] IS_RESET VCO_SW_CAL VARIANT 0x0000 R
[7:0] BE_VER FE_VER
0x7D VARIATION2 [15:8] SIF_VER PART_ID[11:8] 0x2001 R
[7:0] PART_ID[7:0]
0x7E VARIATION3 [15:8] IS_RESET VCO_SW_CAL VARIANT 0x0001 R
[7:0] BE_VER FE_VER
0x7F VARIATION4 [15:8] SIF_VER PART_ID[11:8] 0x2001 R
[7:0] PART_ID[7:0]
Data Sheet ADRF6612
Rev. A | Page 41 of 57
REGISTER DETAILS Address: 0x00, Reset: 0x0000, Name: SOFT_RESET
Table 26. Bit Descriptions for SOFT_RESET Bits Bit Name Settings Description Reset Access [15:0] SOFT_RESET Soft reset bit 0x0 R 0 Any write to this register will assert soft reset command 0x0 R
Address: 0x01, Reset: 0x0000, Name: ENABLES
Table 27. Bit Descriptions for ENABLES Bits Bit Name Settings Description Reset Access 15 LO_LDO_EN Power up LO LDO 0x0 RW 14 LO2_ENP LO 2 enable 0x0 RW 13 BALUN_EN Input Balun enable 0x0 RW 12 LO1_ENP LO 1 enable 0x0 RW 11 DIV2P5_EN Enable dividers 2.5 V LDO 0x0 RW [10:9] PWRUPRX Power up Rx 0x0 RW 0x0 Power down both mixer channels 0x1 Power up mixer Channel 1 0x2 Power up mixer Channel 2 0x3 Power up both mixer channels 8 LO_PATH_EN External LO path enable 0x0 RW 7 LO_DRV_EN LO driver enable 0x0 RW
ADRF6612 Data Sheet
Rev. A | Page 42 of 57
Bits Bit Name Settings Description Reset Access 6 VCOBUF_LDO_EN VCO buffer LDO enable 0x0 RW 5 REF_BUF_EN Reference buffer enable 0x0 RW 4 VCO_EN Power up VCOs 0x0 RW 3 DIV_EN Power up dividers 0x0 RW 2 CP_EN Power up charge pump 0x0 RW 1 VCO_LDO_EN Power up VCO LDO 0x0 RW 0 LDO_3P3_EN Power up 3.3 V LDO 0x0 RW
Address: 0x02, Reset: 0x0058, Name: INT_DIV
Table 28. Bit Descriptions for INT_DIV Bits Bit Name Settings Description Reset Access 15 DIV_MODE Set fractional/integer mode 0x0 RW 0 Fractional 1 Integer [14:0] INT_DIV Set divider INT value 0x58 RW
Address: 0x03, Reset: 0x0250, Name: FRAC_DIV
Table 29. Bit Descriptions for FRAC_DIV Bits Bit Name Settings Description Reset Access [15:0] FRAC_DIV Set divider FRAC value 0x250 RW
Address: 0x04, Reset: 0x0600, Name: MOD_DIV
Table 30. Bit Descriptions for MOD_DIV Bits Bit Name Settings Description Reset Access [15:0] MOD_DIV Set divider MOD value 0x600 RW
Data Sheet ADRF6612
Rev. A | Page 43 of 57
Address: 0x10, Reset: 0x02B5, Name: IF_BIAS
Table 31. Bit Descriptions for IF_BIAS Bits Bit Name Settings Description Reset Access 15 IFA_LIN_HIEFFP Linearity RDAC: 0 = high performance mode, 1 = high efficiency mode 0x0 RW 14 IFA_MAIN_HIEFFP Main RDAC: 0 = high performance mode, 1 = high efficiency mode 0x0 RW [13:12] IFA_LINSLOPE Linearity Slope Adj for IF amps (IPMix) 0x0 RW [11:10] IFA_MAINSLOPE Main Slope Adj for IF amps (IPMix) 0x0 RW [9:6] IFA_LINBIAS Linearity Bias Adj for IF amps (IPMix) 0xa RW 5 IFA_LINBIAS_EN Enable internal Linearity Bias Adj for IF amps (IPMix) 0x1 RW [4:1] IFA_MAINBIAS Main Bias Adj for IF Amps (IPMix) 0xa RW 0 IFA_MAINBIAS_EN Enable internal Main Bias Adj for IF amps (IPMix) 0x1 RW
Address: 0x20, Reset: 0x0026, Name: CP_CTRL
Table 32. Bit Descriptions for CP_CTRL Bits Bit Name Settings Description Reset Access [15:14] UNUSED Unused 0x0 RW [13:8] CSCALE Charge pump current adjust 0x0 RW 7 BLEED_POLARITY Charge pump bleed current polarity 0x0 RW [6:0] BLEED Charge pump bleed 0x26 RW
ADRF6612 Data Sheet
Rev. A | Page 44 of 57
Address: 0x21, Reset: 0x0003, Name: PFD_CTRL1
Table 33. Bit Descriptions for PFD_CTRL1 Bits Bit Name Settings Description Reset Access 15 UNUSED Unused 0x0 RW [14:13] REF_MUX_SEL REF output divide ratio/VPTAT/SCAN/LOCK_DET 0x0 RW 000 LOCK_DET 001 VPTAT 010 REFCLK 011 REFCLK/2 100 REFCLKx2 101 REFCLK/8 110 REFCLK/4 111 SCAN 12 PFD_POLARITY PFD polarity 0x0 RW 0 POS 1 NEG [11:0] REFSEL REF input divide ratio 0x3 RW
Data Sheet ADRF6612
Rev. A | Page 45 of 57
Address: 0x22, Reset: 0x000A, Name: VCO_CTRL1
VCO LDO R4 control setting Select VCO core/external LO
111: None.110: External LO/VCO.101: None.100: None.011: VCO_3 = 2.85 GHz to 3.5 GHz.010: VCO_2 = 3.5 GHz to 4.02 GHz.001: VCO_1 = 4.02 GHz to 4.6 GHz.000: VCO_0 = 4.6 GHz to 5.7 GHz.
VCO LDO R2 control setting
LO_DIV
11: DIV8.10: DIV4.01: DIV2.00: DIV1.
External LO amplitude
11: 9.2 dBm/49 mA.10: 7.5 dBm/40 mA.01: 4.6 dBm/28 mA.00: -0.8 dBm/15 mA.
0
01
12
03
14
05
06
07
08
09
010
011
012
013
014
015
0
[15:12] VCO_LDO_R4 (R/W) [2:0] VCO_SEL (R/W)
[11:8] VCO_LDO_R2 (R/W)
[5:3] LO_DIV (R/W)
[7:6] LO_DRV_LVL (R/W)
Table 34. Bit Descriptions for VCO_CTRL1 Bits Bit Name Settings Description Reset Access [15:12] VCO_LDO_R4 VCO LDO R4 control setting 0x0 RW [11:8] VCO_LDO_R2 VCO LDO R2 control setting 0x0 RW [7:6] LO_DRV_LVL External LO amplitude 0x0 RW 00 −0.8 dBm/15 mA 01 4.6 dBm/28 mA 10 7.5 dBm/40 mA 11 9.2 dBm/49 mA [5:3] LO_DIV LO_DIV 0x1 RW 00 DIV1 01 DIV2 10 DIV4 11 DIV8 [2:0] VCO_SEL Select VCO core/external LO 0x2 RW 000 VCO_0 = 4.6 GHz to 5.7 GHz 001 VCO_1 = 4.02 GHz to 4.6 GHz 010 VCO_2 = 3.5 GHz to 4.02 GHz 011 VCO_3 = 2.85 GHz to 3.5 GHz 100 None 101 None 110 External LO/VCO 111 None
ADRF6612 Data Sheet
Rev. A | Page 46 of 57
Address: 0x30, Reset: 0x0000, Name: BALUN_CTRL
Table 35. Bit Descriptions for BALUN_CTRL Bits Bit Name Settings Description Reset Access [15:14] UNUSED Unused 0x0 RW [13:11] VGS Mixer VGS bias 0x0 RW [10:8] LPF Mixer output IF low-pass filter 0x0 RW [7:4] BAL_COUT Set balun COUT (both channels) 0x0 RW [3:0] RESERVED Reserved, set to 0x0 0x0 RW
Address: 0x40, Reset: 0x0010, Name: PFD_CTRL2
Table 36. Bit Descriptions for PFD_CTRL2 Bits Bit Name Settings Description Reset Access [15:9] UNUSED Unused 0x0 RW [8:5] ABLDLY Set antibacklash delay 0x0 RW 00 0 ns 01 0.5 ns 10 0.75 ns 11 0.9 ns
Data Sheet ADRF6612
Rev. A | Page 47 of 57
Bits Bit Name Settings Description Reset Access [4:2] CPCTRL Set charge pump control 0x4 RW 000 Both ON 001 Pump DWN 010 Pump UP 011 Tristate 100 PFD 101 110 111 [1:0] CLKEDGE Set PFD edge sensitivity 0x0 RW 00 Div and REF DWN edge 01 Div DWN edge, REF UP edge 10 Div UP edge, REF DWN edge 11 Div and REF UP edge
Address: 0x42, Reset: 0x000E, Name: DITH_CTRL1
Table 37. Bit Descriptions for DITH_CTRL1 Bits Bit Name Settings Description Reset Access [15:4] UNUSED Unused register bits 0x0 RW 3 DITH_EN Set dither enable 0x1 RW 0 Disable 1 Enable [2:1] DITH_MAG Dither magnitude 0x3 RW 0 DITH_VAL_H High bit of 17 bit dither value 0x0 RW
Address: 0x43, Reset: 0x0001, Name: DITH_CTRL2
Table 38. Bit Descriptions for DITH_CTRL2 Bits Bit Name Settings Description Reset Access [15:0] DITH_VAL_L Low 16 bits of 17 bit dither value 0x1 RW
ADRF6612 Data Sheet
Rev. A | Page 48 of 57
Address: 0x44, Reset: 0x0000, Name: SYNTH_FCNTN_CTRL
Table 39. Bit Descriptions for SYNTH_FCNTN_CTRL Bits Bit Name Settings Description Reset Access [15:6] UNUSED Unused 0x0 RW 5 DIV_SDM_DIS Disable SDM divider 0x0 RW 4 VCOCNT_CG_DIS Disable BIST clock 0x0 RW 3 BANDCAL_CG_DIS Disable bandcal clock 0x0 RW 2 SDM_CG_DIS Disable SDM clock 0x0 RW 1 SDM_DIVD_CLR SDM_DIVD_CLR 0x0 RW 0 BANDCAL_DIVD_CLR BANDCAL_DIVD_CLR 0x0 RW
Address: 0x45, Reset: 0x0020, Name: VCO_CTRL2
Table 40. Bit Descriptions for VCO_CTRL2 Bits Bit Name Settings Description Reset Access [15:8] UNUSED Unused 0x0 RW 7 VCO_BAND_SRC Set VCO band source 0x0 RW 0 Automatic 1 Manual [6:0] BAND Set VCO band 0x20 RW
Data Sheet ADRF6612
Rev. A | Page 49 of 57
Address: 0x46, Reset: 0x0000, Name: VCO_CTRL3
Table 41. Bit Descriptions for VCO_CTRL3 Bits Bit Name Settings Description Reset Access [15:8] UNUSED Unused 0x0 RW 7 VCO_CNTR_DONE Read back BIST counter status 0x0 R [6:0] VCO_BAND Read back output of bandcap mux 0x0 R
Address: 0x47, Reset: 0x0000, Name: VCO_CNTR_CTRL
Table 42. Bit Descriptions for VCO_CNTR_CTRL Bits Bit Name Settings Description Reset Access [15:4] UNUSED Unused 0x0 RW [3:2] VCO_CNTR_REFCNT BIST counter integration interval 0x0 RW 1 VCO_CNTR_CLR Clear BIST counter 0x0 RW 0 VCO_CNTR_EN Enable BIST counter 0x0 RW
Address: 0x48, Reset: 0x0000, Name: VCO_CNTR_RB
Table 43. Bit Descriptions for VCO_CNTR_RB Bits Bit Name Settings Description Reset Access [15:0] VCO_CNTR_RB Read back output of BIST counter 0x0 R
ADRF6612 Data Sheet
Rev. A | Page 50 of 57
Address: 0x49, Reset: 0x0000, Name: VTUNE_DAC_CTRL
Table 44. Bit Descriptions for VTUNE_DAC_CTRL Bits Bit Name Settings Description Reset Access [15:14] UNUSED Unused 0x0 RW [13:9] VTUNE_DAC_SLOPE Set VTUNE PTAT DAC 0x0 RW [8:0] VTUNE_DAC_OFFSET Set VTUNE ZTAT DAC 0x0 RW
Address: 0x4A, Reset: 0x0000, Name: VCO_BUF_LDO
Table 45. Bit Descriptions for VCO_BUF_LDO Bits Bit Name Settings Description Reset Access [15:8] UNUSED Unused 0x0 RW [7:4] VCOBUF_LDO_R4 VCOBUF LDO R4 control 0x0 RW [3:0] VCOBUF_LDO_R2 VCOBUF LDO R2 control 0x0 RW
Address: 0x7C, Reset: 0x0000, Name: VARIATION1
Table 46. Bit Descriptions for VARIATION1 Bits Bit Name Settings Description Reset Access 15 IS_RESET IS reset 0x0 R 14 VCO_SW_CAL VCO switch calibration 0x0 R [13:8] VARIANT Experimental variant 0x0 R [7:4] BE_VER Back end of line revision 0x0 R [3:0] FE_VER Front end of line revision 0x0 R
Data Sheet ADRF6612
Rev. A | Page 51 of 57
Address: 0x7D, Reset: 0x2001, Name: VARIATION2
Table 47. Bit Descriptions for VARIATION2 Bits Bit Name Settings Description Reset Access [15:12] SIF_VER Serial interface version 0x2 R [11:0] PART_ID Product ID 0x1 R
Address: 0x7E, Reset: 0x0001, Name: VARIATION3
Table 48. Bit Descriptions for VARIATION3 Bits Bit Name Settings Description Reset Access 15 IS_RESET IS reset 0x0 R 14 VCO_SW_CAL VCO switch calibration 0x0 R [13:8] VARIANT Experimental variant 0x0 R [7:4] BE_VER Back end of line revision 0x0 R [3:0] FE_VER Front end of line revision 0x1 R
Address: 0x7F, Reset: 0x2001, Name: VARIATION4
Table 49. Bit Descriptions for VARIATION4 Bits Bit Name Settings Description Reset Access [15:12] SIF_VER Serial interface version 0x2 R [11:0] PART_ID Product ID 0x1 R
ADRF6612 Data Sheet
Rev. A | Page 52 of 57
EVALUATION BOARD An evaluation board is available for the ADRF6612. The standard evaluation board schematic is presented in Figure 102. The USB interface circuitry schematic is presented in Figure 104. The evaluation board layout is shown in Figure 105 and Figure 106.
The evaluation board is fabricated using Rogers® 3003 material. Table 50 details the configuration for the mixer characterization. The evaluation board software is available on the ADRF6612 product page.
CLOSE AS POSSIBLE TO THE PINS ON THE CHIP
PLL REF IN
(VCC2LO3)
(VCC2LO4)
THESE SIX 10PF CAPS
SHOULD BE LOCATED AS
CLOSE AS POSSIBLE TO
(VCC5PLL)
(VCC5SPI)
(VCCIF2)
(VCC1LO4)
(VCC1LO3)
(VCC1LO2)
(VCC5DIV)
(VCC2LO2)
PINS 27,28,29,32,33,34
IF OUTPUT 1
(VCCIF1)
IF OUTPUT 2
ALL 100PF DECOUPLING CAPS SHOULD BE AS
(VCC5VCO)
EXT VCO OUTPUT
DNI
.033UF
0
BLK
1500PF
910
1.8K
BLK
22PF
SML-210MTT86
JOHNSON142-0701-851
330NH
22PF
0.1UF
BLU
20K
0
50
DNI
1K
1K DNI
1KDNI
DNI
1K
00
0
DNI
0
0
DNI
00
0
0DNI
0
10UF
10UF
10UF
10UF
10UF
10UF
10UF
TC4-1W+
TC4-1W+
0.1UF
150PF
150PF
TBD0805
DNI
100PF
100PF
100PF
1000PF
10000PF
150PF
100PF
150PF
0.1UF
330NH
BLK
0.1UF
100PF
330NH
150PF
150PF
AT224-1
10UF
10UF
10UF
RED
RED
RED
100PF
100PF
100PF
100PF
BLU
10PF
BLU
10000PF
0.1UF
100PF
0.1UF
100PF
TC1-1-43A+
150PF
150PF
10PF
0.1UF
10PF
0.1UF
10PF
0.1UF
10PF
0.1UF
10PF
0.1UF
10PF
0.1UF
10PF
0.1UF
100PF
100PF
150PF
150PF
330NH
JOHNSON142-0701-851
JOHNSON142-0701-851
DNI
JOHNSON142-0701-851
JOHNSON142-0701-851
JOHNSON142-0701-851
JOHNSON142-0701-851
JOHNSON142-0701-851
DNI
JOHNSON142-0701-851
JOHNSON142-0701-851
2K
TC1-1-43A+
AT224-1
100PF
BLU
10PF
10UF
100PF
100PF
BLK
100PF
0.1UF
100PF
ADRF
6612
ACPZ
560PF
39PF
C9C3
C27
C25
C31
C28
C11
C12
C6
C17
C16
C41
C45
T5C3
8
C39
L3 L4
C35
C34
C30
R18
R16
IF2P
IF2N
EXT_
LOIN
LO_O
UT
RF_I
N2
C43
C42
RF_I
N1
C40
C44
IF1P IF
1N
R17
R15
T4C3
6
C37
L1 L2
C33
C32
C29
C21
C19
MUX
_OUT
PLL_
REF_
IN
R19
C54
C7C2
C15
T1
T2
C59
C60
C82
R35
GND3
R36 CR
3
GND4
GND2
GND1
R38
R39
R37 R4
0
R41
C89
C26
C24
C51
C4
C52
C10
C53
C46
C55
C47
C56
C48
C90
C49
C91
C50
VCC_
LO
C92
VTUN
E
C100
C102
C101
C103
C105
C104
C14
C108
C107
C5
R93
R94
TP4
R95
TP5
R96
C58
C57
R97
R98
CPOU
T
VCC_
IFVC
C_SY
NTH
C1C8
R10
R8
R7
C23
C18
U1
C20
C22
VCOTUNE
VCC_SYNTH
IF2N
IF2P
IF1N
IF1P
PLL_REF_IN
VCC_IF
VCC_IF
VCC_IF
VCC_IF
VCC_SYNTH
VCC_SYNTH
VCC_SYNTH
VCC_LO
VCC_LO
VCC_LO
VCC_SYNTH
VCC_LO
VCC_LO
VCC_LO
LDO3P3DIV
VCC_LO
VCC_IF
LDO2P5SPI
LDO2P5PLL
LDO3P3PLL
MUXOUT
LDO2P5SPIVCC_SYNTH
DATACLKLE
VCC_IF
VCC_LO
VCC_LO
LDO3P3DIV
VCC_SYNTH
VCC_LO
VCC_LO
VCC_LO
VCC_IF
LDO2P5PLLLDO3P3PLLVCC_SYNTH
CPOUT
VCC_SYNTH
VCC_LO
46
2 31
1
23
45
1
23
45
1
23
45
1
23
45
1
23
45
1
23
45
1
23
45
1
23
45
46
2 31
1
23
45
1
23
45
1 346
1 346
1
CA
111
1
P N
1
1
1
1
11
P NP N
47
10
PAD
4243
36 25
1817
2
19
8 9
11 12
2140
4 51 3 6
2437
48
3938
2322
15
30
4445
1314
35 26
7
16
20
27282931323334
41
46
AGND
AGND
AGND
AGND
AGND
EPGND
CPOUTVCC12LDO4LDO3
REFINMUXOUT
VCC11DNC
IFOUT1+IFOUT1-
GND RFBC
T1RF
IN1
VCC1
0VC
C9VC
C8VC
C7LD
O2VC
C6VC
C5VC
C4RF
IN2
RFBC
T2
GNDIFOUT2-IFPOUT2+DNCVCC3CS_NSCLKSDIOVCC2LDO1LOOUT-LOOUT+
DECL
5DE
CL4
DECL
3DE
CL2
DECL
1VC
C1GN
DEX
TVCO
IN-
EXTV
COIN
+GN
DVC
OVTU
NEGN
D
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AG
ND
AGND AG
ND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGNDAG
ND
SE
CP
RI
SE
CP
RI
AGND
AGND
AGND
AGND
AGND
AGND
AGND
12199-092
Figure 102. Evaluation Board, Main Circuitry
Data Sheet ADRF6612
Rev. A | Page 53 of 57
330PF
330PF
DECOUPLING FOR U1
330PF
78.7K
2K2K
2K
2K
1K DNI
1K DNI
DNI
1K
897-43-005-00-100001
JPR0402
JPR0402
JPR0402
1UF
BLK
1000PF
SNS
DNI
BLK
CY7C68013A-56LTXC
TBD0402
24LC64-I-SN
10PF
0.1UF
0.1UF
0.1UF
10PF
22PF
24.000000MEGHZ
DNI
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
ADP3334ACPZ
0.1UF
22PF
TBD0402
DNI
DNI
SML-210MTT86
SML-210MTT86
DNI
TBD0402
0.1UF
100K
100K
140K
JP3
JP2
JP1
R25
C76
R22
C79
C71
Y1
C70
P2
C62
C69
C75
R30
C74
R31
R27
R28
C73
C72
U2
CR2
R29
R24
C78
U4
TP1
SNS1
TP2
R33
R21
U3
C68
C66
C67
C64
C65
C61
C63
CR1
C77
R32
C80
C81
LE
5V_USB
CLK
DATA
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
3V3_USB
5V_USB
21
21
21
31
42
54321 G4G3G2G1
7
8
56
4
321
A C
4 5
44
55
43
32
27
17
11
1615
42
1421
5251504948474645
2524232221201918
PAD
40 39 38 37 36 35 34 33
13
56
53
41
28
26
128 9
31 30 29
54
73 106
1
21
1
6 PAD
2187
5
3
A C
IN1
IN2
OUT2
OUT1
PAD
FBGN
DSD
_N
DGND
DGND
DGND
DGND
DGND
DGND
AGND
DGND
DGND
DGND
DGND
DGND
DGNDCA
SE
DGND
DGND
PIN
SG
ND
DGND
DGNDDG
ND
DGND
DGND
DGND
DGND
GND
SCL
SDA
WC_
N
A2A1A0VC
C
DGND
DGND
PADGNDVCC
CLKOUTGND
PD7_FD15PD6_FD14PD5_FD13PD4_FD12PD3_FD11PD2_FD10
PD1_FD9PD0_FD8WAKEUP
VCC
RESE
T_N
GND
PA7_
FLAG
D_SL
CS_N
PA6_
PKTE
NDPA
5_FI
FOAD
R1PA
4_FI
FOAD
R0PA
3_W
U2PA
2_SL
OEPA
1_IN
T1_N
PA0_
INT0
_NVC
CCT
L2_F
LAGC
CTL1
_FLA
GBCT
L0_F
LAGA
GNDVCCGNDPB7_FD7PB6_FD6PB5_FD5PB4_FD4PB3_FD3PB2_FD2PB1_FD1PB0_FD0VCCSDASCL
RESE
RVED
IFCL
KGN
DVC
CAG
NDDM
INUS
DPLU
SAV
CCAG
NDXT
ALIN
XTAL
OUT
AVCC
RDY1
_SLW
RRD
Y0_S
LRD
DGND
DGND
12199-093
Figure 103. Evaluation Board, Legacy USB Interface
ADRF6612 Data Sheet
Rev. A | Page 54 of 57
TBD0
603
100K
0DN
I
0DN
I
0
JPR0
402
FX8-
120S
-SV(
21)
JPR0
402
JPR0
402
DGND
E014
160
24LC
32A-
I/MS
DGND
FX8-
120S
-SV(
21)
100K
DNI
DNI
DNI
DNI
DNI
DNI
JEDE
C_TY
PE=M
SOP8
DNI
DNI
DNI
R1
R10
0
R6
JP6
TP6
R34
TP7
JP4
R9
R99
U11
P7
TP8
JP5
P7
VCC_
SYNT
H
DATA
_SDP
LE_S
DPLE
DATA
CLK
CLK_
SDP
21
21
7
48
56321
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
21
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VSS
VCC
WP
A2A1A0 SCL
SDA
DG
ND
DG
ND
DG
ND
12199-094
Figure 104. Evaluation Board, ADI SDP-S USB Interface
Data Sheet ADRF6612
Rev. A | Page 55 of 57
Table 50. Evaluation Board Configuration Components Description Default Conditions C1, C2, C8, C11, C12, C13, C14, C15, C18, C19, C20, C23, C26, C27
Power supply decoupling. Nominal supply decoupling consists of a 0.1 µF capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible.
C1, C2, C26, C27 = 0.1 µF (size 0402), C8, C11, C12, C13, C14, C15, C18, C19, C20, C23 = 10 pF (size 0402)
C6, C7, C24, C25 RF input interface. The input channels are ac-coupled through C6 and C24. C7 and C25 provide bypassing for the center tap of the RF input baluns.
C6, C24 = 22 pF (size 0402), C7, C25 = 22 pF (size 0402)
C3, C4, C5, C28, C29, C30, L1, L2, L3, L4, R20, R21, R22, R23, T1, T2
IF output interface. The open-collector IF output interfaces are biased through pull-up choke inductors L1, L2, L3, and L4. T1 and T2 are 4:1 impedance transformers used to provide single-ended IF output interfaces, with C5 and C30 providing center-tap bypassing. Remove R21 and R22 for balanced output operation.
C3, C4, C5, C28, C29, C30 = 120 pF (size 0402), L1, L2, L3, L4 = 470 nH (size 0603), R20, R23 = open, R21, R22 = 0 Ω (size 0402), T1, T2 = TC4-1W+ (Mini-Circuits®)
C17 LO interface. C17 provides ac coupling for the LOIP local oscillator input. C17 = 22 pF (size 0402) R1, R2 Bias control. R1and R2 set the bias point for the internal IF amplifier. R1, R2 = 910 Ω (size 0402)
1219
9-20
5
Figure 105. Evaluation Board, Top Layer
ADRF6612 Data Sheet
Rev. A | Page 56 of 57
1219
9-20
6
Figure 106. Evaluation Board, Bottom Layer
Data Sheet ADRF6612
Rev. A | Page 57 of 57
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4.
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
1
0.50BSC
BOTTOM VIEWTOP VIEW
PIN 1INDICATOR
48
1324
3637
PIN 1INDICATOR
5.705.60 SQ5.50
0.500.400.30
SEATINGPLANE
0.800.750.70 0.05 MAX
0.02 NOM
0.203 REF
COPLANARITY0.08
0.300.250.18
02-2
9-20
16-A
7.107.00 SQ6.90
0.20 MIN
5.50 REF
END VIEW
EXPOSEDPAD
PKG
-004
452
Figure 107. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADRF6612ACPZ-R7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13 ADRF6612-EVALZ Evaluation Board 1 Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12199-0-5/16(A)