8-Channel, 24-Bit, Simultaneous Sampling ADC
Data Sheet AD7771
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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FEATURES 8-channel, 24-bit simultaneous sampling ADC Single-ended or true differential inputs PGA per channel (gains of 1, 2, 4, and 8) Low dc input current
±4 nA (differential)/±8 nA (single-ended) Up to 128 kSPS ODR per channel Programmable ODRs and bandwidth SRC for coherent sampling
Sampling rate resolution up to 15.2 × 10−6 SPS Low latency sinc3 and sinc5 filter paths Adjustable phase synchronization Internal 2.5 V reference Two power modes
High resolution mode Low power mode
Optimizes power dissipation and performance Low resolution SAR ADC for system and chip diagnostics Power supply
Bipolar (±1.65 V) or unipolar (3.3 V) supplies Digital I/O supply: 1.8 V to 3.6 V Performance temperature range: −40°C to +105°C Functional temperature range: −40°C to +125°C
Performance Combined ac and dc performance 107 dB SNR/dynamic range at 32 kSPS in high resolution
mode (sinc5) −109 dB THD ±8 ppm of FSR INL ±15 µV offset error ±0.1% FS gain error ±10 ppm/°C typical temperature coefficient
APPLICATIONS Power quality and measurement applications General-purpose data acquisition Electroencephalography (EEG) Industrial process control
GENERAL DESCRIPTION The AD77711 is an 8-channel, simultaneous sampling analog-to-digital converter (ADC). Eight full Σ-Δ ADCs are on-chip. The AD7771 provides an ultralow input current to allow direct sensor connection. Each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor outputs into the full-scale ADC input range, maximizing the dynamic range of the signal chain. The AD7771 accepts a VREF
voltage from 1 V up to 3.6 V. The analog inputs accept unipolar (0 V to VREF) or true bipolar (±VREF/2 V) analog input signals with 3.3 V or ±1.65 V analog supply voltages, respectively. The analog inputs can be configured to accept true differential or single-ended signals to match different sensor output configurations. Each channel contains an ADC modulator and a sinc3/sinc5, low latency digital filter. A sample rate converter (SRC) is provided to allow fine resolution control over the AD7771 output data rate (ODR). This control can be used in applications where the ODR resolution is required to maintain coherency with 0.01 Hz changes in the line frequency. The SRC is programmable through the serial port interface (SPI). The AD7771 implements two different interfaces: a data output interface and SPI control interface. The ADC data output interface is dedicated to trans-mitting the ADC conversion results from the AD7771 to the processor. The SPI writes to and reads from the AD7771 configuration registers and for the control and reading of data from the successive approximation register (SAR) ADC. The SPI can also be configured to output the Σ-Δ conversion data.
The AD7771 includes a 12-bit SAR ADC. This ADC can be used for AD7771 diagnostics without having to decommission one of the Σ-Δ ADC channels dedicated to system measurement func-tions. With the use of an external multiplexer, which can be controlled through the three general-purpose input/output pins (GPIOs), and signal conditioning, the SAR ADC can validate the Σ-Δ ADC measurements in applications where functional safety is required. In addition, the AD7771 SAR ADC includes an internal multiplexer to sense internal nodes. The AD7771 contains a 2.5 V reference and reference buffer. The reference has a typical temperature coefficient of ±10 ppm/°C. The AD7771 offers two modes of operation: high resolution mode and low power mode. High resolution mode provides a higher dynamic range while consuming 16.6 mW per channel; low power mode consumes only 5.25 mW per channel at a reduced dynamic range specification.
The specified operating temperature range is −40°C to +105°C, although the device is operational up to +125°C. Note that throughout this data sheet, certain terms are used to refer to either the multifunction pins or a range of pins. The multifunction pins, such as DCLK0/SDO, are referred to either by the entire pin name or by a single function of the pin, for example, DCLK0, when only that function is relevant. In the case of ranges of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4.
1 This product is protected by at least U.S. Patent No. 9.432,043.
AD7771* PRODUCT PAGE QUICK LINKSLast Content Update: 07/28/2017
COMPARABLE PARTSView a parametric search of comparable parts.
EVALUATION KITS• AD7770 / AD7771 / AD7779 Evaluation Board
• AD7771 Evaluation Board
DOCUMENTATIONApplication Notes
• AN-1388: Coherent Sampling for Power Quality Measurements Using the AD7779 24-Bit Simultaneous Sampling Sigma-Delta ADC
• AN-1392: How to Calculate Offset Errors and Input Impedance in ADC Converters with Chopped Amplifiers
• AN-1393: Translating System Level Protection and Measurement Requirements to ADC Specifications
• AN-1405: Diagnostic Features on the AD7770 and AD7779
Data Sheet
• AD7771: 8-Channel, 24-Bit Simultaneous Sampling ADCs Data Sheet
User Guides
• UG-884: Evaluating the AD7770, AD7771, and AD7779 8-Channel, 24-Bit, Simultaneous Sampling, Sigma-Delta ADCs with Power Scaling
SOFTWARE AND SYSTEMS REQUIREMENTS• AD7770/AD7771/AD7779 - No-OS Driver
TOOLS AND SIMULATIONS• AD7770/AD7771/AD7779 Filter Model
• AD7771 CRC Calculator
• AD7770/AD7771/AD7779 IBIS Model
REFERENCE MATERIALSPress
• Analog Devices Improves Monitoring and Protection of Smart Grid Transmission and Distribution Equipment
DESIGN RESOURCES• AD7771 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONSView all AD7771 EngineerZone Discussions.
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AD7771 Data Sheet
Rev. 0 | Page 2 of 98
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5
DOUTx Timing Characterististics ............................................. 9 SPI Timing Characterististics ................................................... 10 Synchronization Pins and Reset Timing Characteristics ...... 11 SAR ADC Timing Characterististics ....................................... 12 GPIO SRC Update Timing Characterististics......................... 12
Absolute Maximum Ratings .......................................................... 13 Thermal Resistance .................................................................... 13 ESD Caution ................................................................................ 13
Pin Configuration and Function Descriptions ........................... 14 Typical Performance Characteristics ........................................... 17 Terminology .................................................................................... 32 Theory of Operation ...................................................................... 34
Analog Inputs .............................................................................. 34 Transfer Function ....................................................................... 35 Core Signal Chain....................................................................... 36 Capacitive PGA ........................................................................... 36 Internal Reference and Reference Buffers ............................... 36 Integrated LDOs ......................................................................... 37 Clocking and Sampling .............................................................. 37 Digital Reset and Synchronization Pins .................................. 37 Digital Filtering ........................................................................... 38 Shutdown Mode .......................................................................... 38 Controlling the AD7771 ............................................................ 39 Pin Control Mode ....................................................................... 39 SPI Control .................................................................................. 42 Digital SPI .................................................................................... 44
RMS Noise and Resolution............................................................ 47 High Resolution Mode ............................................................... 47 Low Power Mode ........................................................................ 48
Diagnostics and Monitoring ......................................................... 49 Self Diagnostics Error ................................................................ 49 Monitoring Using the AD7771 SAR ADC (SPI Control Mode) ........................................................................................... 50 Σ-Δ ADC Diagnostics (SPI Control Mode) ............................ 52
Σ-∆ Output Data............................................................................. 53 ADC Conversion Output—Header and Data ........................ 53 Sample Rate Converter (SRC) (SPI Control Mode) .............. 54 Data Output Interface ................................................................ 56 Calculating the CRC Checksum .............................................. 60
Register Summary .......................................................................... 61 Register Details ............................................................................... 65
Channel 0 Configuration Register ........................................... 65 Channel 1 Configuration Register ........................................... 65 Channel 2 Configuration Register ........................................... 66 Channel 3 Configuration Register ........................................... 66 Channel 4 Configuration Register ........................................... 67 Channel 5 Configuration Register ........................................... 67 Channel 6 Configuration Register ........................................... 68 Channel 7 Configuration Register ........................................... 68 Disable Clocks to ADC Channel Register .............................. 69 Channel 0 Sync Offset Register ................................................ 69 Channel 1 Sync Offset Register ................................................ 69 Channel 2 Sync Offset Register ................................................ 69 Channel 3 Sync Offset Register ................................................ 70 Channel 4 Sync Offset Register ................................................ 70 Channel 5 Sync Offset Register ................................................ 70 Channel 6 Sync Offset Register ................................................ 70 Channel 7 Sync Offset Register ................................................ 70 General User Configuration 1 Register ................................... 71 General User Configuration 2 Register ................................... 72 General User Configuration 3 Register ................................... 73 Data Output Format Register ................................................... 73 Main ADC Meter and Reference Mux Control Register ...... 74 Global Diagnostics Mux Register ............................................. 75 GPIO Configuration Register ................................................... 75 GPIO Data Register.................................................................... 76 Buffer Configuration 1 Register ............................................... 76 Buffer Configuration 2 Register ............................................... 76 Channel 0 Offset Upper Byte Register..................................... 77 Channel 0 Offset Middle Byte Register ................................... 77 Channel 0 Offset Lower Byte Register ..................................... 77 Channel 0 Gain Upper Byte Register ....................................... 77 Channel 0 Gain Middle Byte Register ..................................... 77 Channel 0 Gain Lower Byte Register ....................................... 78
Data Sheet AD7771
Rev. 0 | Page 3 of 98
Channel 1 Offset Upper Byte Register ..................................... 78 Channel 1 Offset Middle Byte Register .................................... 78 Channel 1 Offset Lower Byte Register ..................................... 78 Channel 1 Gain Upper Byte Register........................................ 78 Channel 1 Gain Middle Byte Register ...................................... 79 Channel 1 Gain Lower Byte Register ........................................ 79 Channel 2 Offset Upper Byte Register ..................................... 79 Channel 2 Offset Middle Byte Register .................................... 79 Channel 2 Offset Lower Byte Register ..................................... 79 Channel 2 Gain Upper Byte Register........................................ 80 Channel 2 Gain Middle Byte Register ...................................... 80 Channel 2 Gain Lower Byte Register ........................................ 80 Channel 3 Offset Upper Byte Register ..................................... 80 Channel 3 Offset Middle Byte Register .................................... 80 Channel 3 Offset Lower Byte Register ..................................... 81 Channel 3 Gain Upper Byte Register........................................ 81 Channel 3 Gain Middle Byte Register ...................................... 81 Channel 3 Gain Lower Byte Register ........................................ 81 Channel 4 Offset Upper Byte Register ..................................... 81 Channel 4 Offset Middle Byte Register .................................... 82 Channel 4 Offset Lower Byte Register ..................................... 82 Channel 4 Gain Upper Byte Register........................................ 82 Channel 4 Gain Middle Byte Register ...................................... 82 Channel 4 Gain Lower Byte Register ........................................ 82 Channel 5 Offset Upper Byte Register ..................................... 83 Channel 5 Offset Middle Byte Register .................................... 83 Channel 5 Offset Lower Byte Register ..................................... 83 Channel 5 Gain Upper Byte Register........................................ 83 Channel 5 Gain Middle Byte Register ...................................... 83 Channel 5 Gain Lower Byte Register ........................................ 84 Channel 6 Offset Upper Byte Register ..................................... 84 Channel 6 Offset Middle Byte Register .................................... 84 Channel 6 Offset Lower Byte Register ..................................... 84 Channel 6 Gain Upper Byte Register........................................ 84 Channel 6 Gain Middle Byte Register ...................................... 85
Channel 6 Gain Lower Byte Register ....................................... 85 Channel 7 Offset Upper Byte Register ..................................... 85 Channel 7 Offset Middle Byte Register .................................... 85 Channel 7 Offset Lower Byte Register ..................................... 85 Channel 7 Gain Upper Byte Register ....................................... 86 Channel 7 Gain Middle Byte Register ...................................... 86 Channel 7 Gain Lower Byte Register ....................................... 86 Channel 0 Status Register .......................................................... 86 Channel 1 Status Register .......................................................... 87 Channel 2 Status Register .......................................................... 87 Channel 3 Status Register .......................................................... 88 Channel 4 Status Register .......................................................... 88 Channel 5 Status Register .......................................................... 89 Channel 6 Status Register .......................................................... 89 Channel 7 Status Register .......................................................... 90 Channel 0/Channel 1 DSP Errors Register.............................. 90 Channel 2/Channel 3 DSP Errors Register.............................. 91 Channel 4/Channel 5 DSP Errors Register.............................. 91 Channel 6/Channel 7 DSP Errors Register.............................. 92 Channel 0 to Channel 7 Error Register Enable Register ....... 92 General Errors Register 1 ........................................................... 93 General Errors Register 1 Enable .............................................. 93 General Errors Register 2 ........................................................... 94 General Errors Register 2 Enable .............................................. 94 Error Status Register 1 ................................................................ 95 Error Status Register 2 ................................................................ 95 Error Status Register 3 ................................................................ 96 Decimation Rate (N) MSB Register ......................................... 96 Decimation Rate (N) LSB Register ........................................... 96 Decimation Rate (IF) MSB Register ......................................... 96 Decimation Rate (IF) LSB Register .......................................... 97 SRC Load Source and Load Update Register .......................... 97
Outline Dimensions ........................................................................ 98 Ordering Guide ........................................................................... 98
REVISION HISTORY 6/2017—Revision 0: Initial Version
AD7771 Data Sheet
Rev. 0 | Page 4 of 98
FUNCTIONAL BLOCK DIAGRAM
AVDD1x REF_OUT REFx+
VCM
AVDD2x
AVSSx AVDD4 CONVST_SAR
IOVDDAREGxCAP DREGCAP
CLOCKMANAGER
XTAL1XTAL2/MCLKSYNC_INSYNC_OUTSTART
REFx–
DCLKDRDYDOUT3DOUT2DOUT1DOUT0
FORMAT1FORMAT0MODE3/ALERTMODE2/GPIO2MODE1/GPIO1MODE0/GPIO0
ALERT/CSDCLK2/SCLKDCLK1/SDIDCLK0/SDO
RESET
Σ-Δ ADC
AIN0+AIN0–
280mV p-p
Σ-Δ ADC
REFERENCES
EXT_REFINT_REF
AIN1+AIN1–
Σ-Δ ADC
REFERENCES
AIN2+AIN2–
Σ-Δ ADC
REFERENCES
AIN3+AIN3–
Σ-Δ ADC
REFERENCES
AIN4+AIN4–
Σ-Δ ADC
REFERENCES
AIN5+AIN5–
REFERENCES
AIN6+AIN6–
REFERENCES
DIAGNOSTICINPUTS
AIN7+AIN7–
SINC3/SINC5SRC
FILTER
GAINOFFSET
COMMON-MODE
VOLTAGEANALOG
LDO
2.5V REF
SINC3/SINC5SRC
FILTER
GAINOFFSET
SINC3/SINC5SRC
FILTER
GAINOFFSET
SINC3/SINC5SRC
FILTER
GAINOFFSET
SINC3/SINC5SRC
FILTER
GAINOFFSET
SINC3/SINC5SRC
FILTER
GAINOFFSET
SINC3/SINC5SRC
FILTER
GAINOFFSET
SINC3/SINC5SRC
FILTER
GAINOFFSET
Σ-Δ ADC
Σ-Δ ADC
AUXAIN+AUXAIN–
DATA OUTPUTINTERFACE
REGISTER MAPAND
LOGIC CONTROL
HARDWAREMODE
CONFIGURATION
SPI INTERFACE
AD7771SAR ADC
DIGITALLDO
PGA
PGA
PGA
PGA
PGA
PGA
PGA
PGA
1380
2-00
1
Figure 1.
Data Sheet AD7771
Rev. 0 | Page 5 of 98
SPECIFICATIONS AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = analog ground (AGND) (single-supply operation), AVDD2x − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V AVSSx (internal/external), master clock (MCLK) = 8192 kHz for high resolution mode and 4096 kHz for low power mode, ODR = 128 kSPS for high resolution mode and 32 kSPS for low power mode; all specifications at TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUTS
Differential Input Voltage Range VREF = (REFx+ − REFx−) ±VREF/PGAGAIN V Single-Ended Input Voltage Range 0 to VREF/PGAGAIN V AINx± Common-Mode Input Range AVSSx + 0.10 (AVDD1x +
AVSSx)/2 AVDD1x − 0.10 V
Absolute AINx± Voltage Limits AVSSx + 0.10 AVDD1x − 0.10 V DC Input Current
Differential High resolution mode ±4 nA Low power mode ±1 nA Single-Ended High resolution mode ±8 nA
Low power mode ±2 nA Input Current Drift 50 pA/°C AC Input Capacitance 8 pF
PROGRAMMABLE GAIN AMPLIFIER (PGA) Gain Settings (PGAGAIN) 1, 2, 4, or 8 Bandwidth
Small Signal High resolution mode 2 MHz Low power mode 512 kHz Large Signal High resolution mode See Figure 39, Figure 40, and Figure 44
Low power mode See Figure 42, Figure 43, and Figure 47 REFERENCE
Internal Initial Accuracy REF_OUT, TA = 25°C 2.495 2.5 2.505 V Temperature Coefficient ±10 ±38 ppm/°C Reference Load Current, IL −10 +10 mA DC Power Supply Rejection Line regulation 95 dB Load Regulation, ∆VOUT/∆IL 100 µV/mA Voltage Noise, eN p-p 0.1 Hz to 10 Hz 6.8 µV rms Voltage Noise Density, eN 1 kHz, 2.5 V reference 273.5 nV/√Hz Turn On Settling Time 100 nF 1.5 ms
External Input Voltage VREF = (REFx+ − REFx−) 1 2.5 AVDD1x V Buffer Headroom AVSSx + 0.1 AVDD1x − 0.1 V REFx− Input Voltage AVSSx AVDD1x − REFx+ V Average REFx± Input Current Current per channel
Reference buffer disabled, high resolution mode
18 µA/V
Reference buffer precharge mode (pre-Q), high resolution mode
600 nA/V
Reference buffer disabled, low power mode
4.5 µA/V
Reference buffer pre-Q, low power mode
100 nA/V
Reference buffer enabled, high resolution mode
12 nA/V
Reference buffer enabled, low power mode
5 nA/V
AD7771 Data Sheet
Rev. 0 | Page 6 of 98
Parameter Test Conditions/Comments Min Typ Max Unit TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +105 °C Functional2 TMIN to TMAX −40 +125 °C
TEMPERATURE SENSOR Accuracy ±2 °C
DIGITAL FILTER RESPONSE Group Delay See the SRC Group Delay section Settling Time See the Settling Time section Pass Band −0.1 dB See the SRC Bandwidth section −3 dB See the SRC Bandwidth section Decimation Rate
Sinc3 16 4095.99 Sinc5 16 2048
CLOCK SOURCE Frequency High resolution mode 0.655 8.192 MHz Low power mode 1.3 4.096 MHz Duty Cycle 45:55 50:50 55:45 %
Σ-Δ ADC Speed and Performance
Resolution 24 Bits ODR High resolution mode 128 kSPS Low power mode 32 kSPS No Missing Codes Sinc3, up to 24 kSPS 24 Bits Sinc5 24 Bits
AC Accuracy Dynamic Range Shorted inputs, PGAGAIN = 1
128 kSPS High resolution mode (sinc5) 95 dB 32 kSPS High resolution mode (sinc5) 107 dB 16 kSPS High resolution mode (sinc3) 105.9 dB 4 kSPS High resolution mode (sinc3) 116 dB 32 kSPS Low power mode (sinc5) 94.5 dB 8 kSPS Low power mode (sinc5) 106.5 dB 8 kSPS Low power mode (sinc3) 95.8 dB 2 kSPS Low power mode (sinc3) 111.8 dB
Total Harmonic Distortion (THD) −0.5 dBFS, high resolution mode −109 dB −0.5 dBFS, low power mode −105 dB Signal-to-Noise-and-Distortion Ratio
(SINAD) fIN = 60 Hz 106 dB
Spurious-Free Dynamic Range (SFDR)
High resolution mode, 16 kSPS, PGAGAIN = 1
132 dB
Intermodulation Distortion (IMD) fA = 50 Hz, fB = 51 Hz, high resolution mode
−125 dB
fA = 50 Hz, fB = 51 Hz, low power mode
−105 dB
DC Power Supply Rejection AVDD1x = 3.3 V −90 dB DC Common-Mode Rejection Ratio 80 dB Crosstalk −120 dB
DC ACCURACY Integral Nonlinearity (INL) Endpoint method
High Resolution PGAGAIN = 1 ±8 ±15 ppm of FSR
Other PGA gains ±4 ±15 ppm of FSR
Data Sheet AD7771
Rev. 0 | Page 7 of 98
Parameter Test Conditions/Comments Min Typ Max Unit Low Power PGAGAIN = 1 ±9 ±17 ppm of
FSR Other PGA gains ±6 ±15 ppm of
FSR Offset Error ±15 ±90 µV Offset Error Drift 0.25 µV/°C Over time −2 µV/1000
hours Offset Matching 25 µV Gain Error ±0.1 % FS Gain Error Drift vs. Temperature PGAGAIN = 1 ±0.75 ppm/°C Gain Matching ±0.1 %
SAR ADC Speed and Performance
Resolution 12 Bits Analog Input Range AVSS4 + 0.1 AVDD4 − 0.1 V Analog Input Common-Mode Range AVSS4 + 0.1 (AVDD4 +
AVSS4)/2 AVDD4 − 0.1 V
Analog Input Current ±100 nA Throughput 256 kSPS
DC Accuracy Differential mode INL ±1.5 LSB Differential Nonlinearity (DNL) No missing codes (12-bit) −0.99 1 LSB Offset ±1 LSB Gain 12 LSB
AC Performance Signal-to-Noise Ratio (SNR) 1 kHz 66 dB THD 1 kHz −81 dB
VCM PIN Output (VCM) (AVDD1x +
AVSSx)/2 V
Load Current, IL 1 mA Load Regulation, ∆VOUT/∆IL 12 mV/mA Short-Circuit Current 5 mA
LOGIC INPUTS Input Voltage
High, VIH 0.7 × IOVDD V Low, VIL 0.4 V
Hysteresis 0.1 V Input Currents −10 +10 µA
LOGIC OUTPUTS3 Output Voltage
High, VOH IOVDD ≥ 3 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.3 V ≤ IOVDD < 3 V,
ISOURCE = 500 µA 0.8 × IOVDD V
IOVDD < 2.3 V, ISOURCE = 200 µA 0.8 × IOVDD V Low, VOL IOVDD ≥ 3 V, ISINK = 2 mA 0.4 V 2.3 V ≤ IOVDD < 3 V, ISINK = 1 mA 0.4 V IOVDD < 2.3 V, ISINK = 100 µA 0.4 V
Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF Σ-Δ ADC Data Output Coding Twos complement SAR ADC Data Output Coding Binary
AD7771 Data Sheet
Rev. 0 | Page 8 of 98
Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLIES All Σ-Δ channels enabled
AVDD1x − AVSSx 3.0 3.6 V IAVDD1x
4, 5 Reference buffer pre-Q, VCM enabled, internal reference enabled
High resolution mode 18.3 23.7 mA Low power mode 5 6.4 mA Reference buffer enabled, VCM
enabled, internal reference enabled
High resolution mode 20.5 26.7 mA Low power mode 5.5 7.1 mA Reference buffer disabled, VCM
disabled, internal reference disabled
High resolution mode 14.3 18.8 mA Low power mode 3.9 5.1 mA AVDD2x − AVSSx 2.2 3.6 V IAVDD2x High resolution mode 10.2 10.65 mA Low power mode 3.8 4 mA AVDD4 − AVSSx 3 3.6 V IAVDD4 SAR enabled 1.7 2 mA SAR disabled 1 10 µA AVSSx − DGND −1.8 0 V IOVDD − DGND 1.8 3.6 V IIOVDD High resolution mode (sinc5) 14.3 17 mA Low power mode (sinc5) 4.6 5.5 mA High resolution mode (sinc3) 12.2 14.2 mA Low power mode (sinc3) 2.2 4.9 mA Power Dissipation6 Internal buffers bypassed, internal
reference disabled, internal oscillator disabled, SAR disabled
High Resolution Mode 128 kSPS 133 153 mW Low Power Mode 32 kSPS 42 48.5 mW
Power-Down All ADCs disabled 530 µW 1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVDD3, and AVSS4. This term is used throughout the data sheet. 2 At temperatures higher than 105°C, the device can be operated normally, though slight degradation on the maximum/minimum specifications is expected because
these specifications are only guaranteed up to 105°C. See the Typical Performance Characteristics section for plots showing the typical performance of the device at high temperatures.
3 The SDO pin and the DOUTx pin are configured in the default mode of strength. 4 AVDD1x = 3.3 V, AVSSx = GND = ground, IOVDD = 1.8 V, CMOS clock. 5 Disabling either the VCM pin or the internal reference results in a 40 µA typical current consumption reduction. 6 Power dissipation is calculated using the maximum supply voltage, 3.6 V.
Data Sheet AD7771
Rev. 0 | Page 9 of 98
DOUTx TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND (single-supply operation), AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V internal/external, MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Description2 Test Conditions/Comments Min Typ Max Unit t1 MCLK frequency 50:50 0.655 8.192 MHz t2 MCLK low time 60 ns t3 MCLK high time 60 ns t4 DCLK high time MCLK/2 121 ns t5 DCLK low time MCLK/2 121 ns t6 MCLK falling edge to DCLK rising edge 45 ns t7 MCLK falling edge to DCLK falling edge 45 ns t8 DCLK rising edge to DRDY rising edge 2 ns
t9 DCLK rising edge to DRDY falling edge 1 ns
t10 DOUTx setup time 20 ns t11 DOUTx hold time 20 ns 1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. 2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
DCLK
DRDY
LSB MSB MSB – 1 LSB + 1 LSBDOUTx
t2
t4 t5t6
t7
t10 t11
t8 t9
t1
t3
1380
2-00
2
Figure 2. Data Interface Timing Diagram
AD7771 Data Sheet
Rev. 0 | Page 10 of 98
SPI TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Description2 Test Conditions/Comments Min Typ Max Unit t12 SCLK period 50:50 30 MHz t13 SCLK low time 7 ns t14 SCLK high time 7 ns t15 SCLK rising edge to CS falling edge 10 ns
t16 CS falling edge to SCLK rising edge 10 ns
t17 SCLK rising edge to CS rising edge 10 ns
t18 CS rising edge to SCLK rising edge 10 ns
t19 Minimum CS high time 10 ns
t20 SDI setup time 5 ns t21 SDI hold time 5 ns t22A CS falling edge to SDO enable (SPI = Mode 0) 30 ns
t22B SCLK falling edge to SDO enable (SPI = Mode 1) 49 ns t23 SDO setup time 10 ns t24 SDO hold time 10 ns t25 CS rising edge to SDO disable 30 ns 1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. 2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
CS
SCLK
MSB MSB – 1 LSB + 1 LSBSDI
MSB MSB – 1 LSB + 1 LSBSDO
t15 t16 t13
t14
t20
t22A t21
t24
t23
t22B
t12
t19
t17
t18
t25
1380
2-00
3
Figure 3. SPI Control Interface Timing Diagram
Data Sheet AD7771
Rev. 0 | Page 11 of 98
SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 4. Parameter Description2 Test Conditions/Comments Min Typ Max Unit t26 START setup time 10 ns
t27 START hold time MCLK ns
t28 MCLK falling edge to SYNC_OUT falling edge MCLK ns
t29 SYNC_IN setup time 10 ns
t30 SYNC_IN hold time MCLK ns
tINIT_SYNC_IN SYNC_IN rising edge to first DRDY 16 kSPS, high resolution mode 145 µs
tINIT_RESET RESET rising edge to first DRDY 16 kSPS, high resolution mode 225 µs
t31 RESET hold time 2 × MCLK ns
tPOWER_UP Start time tPOWER_UP is not shown in Figure 4 2 ms 1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet. 2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
START
SYNC_OUT
SYNC_IN
DRDY
RESET
t26
t27
t28
t29
tINIT_SYNC_IN
t31 tINIT_RESET
t30
1380
2-00
4
Figure 4. Synchronization Pins and Reset Control Interface Timing Diagram
AD7771 Data Sheet
Rev. 0 | Page 12 of 98
SAR ADC TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 5. Parameter Description2 Min Typ Max Unit t32 Conversion time 1 3.4 µs t33 Acquisition time3 500 ns t34 Delay time 50 ns t35 Throughput data rate 256 kSPS 1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet. 2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2. 3 Direct mode enabled. If deglitch mode is enabled, add 1.5/MCLK as described in Table 29.
CS
CONVST_SAR
t33 t32
t35
t34
1380
2-00
5
Figure 5. SAR ADC Timing Diagram
GPIO SRC UPDATE TIMING CHARACTERISTISTICS AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications TMIN to TMAX, unless otherwise noted.
Table 6. Parameter Description2 Min Typ Max Unit t36 GPIO2 setup time 10 ns t37 GPIO2 hold time—high resolution mode MCLK ns GPIO2 hold time—low power mode 2 × MCLK ns t38 MCLK rising edge to GPIO1 rising edge time 20 ns t39 GPIO0 setup time 5 ns t40 GPIO0 hold time MCLK ns 1 AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet. 2 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
GPIO2
GPIO1
GPIO0
t36
t37
t38
t39
t40
1380
2-00
6
Figure 6. GPIOs for SRC Update Timing Diagram
Data Sheet AD7771
Rev. 0 | Page 13 of 98
ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating Any Supply Pin to AVSSx −0.3 V to +3.96 V AVSSx to DGND −1.98 V to +0.3 V AREGxCAP to AVSSx −0.3 V to +1.98 V DREGCAP to DGND −0.3 V to +1.98 V IOVDD to DGND −0.3 V to +3.96 V IOVDD to AVSSx −0.3 V to +5.94 V AVDD4 to AVSSx −0.3 V to +3.96 V Analog Input Voltage AVSSx − 0.3 V to AVDD1x + 0.3 V or
3.96 V (whichever is less) REFx± Input Voltage AVSSx − 0.3 V to AVDD1x + 0.3 V or
3.96 V (whichever is less) AUXAIN± AVSSx − 0.3 V to AVDD4 + 0.1 V or
3.96 V (whichever is less) Digital Input Voltage to
DGND DGND − 0.3 V to IOVDD + 0.3 V or 3.96 V (whichever is less)
Digital Output Voltage to DGND
DGND − 0.3 V to IOVDD + 0.3 V or 3.96 V (whichever is less)
XTAL1 to DGND DGND − 0.3 V to DREGCAP + 0.3 V or 1.98 V (whichever is less)
AINx±, AUXAIN±, and Digital Input Current
±10 mA
Operating Temperature Range
−40°C to +125°C
Junction Temperature, TJ Maximum
150°C
Storage Temperature Range −65°C to +150°C Reflow Soldering 260°C ESD 2 kV Field Induced Charged
Device Model (FICDM) 500 V
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required.
Table 8. Thermal Resistance Package Type θJA θJB ΨJT ΨJB Unit CP-64-151
No Thermal Vias 30.43 N/A2 0.13 6.59 °C/W 49 Thermal Vias 22.62 3.17 0.09 3.19 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51. 2 N/A means not applicable.
ESD CAUTION
AD7771 Data Sheet
Rev. 0 | Page 14 of 98
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7771TOP VIEW
(Not to Scale)17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CONV
ST_S
ARAL
ERT/
CSDC
LK2/
SCLK
DCLK
1/SD
IDC
LK0/
SDO
DGND
DREG
CAP
IOVD
DDO
UT3
DOUT
2DO
UT1
DOUT
0DC
LKDR
DYXT
AL1
XTAL
2/M
CLK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AUXA
IN–
AUXA
IN+
AVDD
4AV
SS4
AVSS
2AAR
EG1C
APAV
DD2A
VCM
CLK_
SEL
FORM
AT0
FORM
AT1
AVSS
3AV
DD2B
AREG
2CAP
AVSS
2BRE
F_O
UT
123456789
10111213141516
AIN0–AIN0+AIN1–AIN1+
AVSS1AAVDD1A
REF1–REF1+AIN2–AIN2+AIN3–AIN3+
MODE0/GPIO0MODE1/GPIO1MODE2/GPIO2MODE3/ALERT
NOTES1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSSx.
AIN4–AIN4+AIN5–AIN5+AVSS1BAVDD1BREF2–REF2+AIN6–AIN6+AIN7–AIN7+RESETSYNC_INSYNC_OUTSTART
48474645444342414039383736353433
1380
2-00
7
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions Pin No. Mnemonic Type Direction Description 1 AIN0− Analog input Input Analog Input Channel 0, Negative. 2 AIN0+ Analog input Input Analog Input Channel 0, Positive. 3 AIN1− Analog input Input Analog Input Channel 1, Negative. 4 AIN1+ Analog input Input Analog Input Channel 1, Positive. 5 AVSS1A Supply Supply Negative Front-End Analog Supply for Channel 0 to Channel 3, Typical at −1.65 V
(Dual Supply) and AGND (Single Supply). Connect all the AVSSx pins to the same potential.
6 AVDD1A Supply Supply Positive Front-End Analog Supply for Channel 0 to Channel 3, Typical at AVSSx + 3.3 V. Connect this pin to AVDD1B.
7 REF1− Reference Input Negative Reference Input 1 for Channel 0 to Channel 3, Typical at AVSSx. Connect all the REFx− pins to the same potential.
8 REF1+ Reference Input Positive Reference Input 1 for Channel 0 to Channel 3, Typical at REF1− + 2.5 V. 9 AIN2− Analog input Input Analog Input Channel 2, Negative. 10 AIN2+ Analog input Input Analog Input Channel 2, Positive. 11 AIN3− Analog input Input Analog Input Channel 3, Negative. 12 AIN3+ Analog input Input Analog Input Channel 3, Positive. 13 MODE0/GPIO0 Digital I/O I/O Mode 0 Input in Pin Control Mode (MODE0). See Table 14 for more details. Configurable General-Purpose Input/Output 0 in SPI Control Mode (GPIO0).
If not in use, connect this pin to DGND or IOVDD. 14 MODE1/GPIO1 Digital I/O I/O Mode 1 Input in Pin Control Mode (MODE1). See Table 14 for more details. Configurable General-Purpose Input/Output 1 in SPI Control Mode (GPIO1).
If not in use, connect this pin to DGND or IOVDD. 15 MODE2/GPIO2 Digital I/O I/O Mode 2 Input in Pin Control Mode (MODE2). See Table 14 for more details. Configurable General-Purpose Input/Output 2 in SPI Control Mode (GPIO2).
If not in use, connect this pin to DGND or IOVDD. 16 MODE3/ALERT Digital I/O I/O Mode 3 Input in Pin Control Mode (MODE3). See Table 14 for more details. Alert Output in SPI Control Mode (ALERT).
Data Sheet AD7771
Rev. 0 | Page 15 of 98
Pin No. Mnemonic Type Direction Description 17 CONVST_SAR Digital input Input Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table 13 for more
details. This pin also functions as the start for the SAR conversion in SPI control mode.
18 ALERT/CS Digital input Input Alert Output in Pin Control Mode (ALERT).
Chip Select in SPI Control Mode (CS).
19 DCLK2/SCLK Digital input Input Data Clock Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 15 for more details.
SPI Clock in SPI Control Mode (SCLK). 20 DCLK1/SDI Digital input Input Data Clock Frequency Selection Pin 1 in Pin Control Mode (DCLK1). See Table 15
for more details. SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the
device is configured in pin control mode with the SPI as the data output interface. 21 DCLK0/SDO Digital output Output Data Clock Frequency Selection Pin 0 in Pin Control Mode (DCLK0). See Table 15
for more details. SPI Data Output in SPI Control Mode (SDO). 22 DGND Supply Supply Digital Ground. 23 DREGCAP Supply Output Digital Low Dropout (LDO) Output. Decouple this pin to DGND with a 1 µF
capacitor. 24 IOVDD Supply Supply Digital Levels Input/Output and Digital LDO (DLDO) Supply from 1.8 V to 3.6 V.
IOVDD must not be lower than DREGCAP. 25 DOUT3 Digital output I/O Data Output Pin 3. If the device is configured in daisy-chain mode, this pin
acts as an input pin. See the Daisy-Chain Mode section for more details. 26 DOUT2 Digital output I/O Data Output Pin 2. If the device is configured in daisy-chain mode, this pin
acts as an input pin. See the Daisy-Chain Mode section for more details. 27 DOUT1 Digital output Output Data Output Pin 1. 28 DOUT0 Digital output Output Data Output Pin 0. 29 DCLK Digital output Output Data Output Clock. 30 DRDY Digital output Output Data Output Ready Pin.
31 XTAL1 Clock Input Crystal 1 Input Connection. If CMOS is used as a clock source, tie this pin to DGND. See Table 12 for more details.
32 XTAL2/MCLK Clock Input Crystal 2 Input Connection (XTAL2). See Table 12 for more details. CMOS Clock (MCLK). See Table 12 for more details. 33 START Digital input Input Synchronization Pulse. This pin internally synchronizes an external START
asynchronous pulse with MCLK. The synchronize signal is shifted out by the SYNC_OUT pin. If not in use, tie this pin to DGND. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details.
34 SYNC_OUT Digital output Input Synchronization Signal. This pin generates a synchronous pulse generated and driven by hardware (via the START pin) or by software (GENERAL_USER_ CONFIG_2, Bit 0). If this pin is in use, it must be wired to the SYNC_IN pin. See the Phase Adjustment section and the Digital Reset and Synchronization Pins section for more details.
35 SYNC_IN Digital input Input Reset for the Internal Digital Block and Synchronize for Multiple Devices. See the Digital Reset and Synchronization Pins section for more details.
36 RESET Digital input Input Asynchronous Reset Pin. This pin resets all registers to their default value. It is recommended to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block.
37 AIN7+ Analog input Input Analog Input Channel 7, Positive. 38 AIN7− Analog input Input Analog Input Channel 7, Negative. 39 AIN6+ Analog input Input Analog Input Channel 6, Positive. 40 AIN6− Analog input Input Analog Input Channel 6, Negative. 41 REF2+ Reference Input Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2− + 2.5 V. 42 REF2− Reference Input Negative Reference Input 2 for Channel 4 to Channel 7, Typical at AVSSx.
Connect all the REFx− pins to the same potential. 43 AVDD1B Supply Supply Positive Front-End Analog Supply for Channel 4 to Channel 7. Connect this pin
to AVDD1A.
AD7771 Data Sheet
Rev. 0 | Page 16 of 98
Pin No. Mnemonic Type Direction Description 44 AVSS1B Supply Supply Negative Front-End Analog Supply for Channel 4 to Channel 7, Typical at
−1.65 V (Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins to the same potential.
45 AIN5+ Analog input Input Analog Input Channel 5, Positive. 46 AIN5− Analog input Input Analog Input Channel 5, Negative. 47 AIN4+ Analog input Input Analog Input Channel 4, Positive. 48 AIN4− Analog input Input Analog Input Channel 4, Negative. 49 REF_OUT Reference Output 2.5 V Reference Output. Connect a 100 nF capacitor on this pin if using the
internal reference. 50 AVSS2B Supply Supply Negative Analog Supply. Connect all the AVSSx pins together. 51 AREG2CAP Supply Output Analog LDO Output 2. Decouple this pin to AVSS2B with a 1 µF capacitor. 52 AVDD2B Supply Supply Positive Analog Supply. Connect this pin to AVDD2A. 53 AVSS3 Supply Supply Negative Analog Ground. Connect all the AVSSx to the same potential. 54 FORMAT1 Digital input Input Output Data Frame 1. See Table 13 for more details. 55 FORMAT0 Digital input Input Output Data Frame 0. See Table 13 for more details. 56 CLK_SEL Digital input Input Select Clock Source. See Table 12 for more details. 57 VCM Analog output Output Common-Mode Voltage Output, Typical at (AVDD1x + AVSSx)/2. 58 AVDD2A Supply Input Analog Supply from 2.2 V to 3.6 V. AVSS2x must not be lower than AREGxCAP.
Connect this pin to AVDD2B. 59 AREG1CAP Supply Output Analog LDO Output 1. Decouple this pin to AVSSx with a 1 µF capacitor. 60 AVSS2A Supply Input Negative Analog supply. Connect all the AVSSx pins to the same potential. 61 AVSS4 Supply Supply Negative SAR Analog Supply and Reference. Connect all AVSSx pins to the same
potential. 62 AVDD4 Supply Supply Positive SAR Analog Supply and Reference Source. 63 AUXAIN+ Analog input Input Positive SAR Analog Input Channel. 64 AUXAIN− Analog input Input Negative SAR Analog Input Channel. EPAD Supply Input Exposed Pad. Connect the exposed pad to AVSSx.
Data Sheet AD7771
Rev. 0 | Page 17 of 98
TYPICAL PERFORMANCE CHARACTERISTICS 10
–10
–8
–6
–4
–2
0
2
4
6
8
INL
(ppm
)
INPUT VOLTAGE (V)
–2.4
8
–2.1
2
–1.7
7
–1.4
1
–1.0
6
–0.7
0
–0.3
5 0
0.35
0.70
1.06
1.41
1.77
2.12
2.48
TA = 25°CGAIN = 1DIFFERENTIAL INPUT SIGNALVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
1380
2-00
8
Figure 8. INL vs. Input Voltage and Channel at 64 kSPS, High Resolution Mode
10
8
6
4
2
0
–2
–4
–6
–8
–10
–2.4
8
2.48
INL
(ppm
)
INPUT VOLTAGE (V)
–2.1
2
–1.7
7
–1.4
1
–1.0
6
–0.7
0
–0.3
5 0
0.35
0.70
1.06
1.41
1.77
2.12
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CDIFFERENTIAL VIN × GAINVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-00
9
Figure 9. INL vs. Input Voltage and PGA Gain at 64 kSPS,
High Resolution Mode
–3 –2 –1 0 1 2 3
10
8
6
4
2
0
–2
–4
–6
–8
–10
INL
(ppm
)
INPUT VOLTAGE (V)
GAIN = 1DIFFERENTIAL INPUT SIGNALVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
TA = –40°CTA = +25°CTA = +105°CTA = +125°C
1380
2-01
0
Figure 10. INL vs. Input Voltage and Temperature at 64 kSPS,
High Resolution Mode
15
10
5
0
–5
–10
–15
INL
(ppm
)
–2.4
8
2.48
INPUT VOLTAGE (V)
–2.1
2
–1.7
7
–1.4
1
–1.0
6
–0.7
0
–0.3
5 0
0.35
0.70
1.06
1.41
1.77
2.12
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
TA = 25°CGAIN = 1DIFFERENTIAL INPUT SIGNALVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-01
1
Figure 11. INL vs. Input Voltage and Channel at 16 kSPS,
Low Power Mode
10
–10
–8
–6
–4
–2
0
2
4
6
8
INL
(ppm
)
INPUT VOLTAGE (V)
–2.4
8
–2.1
2
–1.7
7
–1.4
1
–1.0
6
–0.7
0
–0.3
5 0
0.35
0.70
1.06
1.41
1.77
2.12
2.48
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CDIFFERENTIAL VIN × GAINVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-01
2
Figure 12. INL vs. Input Voltage and PGA Gain at 16 kSPS,
Low Power Mode
10
5
–5
0
–10
–15–3 –2 –1 0 1 2 3
INL
(ppm
)
INPUT VOLTAGE (V)
TA = –40°CTA = +25°CTA = +105°CTA = +125°C
GAIN = 1DIFFERENTIAL INPUT SIGNALVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-01
3
Figure 13. INL vs. Input Voltage and Temperature at 16 kSPS, Low Power Mode
AD7771 Data Sheet
Rev. 0 | Page 18 of 98
20
–20
–10
5
15
0
–15
–5
10
–4 –2 0 2–3 –1 1 3 4
INL
(ppm
)
INPUT VOLTAGE (V)
TA = 25°CGAIN = 1DIFFERENTIAL INPUT SIGNALVCM = (AVDD1x + AVSSx) ÷ 2
VREF = 1.0VVREF = 1.5VVREF = 2.0VVREF = 2.5VVREF = 3.0VVREF = 3.3V
1380
2-01
4
Figure 14. INL vs. Input Voltage and Reference Voltage (VREF)
at 64 kSPS, High Resolution Mode
10
–10
–8
–6
–4
–2
0
2
4
6
8
INL
(ppm
)
INPUT VOLTAGE (V)
–2.4
8
–2.1
2
–1.7
7
–1.4
1
–1.0
6
–0.7
0
–0.3
5 0
0.35
0.70
1.06
1.41
1.77
2.12
2.48
TA = 25°CGAIN = 1DIFFERENTIAL VIN × GAINVREF = 2.5V
VCM = 1.95VVCM = 1.65VVCM = 1.35V
1380
2-01
5
Figure 15. INL vs. Input Voltage and VCM at 64 kSPS,
High Resolution Mode
8388
326
ADC CODE
1000
900
800
700
600
500
400
300
200
100
0
SAM
PLE
CO
UN
T
8388
340
8388
354
8388
368
8388
382
8388
396
8388
410
8388
424
8388
438
8388
452
8388
466
8388
480
8388
494
8388
508
8388
522
8388
536
8388
550
8388
564
8388
578
8388
592
8388
606
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2TA = 25°C
1380
2-01
6
Figure 16. Noise Histogram at 16 kSPS, High Resolution Mode,
Sinc3 Filter Enabled
–4 –3 4INPUT VOLTAGE (V)
15
10
5
0
–5
–10
–15
INL
(ppm
)
–2 –1 0 1 2 3
TA = 25°CGAIN = 1DIFFERENTIAL INPUT SIGNALVCM = (AVDD1x + AVSSx) ÷ 2VREF = 2.5V
VREF = 1.0VVREF = 1.5VVREF = 2.0VVREF = 2.5VVREF = 3.0VVREF = 3.3V
1380
2-01
7
Figure 17. INL vs. Input Voltage and Reference Voltage (VREF)
at 16 kSPS, Low Power Mode
15
10
5
0
–5
–10
–15
INL
(ppm
)
–2.4
8
2.48
INPUT VOLTAGE (V)
–2.1
2
–1.7
7
–1.4
1
–1.0
6
–0.7
0
–0.3
5 0
0.35
0.70
1.06
1.41
1.77
2.12
TA = 25°CGAIN = 1DIFFERENTIAL INPUT SIGNALVREF = 2.5V
VCM = 1.95VVCM = 1.65VVCM = 1.35V
1380
2-01
8
Figure 18. INL vs. Input Voltage and VCM at 16 kSPS,
Low Power Mode
8388
300
8388
604
ADC CODE
1000
900
800
700
600
500
400
300
200
100
0
SAM
PLE
CO
UN
T
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2TA = 25°C
8388
316
8388
332
8388
348
8388
364
8388
380
8388
396
8388
412
8388
428
8388
444
8388
460
8388
476
8388
492
8388
508
8388
524
8388
540
8388
556
8388
572
8388
588
1380
2-01
9
Figure 19. Noise Histogram at 4 kSPS, Low Power Mode,
Sinc3 Filter Enabled
Data Sheet AD7771
Rev. 0 | Page 19 of 98
300
250
200
150
100
50
0
SAM
PLE
CO
UN
T
ADC CODE
8387
690
8387
760
8387
830
8387
900
8387
970
8388
040
8388
110
8388
180
8388
250
8388
320
8388
390
8388
460
8388
530
8388
600
8388
670
8388
740
8388
810
8388
880
8388
950
8389
020
8389
090
8389
160
8389
230
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2TA = 25°C
1380
2-02
0
Figure 20. Noise Histogram at 64 kSPS, High Resolution Mode,
Sinc5 Filter Enabled
12
0125
NO
ISE
(µV
rms)
TEMPERATURE (°C)
2
4
6
8
10
–40 25 105
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-02
1
Figure 21. Noise vs. Temperature at 16 kSPS, High Resolution Mode,
Sinc3 Filter Enabled
18
0
NO
ISE
(µV
rms)
2
4
6
8
10
12
14
16
125TEMPERATURE (°C)
–40 25 105
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-02
2
Figure 22. Noise vs. Temperature at 64 kSPS, High Resolution Mode,
Sinc5 Filter Enabled
300
250
200
150
100
50
0
SAM
PLE
CO
UN
T
ADC CODE
8387
466
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2TA = 25°C
8387
554
8387
642
8387
730
8387
818
8387
906
8387
994
8388
082
8388
170
8388
258
8388
346
8388
434
8388
522
8388
610
8388
698
8388
786
8388
874
8388
962
8389
050
8389
138
1380
2-02
3
Figure 23. Noise Histogram at 16 kSPS, Low Power Mode,
Sinc5 Filter Enabled
12
0125
NO
ISE
(µV
rms)
TEMPERATURE (°C)
2
4
6
8
10
–40 25 105
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-02
4
Figure 24. Noise vs. Temperature at 4 kSPS, Low Power Mode,
Sinc3 Filter Enabled
20
0
NO
ISE
(µV
rms)
2
4
6
8
10
12
14
16
18
125TEMPERATURE (°C)
–40 25 105
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2
1380
2-02
5
Figure 25. Noise vs. Temperature at 16 kSPS, Low Power Mode,
Sinc5 Filter Enabled
AD7771 Data Sheet
Rev. 0 | Page 20 of 98
1.6
0
8192
000
NO
ISE
(µV
rms)
CLOCK FREQUENCY (Hz)
1.02.03.04.05.06.07.08.09.01.01.11.21.31.41.5
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
7708
400
7224
800
6741
200
6257
600
5774
000
5290
400
4806
800
4323
200
3839
600
3356
000
2872
400
2388
800
1905
200
1421
600
9380
00
4544
00
1380
2-02
6
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2TA = 25°CDECIMATION = 256
Figure 26. Noise vs. Clock Frequency, High Resolution Mode
160
0
140
NO
ISE
(nV/
√Hz)
ODR (SPS)
20
40
60
80
100
120
1000 4000 8000 16000
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
1380
2-02
7
Figure 27. Noise vs. ODR, High Resolution Mode, Sinc3 Filter Enabled
180
0
40
80
120
160
20
60
100
140
NO
ISE
(nV/
√Hz)
ODR (SPS)8000 128000
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
32000 64000
1380
2-02
8
Figure 28. Noise vs. ODR, High Resolution Mode, Sinc5 Filter Enabled
1.80
0
4096
000
2252
80
NO
ISE
(µV
rms)
CLOCK FREQUENCY (Hz)
2.00
4.00
6.00
8.00
1.00
1.20
1.40
1.60
4015
360
3773
440
3531
520
3249
280
3007
360
2765
440
2523
520
2241
280
1999
360
1757
440
1475
200
1233
280
9913
60
7091
20
4672
00
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
1380
2-02
9
VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2TA = 25°CDECIMATION = 256
Figure 29. Noise vs. Clock Frequency, Low Power Mode
700
0
NO
ISE
(nV/
√Hz)
ODR (SPS)500 8000
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
2000 4000
100
200
300
400
500
600
1380
2-03
0
Figure 30. Noise vs. ODR, Low Power Mode, Sinc3 Filter Enabled
400
0
NO
ISE
(nV/
√Hz)
50
100
150
200
250
300
350
ODR (SPS)1000 32000
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
8000 16000
1380
2-03
1
Figure 31. Noise vs. ODR, Low Power Mode, Sinc5 Filter Enabled
Data Sheet AD7771
Rev. 0 | Page 21 of 98
10
–180
AM
PLIT
UD
E (d
B)
FREQUENCY (Hz)
027
8.32
055
5.66
484
6.68
011
25.9
7713
93.5
5516
73.8
2819
54.1
0222
34.3
7525
01.9
5327
69.5
3130
37.1
0933
04.6
8735
72.2
6638
39.8
4441
07.4
2243
88.6
7246
64.0
6349
38.4
7752
11.9
1454
85.3
5257
59.7
6660
33.2
0363
07.6
1765
80.0
7868
51.5
6371
25.9
7773
99.4
1476
72.8
5279
47.2
66
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2INPUT FREQUENCY = 50Hz
1380
2-03
2
Figure 32. FFT Plot, High Resolution Mode at 16 kSPS,
Input Frequency (fIN) = 50 Hz, Sinc3 Filter Enabled
0
6300
0
FREQUENCY (Hz)
10
–180
AM
PLIT
UD
E (d
B)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
2250
4500
6750
9000
1125
013
500
1575
018
000
2025
022
500
2475
027
000
2925
031
500
3375
036
000
3825
040
500
4275
045
000
4725
049
500
5175
054
000
5625
058
500
6075
0
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2ODR = 128kSPSINPUT FREQUENCY = 50Hz
1380
2-03
3
Figure 33. FFT Plot, High Resolution Mode at 128 kSPS, Input Frequency (fIN) = 50 Hz, Sinc5 Filter Enabled
0
7861
.33
FREQUENCY (Hz)
10
–180
AM
PLIT
UD
E (d
B)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2INPUT FREQUENCY = 1kHz
341.
8068
3.59
1025
.39
1367
.19
1708
.98
2050
.78
2392
.58
2734
.38
3076
.17
3417
.97
3759
.77
4101
.56
4443
.36
4785
.16
5126
.95
5468
.75
5810
.55
6152
.34
6494
.14
6835
.94
7177
.73
7519
.53
1380
2-03
4
Figure 34. FFT Plot, High Resolution Mode at 16 kSPS,
Input Frequency (fIN) = 1 kHz, Sinc3 Filter Enabled
0
1982
.42
FREQUENCY (Hz)
10
–180
AM
PLIT
UD
E (d
B)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2INPUT FREQUENCY = 50Hz
68.3
613
6.72
205.
0827
3.44
341.
8041
0.16
478.
5254
6.88
615.
2368
3.59
751.
9582
0.31
888.
6795
7.03
1025
.39
1093
.75
1162
.11
1230
.47
1298
.83
1367
.19
1435
.55
1503
.91
1572
.27
1640
.63
1708
.98
1777
.34
1845
.70
1914
.06
1380
2-03
5
Figure 35. FFT Plot, Low Power Mode at 4 kSPS,
Input Frequency (fIN) = 50 Hz, Sinc3 Filter Enabled
0
1575
0.0
FREQUENCY (Hz)
10
–180
AM
PLIT
UD
E (d
B)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2ODR = 32kSPSINPUT FREQUENCY = 50Hz
562.
511
25.0
1687
.522
50.0
2812
.533
75.0
3937
.545
00.0
5062
.556
25.0
6187
.567
50.0
7312
.578
75.0
8437
.590
00.0
9562
.510
125.
010
687.
511
250.
011
812.
512
375.
012
937.
513
500.
014
062.
514
625.
015
187.
5
1380
2-03
6
Figure 36. FFT Plot, Low Power Mode at 32 kSPS,
Input Frequency (fIN) = 50 Hz, Sinc5 Filter Enabled
0
FREQUENCY (Hz)
10
–180
AM
PLIT
UD
E (d
B)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
74.2
214
8.44
222.
6629
6.88
371.
0944
5.31
519.
5359
3.75
667.
9774
2.19
816.
4189
0.63
964.
8410
39.0
611
13.2
811
87.5
012
61.7
213
35.9
414
10.1
614
84.3
815
58.5
916
32.8
117
07.0
317
81.2
518
55.4
719
29.6
9TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2INPUT FREQUENCY = 1kHz
1380
2-03
7
Figure 37. FFT Plot, Low Power Mode at 4 kSPS, Input Frequency (fIN) = 1 kHz, Sinc3 Filter Enabled
AD7771 Data Sheet
Rev. 0 | Page 22 of 98
0
6296
8.75
FREQUENCY (Hz)
10
–180
AM
PLIT
UD
E (d
B)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
2421
.88
4843
.75
7265
.63
9687
.50
1210
9.38
1453
1.25
1695
3.13
1937
5.00
2179
6.88
2421
8.75
2664
0.63
2906
2.50
3148
4.38
3390
6.25
3632
8.13
3875
0.00
4117
1.88
4359
3.75
4601
5.63
4843
7.50
5085
9.38
5328
1.25
5570
3.13
5812
5.00
6054
6.88
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2ODR = 128kSPSINPUT FREQUENCY = 1kHz
0
1380
2-03
8
Figure 38. FFT Plot, High Resolution Mode at 128 kSPS,
Input Frequency (fIN) = 1 kHz, Sinc5 Filter Enabled
–100
–105
–110
–115
–120
–125
–130
10.0
THD
(dB
)
INPUT FREQUENCY (Hz)
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
89.2
168.
424
7.6
326.
840
6.0
485.
256
4.4
643.
672
2.8
802.
088
1.2
970.
328
60.0
5340
.078
20.0
1030
0.0
1309
0.0
1557
0.0
1805
0.0
2053
0.0
2301
0.0
2549
0.0
2797
0.0
3045
0.0
TA = 25°CGAIN = 1VREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2VIN = –0.5dBFS
1380
2-03
9
Figure 39. THD vs. Input Frequency at 64 kSPS, High Resolution Mode,
Sinc5 Filter Enabled
–100
–135
10.0
3910
.0
THD
(dB
)
INPUT FREQUENCY (Hz)
–130
–125
–120
–115
–110
–105
89.2
168.
424
7.6
326.
840
6.0
485.
256
4.4
643.
672
2.8
802.
088
1.2
970.
311
80.0
1450
.017
20.0
2050
.023
50.0
2590
.028
90.0
3130
.034
00.0
3670
.0
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = –0.5dBFS
1380
2-04
0
Figure 40. THD vs. Input Frequency at 16 kSPS, High Resolution Mode,
Sinc3 Filter Enabled
10
–180
0
AMPL
ITUD
E (d
B)
FREQUENCY (Hz)
–170–160–150–140–130–120–110–100
–90–80–70–60–50–40–30–20–10
0
593.
7511
87.5
017
81.2
523
75.0
029
68.7
535
62.5
041
56.2
547
50.0
053
43.7
559
37.5
065
31.2
571
25.0
077
18.7
583
12.5
089
06.2
595
00.0
010
093.
7510
687.
5011
281.
2511
875.
0012
468.
7513
062.
5013
656.
2514
250.
0014
843.
7515
437.
50
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVCM = (AVDD1x + AVSSx) ÷ 2ODR = 32kSPSINPUT FREQUENCY = 1kHz
1380
2-04
1
Figure 41. FFT Plot, Low Power Mode at 32 kSPS, Input Frequency (fIN) = 1 kHz, Sinc5 Filter Enabled
–100
–125
THD
(dB
)
10.0
INPUT FREQUENCY (Hz)
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = –0.5dBFS
–120
–115
–110
–105
89.2
168.
424
7.6
326.
840
6.0
514.
960
4.0
703.
079
2.1
881.
296
0.4
1280
.018
40.0
2400
.029
60.0
3520
.040
80.0
4710
.052
70.0
5830
.064
60.0
7020
.075
80.0
1380
2-04
2
Figure 42. THD vs. Input Frequency at 16 kSPS, Low Power Mode, Sinc5 Filter Enabled
10.0
–100
–135
THD
(dB
)
INPUT FREQUENCY (Hz)
–130
–125
–120
–115
–110
–105
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = –0.5dBFS
49.6
89.2
128.
816
8.4
208.
024
7.6
287.
232
6.8
366.
440
6.0
455.
551
4.9
554.
560
4.0
643.
670
3.0
742.
679
2.1
841.
688
1.2
920.
896
0.4
1380
2-04
3
Figure 43. THD vs. Input Frequency at 4 kSPS, Low Power Mode,
Sinc3 Filter Enabled
Data Sheet AD7771
Rev. 0 | Page 23 of 98
–100
–140
0.17
2
4.64
4
THD
(dB
)
INPUT VOLTAGE (V)
–135
–130
–125
–120
–115
–110
–105
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VINPUT FREQUENCY = 50Hz
0.34
40.
516
0.68
80.
860
1.03
21.
204
1.37
61.
548
1.72
01.
892
2.06
42.
236
2.40
82.
580
2.75
22.
924
3.09
63.
268
3.44
03.
612
3.78
43.
956
4.12
84.
300
4.47
2
1380
2-04
4
Figure 44. THD vs. Input Voltage at 64 kSPS, High Resolution Mode
–125
1.0
3.3
REFERENCE VOLTAGE (V)
–90
–120
–105
–95
–110
–115
–100
THD
(dB
)
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°C±VREFINPUT FREQUENCY = 50Hz
1380
2-04
5
Figure 45. THD vs. Reference Voltage at 64 kSPS, High Resolution Mode
–100
–118
2126
00
THD
(dB
)
MCLK FREQUENCY (Hz)
–116
–114
–112
–110
–108
–106
–104
–102
5350
0085
7400
1179
800
1502
200
1824
600
2147
000
2469
400
2791
800
3114
200
3436
600
3759
000
4081
400
4403
800
4726
200
5048
600
5371
000
5693
400
6015
800
6338
200
6660
600
6983
000
7305
400
7627
800
7950
200
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VINPUT FREQUENCY = 50Hz
1380
2-04
6
Figure 46. THD vs. Master Clock Frequency, High Resolution Mode
–100
–140
0.17
2
4.64
4
THD
(dB
)
INPUT VOLTAGE (V)
–135
–130
–125
–120
–115
–110
–105
0.34
40.
516
0.68
80.
860
1.03
21.
204
1.37
61.
548
1.72
01.
892
2.06
42.
236
2.40
82.
580
2.75
22.
924
3.09
63.
268
3.44
03.
612
3.78
43.
956
4.12
84.
300
4.47
2
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VINPUT FREQUENCY = 50Hz
1380
2-04
7
Figure 47. THD vs. Input Voltage at 16 kSPS, Low Power Mode
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°C±VREFINPUT FREQUENCY = 50Hz
–125
1.0
3.3
REFERENCE VOLTAGE (V)
–90
–120
–105
–95
–110
–115
–100TH
D (d
B)
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
1380
2-04
8
Figure 48. THD vs. Reference Voltage at 16 kSPS, Low Power Mode
–100
–105
–110
–115
–120
–125
THD
(dB)
1043
20
MCLK FREQUENCY (Hz)
2656
0042
6880
5881
6074
9440
9107
2010
7200
012
3328
013
9456
015
5584
017
1712
018
7840
020
3968
022
0096
023
6224
025
2352
026
8480
028
4608
030
0736
031
6864
033
2992
034
9120
036
5248
038
1376
039
7504
0
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VINPUT FREQUENCY = 50Hz
1380
2-04
9
Figure 49. THD vs. Master Clock Frequency, Low Power Mode
AD7771 Data Sheet
Rev. 0 | Page 24 of 98
125
801000 16000
SNR
(dB)
ODR (SPS)
85
90
95
100
105
110
115
120
4000 8000
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = 0dBFS
1380
2-05
0
Figure 50. SNR vs. ODR at 16 kSPS, High Resolution Mode
(AVDDx = 3.6 V, IOVDD = 3.6 V)
115
808000 128000
SNR
(dB)
ODR (SPS)
85
90
95
100
105
110
32000 64000
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = 0dBFS
1380
2-05
1
Figure 51. SNR vs. ODR at 64 kSPS, High Resolution Mode
(AVDDx = 3.6 V, IOVDD = 3.6 V)
1 2 4 8PGA GAIN
108
96
100
98
102
104
106
DYN
AM
IC R
AN
GE
(dB
)
TA = 25°CODR = 16kSPS
1380
2-05
2
Figure 52. Dynamic Range vs. PGA Gain at 16 kSPS,
High Resolution Mode
500 2000 4000 8000ODR (SPS)
120
80
SNR
(dB
)
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = 0dBFS
85
90
95
100
105
110
115
1380
2-05
3
Figure 53. SNR vs. ODR at 4 kSPS, Low Power Mode
(AVDDx = 3.6 V, IOVDD = 3.6 V)
1000 8000 16000 32000
SNR
(dB)
ODR (SPS)
120
80
85
90
95
100
105
110
115
TA = 25°CVREF = 2.5VVIN = 0dBFS
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
1380
2-05
4
Figure 54. SNR vs. ODR at 16 kSPS, Low Power Mode
(AVDDx = 3.6 V, IOVDD = 3.6 V)
108
941 2 4 8
DYN
AM
IC R
AN
GE
(dB
)
PGA GAIN
TA = 25°CODR = 4kSPS
98
100
102
104
106
1380
2-05
5
Figure 55. Dynamic Range vs. PGA Gain at 4 kSPS,
Low Power Mode
Data Sheet AD7771
Rev. 0 | Page 25 of 98
104
82
DYN
AM
IC R
AN
GE
(dB
)
1 2 4 8PGA GAIN
TA = 25°CODR = 64kSPS
84
86
88
90
92
94
96
98
100
102
1380
2-05
6
Figure 56. Dynamic Range vs. PGA Gain at 64 kSPS,
High Resolution Mode
0
–401 8
OFF
SET
ERRO
R (µ
V)
TA = 25°CVREF = 2.5VVIN = 0VSUPPLY = AVDD1x = 3.3V
–35
–30
–25
–20
–15
–10
–5
2 4PGA GAIN
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
1380
2-05
7
Figure 57. Offset Error vs. PGA Gain at 64 kSPS,
High Resolution Mode
0
–25
–20
–15
–10
–5
3.0 3.3 3.6
OFF
SET
ERR
OR
(µV)
AVDD1x SUPPLY
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = 0V
1380
2-05
8
Figure 58. Offset Error vs. AVDD1x Supply,
High Resolution Mode
105
80
DYN
AM
IC R
AN
GE
(dB
)
TA = 25°CODR = 16kSPS
85
90
95
100
1 2 4 8PGA GAIN 13
802-
059
Figure 59. Dynamic Range vs. PGA Gain at 16 kSPS,
Low Power Mode
0
–35
–30
–25
–15
–5
–20
10
OFF
SET
ERRO
R (µ
V)
TA = 25°CVREF = 2.5VVIN = 0VSUPPLY = AVDD1x = 3.3V
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
1 82 4PGA GAIN 13
802-
060
Figure 60. Offset Error vs. PGA Gain at 16 kSPS,
Low Power Mode
3.0 3.3 3.6AVDD1x SUPPLY
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CVREF = 2.5VVIN = 0V
0
–25
–20
–15
–10
–5
OFF
SET
ERR
OR
(µV)
1380
2-06
1
Figure 61. Offset Error vs. AVDD1x Supply,
Low Power Mode
AD7771 Data Sheet
Rev. 0 | Page 26 of 98
–50
40
30
20
10
0
–10
–20
–30
–40
–40 –20 0 20 40 60 80 100 120
OFF
SET
DR
IFT
(µV)
TEMPERATURE (°C)
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
AVDD1x = 3.3V
1380
2-06
2
Figure 62. Offset Drift vs. Temperature
–0.043
–0.035
–0.026
–0.017
–0.008
0
0.008
0.017
3.0 3.3 3.6
GA
IN E
RR
OR
(%)
AVDD1x SUPPLY (V)
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
TEMPERATURE = 25°CGAIN = 1VREF = 2.5VVIN = 0dBFS
1380
2-06
3
Figure 63. Gain Error vs. AVDD1x Supply, High Resolution Mode
–40 25 105 125
GA
IN E
RR
OR
(%)
TEMPERATURE (°C)
AVDD1x = 3.3VVREF = 2.5VVIN = 0dBFS
–0.400
–0.035
–0.029
–0.023
–0.017
–0.011
–0.005
0
0.005
0.011
0.017CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
1380
2-06
4
Figure 64. Gain Error vs. Temperature, High Resolution Mode
–20
–15
–10
–5
0
5
10
15
20
25
30
45
40
35
0 500168 1000
GA
IN E
RR
OR
DR
IFT
(ppm
)
TIME (Hours) 1380
2-06
5
Figure 65. Gain Error Drift vs. Time
3.0 3.3 3.6
AVDD1x SUPPLY (V)
TEMPERATURE = 25°CGAIN = 1VREF = 2.5VVIN = 0dBFS
GA
IN E
RR
OR
(%)
–0.043
–0.035
–0.026
–0.017
–0.008
0
0.008
0.017CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
1380
2-06
6
Figure 66. Gain Error vs. AVDD1x Supply, Low Power Mode
–0.400
–0.035
–0.029
–0.023
–0.017
–0.011
–0.005
0
0.005
0.011
0.017
–40 25 105 125
GAI
N ER
ROR
(%)
TEMPERATURE (°C)
AVDD1x = 3.3VVREF = 2.5VVIN = 0dBFS
CH 0CH 1CH 2CH 3CH 4CH 5CH 6CH 7
1380
2-06
7
Figure 67. Gain Error vs. Temperature, Low Power Mode
Data Sheet AD7771
Rev. 0 | Page 27 of 98
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
1 2 4 8
GAI
N ER
ROR
(%)
PGA GAIN
HIGH RESOLUTIONLOW POWER
TEMPERATURE = 25°CAVDD1x = 3.3VVREF = 2.5VVIN = 0dBFS
1380
2-06
8
Figure 68. Channel Gain Mismatch
0.008
–0.010–40 125
TUE
AS
% O
F IN
PUT
TEMPERATURE (°C)
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
CH 0CH 1CH 2CH 3
CH 4CH 5CH 6CH 7
–30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110
VREF = 2.5VVIN = –0.5dBFSSUPPLY = AVDD1x = 3.3V
1380
2-06
9
Figure 69. Total Unadjusted Error (TUE) (as Percent of Input) vs. Temperature,
High Resolution Mode
3
–5
–3
0
2
–1
–4
–2
1
–2.5 –1.5 –0.5 0.5 1.5–2.0 –1.0 0 1.0 2.0 2.5
INPU
T C
UR
REN
T (n
A)
DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
VREF = 2.5VSUPPLY = AVDD1x = 3.3V
AINx+, VCM = 1.95VAINx–, VCM = 1.95VAINx+; VCM = 1.35VAINx–, VCM = 1.35V
1380
2-07
0
Figure 70. Input Current vs. Differential Input Voltage,
High Resolution Mode
–40 25 105 125
REF
EREN
CE
VOLT
AG
E D
RIF
T (m
V)
TEMPERATURE (°C)
–6
4
3
2
1
0
–1
–2
–3
–4
–5
1380
2-07
1
Figure 71. Internal Reference Voltage Drift
0.006
–0.008
TUE
AS %
OF
INPU
T
–0.006
–0.004
–0.002
0
0.002
0.004
–40 125TEMPERATURE (°C)
CH 0CH 1CH 2CH 3
CH 4CH 5CH 6CH 7
–30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110
VREF = 2.5VVIN = –0.5dBFSSUPPLY = AVDD1x = 3.3V
1380
2-07
2
Figure 72. Total Unadjusted Error (TUE) (as Percent of Input) vs.
Temperature, Low Power Mode
1.0
0.8
–0.8
–0.6
0
0.4
0.6
–0.2
–0.4
0.2
INPU
T C
UR
REN
T (n
A)
–2.5 –1.5 –0.5 0.5 1.5–2.0 –1.0 0 1.0 2.0 2.5DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
VREF = 2.5VSUPPLY = AVDD1x = 3.3V
AINx+, VCM = 1.95VAINx–, VCM = 1.95VAINx+; VCM = 1.35VAINx–, VCM = 1.35V
1380
2-07
3
Figure 73. Input Current vs. Differential Input Voltage,
Low Power Mode
AD7771 Data Sheet
Rev. 0 | Page 28 of 98
10
5
0
–5
–10
–15
AB
SOLU
TE IN
PUT
CU
RR
ENT
(nA
)
–60 –40 140120TEMPERATURE (°C)
–20 0 20 40 60 80 100
AIN0+AIN0–AIN2+AIN2–
VREF = 2.5VVIN = 2.5VSUPPLY = AVDD1x = 3.3V
1380
2-07
4
Figure 74. Absolute Input Current vs. Temperature, High Resolution Mode
4
–4
–2
1
3
0
–3
–1
2
DIF
FER
ENTI
AL
INPU
T C
UR
REN
T (n
A)
–2.5 –1.5 –0.5 0.5 1.5–2.0 –1.0 0 1.0 2.0 2.5DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
VREF = 2.5VSUPPLY = AVDD1x = 3.3V
AINx+ – AINx–, VCM = 1.95VAINx+ – AINx–, VCM = 1.35V
1380
2-07
5
Figure 75. Differential Input Current vs. Differential Input Voltage,
High Resolution Mode
14
12
10
8
6
4
2
0–60 140
DIF
FER
ENTI
AL
INPU
T C
UR
REN
T (n
A)
TEMPERATURE (°C)–40 –20 0 20 40 60 80 100 120
VREF = 2.5VVIN = 2.5VSUPPLY = AVDD1x = 3.3V
1380
2-07
6
Figure 76. Differential Input Current vs. Temperature,
High Resolution Mode
6
4
2
0
–2
–4
–6
–8
AB
SOLU
TE IN
PUT
CU
RR
ENT
(nA
)
–60 –40 140120TEMPERATURE (°C)
–20 0 20 40 60 80 100
VREF = 2.5VVIN = 2.5VSUPPLY = AVDD1x = 3.3V
AIN0+AIN0–AIN2+AIN2–
1380
2-07
7
Figure 77. Absolute Input Current vs. Temperature, Low Power Mode
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
VREF = 2.5VSUPPLY = AVDD1x = 3.3V
AINx+ – AINx–, VCM = 1.95VAINx+ – AINx–, VCM = 1.35V
DIF
FER
ENTI
AL
INPU
T C
UR
REN
T (n
A)
DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))–2.5 –1.5 –0.5 0.5 1.5–2.0 –1.0 0 1.0 2.0 2.5
1380
2-07
8
Figure 78. Differential Input Current vs. Differential Input Voltage,
Low Power Mode
12
10
8
6
4
2
0–40 140120
TEMPERATURE (°C)
DIF
FER
ENTI
AL
INPU
T C
UR
REN
T (n
A)
–20 0 20 40 60 80 100
VREF = 2.5VVIN = 2.5VSUPPLY = AVDD1x = 3.3V
1380
2-07
9
Figure 79. Differential Input Current vs. Temperature,
Low Power Mode
Data Sheet AD7771
Rev. 0 | Page 29 of 98
0
–140
250.
6083
17
CM
RR
(d
B)
INPUT FREQUENCY (Hz)
–120
–100
–80
–60
–40
–20
1102
2.18
5
2179
3.76
2
3296
1.35
3
4373
2.93
5450
4.50
7
6575
1.30
1
7652
2.87
8
8729
4.45
5
9862
0.45
1
1093
92.0
29
1201
63.6
06
1313
31.1
96
1421
02.7
73
1528
74.3
5
1640
41.9
41
1748
13.5
18
1855
85.0
95
1967
52.6
86
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VCM = 1.65V + 100mV p-pSUPPLY = AVDD1x = 3.3V + 100mV p-p
138
02-0
80
Figure 80. CMRR vs. Input Frequency at 128 kSPS, High Resolution Mode
0
–160
2001
4.97
AC
PS
R (
dB
)
INPUT FREQUENCY(Hz)
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
4600
14.3
188
0013
.68
1340
013.
0017
4001
2.00
2220
012.
0026
4001
1.00
3040
010.
0034
8001
0.00
3900
009.
0045
2000
8.00
4920
008.
0053
6000
7.00
5780
006.
0062
0000
6.00
6620
005.
0070
2000
4.00
7440
004.
0078
6000
3.00
8360
002.
0087
8000
2.00
9200
001.
0096
2000
1.00
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CSUPPLY = AVDD1x = 3.3V+100mVpp
13
80
2-0
81
Figure 81. AC PSRR vs. Input Frequency at 128 kSPS, High Resolution Mode
10
–120
AT
TE
NU
AT
ION
(d
B)
25
FREQUENCY (Hz)
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
5144
1026
315
382
2050
125
620
3073
935
858
4097
746
096
5121
556
334
6145
366
572
7169
176
810
8192
987
048
9216
797
286
1024
0510
7524
1126
4311
7762
1228
81
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
138
02-0
82
Figure 82. Filter Profiles at 64 kSPS, High Resolution Mode
0
–140
171.
0924
9
CM
RR
(d
B)
INPUT FREQUENCY (Hz)
–120
–100
–80
–60
–40
–20
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
VCM = 1.65V + 100mV p-pSUPPLY = AVDD1x = 3.3V + 100mV p-p
1092
1.38
2
2182
9.76
4
3273
8.14
5
4380
4.62
5455
4.90
9
6546
3.29
1
7637
1.67
3
8743
8.14
7
9834
6.52
9
1090
96.8
18
1201
63.2
92
1309
13.5
82
1418
21.9
64
1525
72.2
53
1636
38.7
27
1743
89.0
17
1851
39.3
06
1958
89.5
95
138
02-0
83
Figure 83. CMRR vs. Input Frequency at 32 kSPS, Low Power Mode
15.0
0
–160
AC
PS
R (
dB
)
INPUT FREQUENCY(Hz)
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10 GAIN = 1GAIN = 2GAIN = 4GAIN = 8
TA = 25°CSUPPLY = AVDD1x = 3.3V + 100mV p-p
4000
14.4
8000
13.8
1260
013.
0
1680
012.
0
2200
012.
0
2660
011.
0
3140
010.
0
3600
010.
0
4060
009.
045
2000
8.0
4980
008.
0
5420
007.
0
5880
006.
0
6340
005.
0
6800
005.
0
7260
004.
0
7720
003.
0
8180
003.
0
8620
002.
0
9080
001.
0
9540
001.
0
13
80
2-0
84
Figure 84. AC PSRR vs. Input Frequency at 32 kSPS, Low Power Mode
25
FREQUENCY (Hz)
0
–120
AT
TE
NU
AT
ION
(d
B)
GAIN = 1GAIN = 2GAIN = 4GAIN = 8
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1304
2583
3862
5141
6420
7699
8978
1025
711
536
1281
514
094
1537
316
652
1793
119
210
2048
921
768
2304
724
326
2560
526
884
2816
329
442
3072
1
138
02-0
85
Figure 85. Filter Profiles at 16 kSPS, Low Power Mode
AD7771 Data Sheet
Rev. 0 | Page 30 of 98
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6SUPPLY VOLTAGE (V)
20
18
16
14
12
10
8
6
4
2
0
SUPP
LY C
UR
REN
T (m
A)
AVDD1xAVDD2xAVDD4IOVDD
1380
2-08
6
Figure 86. Supply Current vs. Supply Voltage, High Resolution Mode
30
25
20
15
10
5
0–40
SUPP
LY C
UR
REN
T (m
A)
AVDD1xAVDD2xAVDD4IOVDD
120TEMPERATURE (°C)
–20 0 20 40 60 80 100
1380
2-08
7
Figure 87. Supply Current vs. Temperature High Resolution Mode
–800
–600
–400
–200
0
200
400
600
800
–35.
263
–29.
594
–22.
185
–15.
223
–7.3
66–0
.405
7.00
614
.429
22.0
6729
.170
36.6
4644
.122
52.0
0958
.557
66.0
6474
.427
81.4
4689
.252
96.2
3810
5.34
811
2.09
211
9.54
212
3.07
5
REF
EREN
CE
INPU
T C
UR
REN
T (n
A)
TEMPERATURE (°C)
REF1–REF1+REF2–REF2+
1380
2-08
8
Figure 88. Reference Input Current vs. Temperature, High Resolution Mode
6
5
4
3
2
1
0
SUPP
LY C
UR
REN
T (m
A)
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6SUPPLY VOLTAGE (V)
AVDD1xAVDD2xAVDD4IOVDD
1380
2-08
9
Figure 89. Supply Current vs. Supply Voltage, Low Power Mode
7
6
5
4
3
2
1
0–40 120
SUPP
LY C
UR
REN
T (m
A)
TEMPERATURE (°C)–20 0 20 40 60 80 100
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
0
Figure 90. Supply Current vs. Temperature Low Power Mode
–35.
263
–29.
594
–22.
185
–15.
223
–7.3
66–0
.405
7.00
614
.429
22.0
6729
.170
36.6
4644
.122
52.0
0958
.557
66.0
6474
.427
81.4
4689
.252
96.2
3810
5.34
811
2.09
211
9.54
212
3.07
5
REF
EREN
CE
INPU
T C
UR
REN
T (n
A)
TEMPERATURE (°C)
–600
–500
–400
–300
–200
–100
0
100
200
300
REF1–REF1+REF2–REF2+
1380
2-09
1
Figure 91. Reference Input Current vs. Temperature, Low Power Mode
Data Sheet AD7771
Rev. 0 | Page 31 of 98
0
80
70
60
50
40
30
20
10
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SHU
TDO
WN
SU
PPLY
CU
RR
ENT
(µA
)
SUPPLY VOLTAGE (V)
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
2
Figure 92. Shutdown Supply Current vs. Supply Voltage
60
50
40
30
20
10
0
POW
ER C
ON
SUM
PTIO
N (m
W)
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6SUPPLY VOLTAGE (V)
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
3
Figure 93. Power Consumption per Channel vs. Supply Voltage,
High Resolution Mode
90
80
70
50
60
30
40
10
20
0
POW
ER D
ISSI
PATI
ON
(mW
)
–40 120TEMPERATURE (°C)
–20 0 20 40 60 80 100
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
4
Figure 94. Power Dissipation vs. Temperature, High Resolution Mode
0
500
400
300
200
100
450
350
250
150
50
–60 –40 –20 0 20 40 60 80 100 140120
SHUT
DOW
N SU
PPLY
CUR
RENT
(µA)
TEMPERATURE (°C)
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
5
Figure 95. Shutdown Supply Current vs. Temperature
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6SUPPLY VOLTAGE (V)
20
18
16
14
12
10
8
6
4
2
0
POW
ER C
ON
SUM
PTIO
N (m
W)
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
6
Figure 96. Power Consumption per Channel vs. Supply Voltage,
Low Power Mode
25
20
10
15
5
0
POW
ER D
ISSI
PATI
ON
(mW
)
–40 120TEMPERATURE (°C)
–20 0 20 40 60 80 100
AVDD1xAVDD2xAVDD4IOVDD
1380
2-09
7
Figure 97. Power Dissipation vs. Temperature, Low Power Mode
AD7771 Data Sheet
Rev. 0 | Page 32 of 98
TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of AINx+ and AINx− at frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output.
Differential Nonlinearity (DNL) Error In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. DNL error is often specified in terms of resolution for which no missing codes are guaranteed.
Integral Nonlinearity (INL) Error Integral nonlinearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
Dynamic Range Dynamic range is the ratio of the rms value of the full-scale input signal to the rms noise measured for an input. The value for dynamic range is expressed in decibels.
Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale frequency sweep sine wave signal to all seven unselected input channels and determining how much that signal is attenuated in the selected channel. The value is given for worst case scenarios across all eight channels of the AD7771.
Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fA and fB, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfA and nfB, where m, n = 0,1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fA + fB) and (fA − fB and the third-order terms include (2fA + fB), (2fA − fB), (fA + 2fB), and (fA − 2fB). The AD7771 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels.
Gain Error The first transition (from 100 … 000 to 100 … 001) occurs at a level ½ LSB above nominal negative full scale (−2.49999 V for the ±2.5 V range). The last transition (from 011 … 110 to 011 … 111) occurs for an analog voltage 1½ LSB below the nominal full scale (2.49999 V for the ±2.5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels.
Gain Error Drift Gain error drift is the ratio of the gain error change due to a temperature change of 1°C and the full-scale range (2N). It is expressed in ppm/°C.
Least Significant Bit (LSB) The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is
LSB (V) = NREFV
22×
The LSB referred to the input is
LSB (VIN) = NGAIN
REF
PGAV
2
2×
Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the full-scale transition point due to a change in the power supply voltage from the nominal value.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal including harmonics.
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
Data Sheet AD7771
Rev. 0 | Page 33 of 98
Offset Error Offset error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.
Offset Error Drift Offset error drift is the ratio of the offset error change due to a temperature change of 1°C and the full-scale code range (2N). It is expressed in µV/°C.
AD7771 Data Sheet
Rev. 0 | Page 34 of 98
THEORY OF OPERATION The AD7771 is an 8-channel, simultaneously sampling, low noise, 24-bit Σ-Δ ADC with integrated digital filtering per channel and SRC.
The AD7771 offers two operation modes: high resolution mode, which offers up to 128 kSPS, and low power mode, which offers up to 32 kSPS.
The AD7771 employs a Σ-Δ conversion technique to convert the analog input signal into an equivalent digital word. The overview of the Σ-Δ technique is that the modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, fCLKIN.
Due to the high oversampling rate, this technique spreads the quantization noise from 0 Hz to fCLKIN/2 (in the case of the AD7771, fCLKIN relates to the external clock); therefore, the noise energy contained in the band of interest is reduced (see Figure 98). To further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (see Figure 99). The digital filter that follows the modulator removes the large out of band quantization noise (see Figure 100).
For more information on basic and advanced concepts of Σ-Δ ADCs, see the MT-022 Tutorial and MT-023 Tutorial.
Digital filtering has certain advantages over analog filtering. Because digital filtering occurs after the analog-to-digital conversion process, it can remove noise injected during the conversion. Analog filtering cannot remove noise injected during conversion.
QUANTIZATION NOISE
fCLKIN/2BAND OF INTEREST 13
802-
098
Figure 98. Σ-Δ ADC Operation, Reduction of Noise Energy Contained in the
Band of Interest (Linear Scale X-Axis)
fCLKIN/2
NOISE SHAPING
BAND OF INTEREST 1380
2-09
9
Figure 99. Σ-Δ ADC Operation, Majority of Noise Energy Shifted Out of the
Band of Interest (Linear Scale X-Axis)
fCLKIN/2BAND OF INTEREST
DIGITAL FILTER CUTOFF FREQUENCY
1380
2-10
0
Figure 100. Σ-Δ ADC Operation, Removal of Noise Energy from the Band of
Interest (Linear Scale X-Axis)
The Σ-Δ ADC starts the conversions of the input signal after the supplies generated by the internal LDO regulators become stable. An external signal is not required to generate the conversions.
ANALOG INPUTS The AD7771 can be operated in bipolar or unipolar modes and accepts true differential, pseudo differential, and single-ended input signals, as shown in Figure 101 through Figure 104.
Table 10 summarizes the maximum differential input signal and dynamic range for the different input modes.
Table 10. Input Signal Modes Input Signal Mode PGA Gain Maximum Differential Signal Maximum Peak-to-Peak Signal True differential All gains ±(VREF/PGAGAIN) 2 × VREF/PGAGAIN Pseudo differential All gains ±(VREF/PGAGAIN) 2 × VREF/PGAGAIN Single-ended All gains VREF/PGAGAIN VREF/PGAGAIN
Data Sheet AD7771
Rev. 0 | Page 35 of 98
BIPOLAR OR UNIPOLARTR
UE
DIF
FER
ENTI
AL
AVDD1x – 0.1V
AINx+AINx+
AVSSx + 0.1V
VCMVREF/PGAGAIN
1380
2-10
1
Figure 101. Σ-Δ ADC Input Signal Configuration, True Differential
BIPOLAR OR UNIPOLAR
PSEU
DO
DIF
FER
ENTI
AL
AVDD1x – 0.1V
AINx+AINx+
AVSSx + 0.1V
VCM
VREF/PGAGAIN13
802-
102
Figure 102. Σ-Δ ADC Input Signal Configuration, Pseudo Differential
BIPOLAR
SIN
GLE
-EN
DED
AINx+AINx+
AVSSx + 0.1V
VREF/PGAGAIN
1380
2-10
3
Figure 103. Σ-Δ ADC Input Signal Configuration, Single-Ended Bipolar
VREF/PGAGAIN
UNIPOLAR
SING
LE-E
NDED
AINx+AINx+
+ 0.1V
1380
2-10
4
Figure 104. Σ-Δ ADC Input Signal Configuration, Single-Ended Unipolar
The common mode input signal is not limited, but keep the absolute input signal voltage on any AINx± pin between AVSSx + 100 mV and AVDD1x − 100 mV; otherwise, the input signal linearity degrades and, if the signal voltage exceeds the absolute maximum signal rating, damages the device.
Figure 105 shows the maximum and minimum voltage common-mode range at different PGA gains for a maximum differential input voltage.
COM
MO
N-M
ODE
VO
LTAG
E (V
)
1.6500
1.2375
0.8250
0.4125
(AVDD1x + AVSSx)/2
–0.4125
PGA GAIN2 4 81
–0.8250
–1.2375
–1.6500
VREF = 2.5VAVDD1x = 1.65VAVSSx = –1.65V
TRUE DIFFERENTIALPSEUDO DIFFERENTIAL
1380
2-10
5
Figure 105. Maximum Common-Mode Voltage Range for a Maximum
Differential Input Signal
The AD7771 provides a common-mode voltage pin (AVDD1x + AVSSx)/2), VCM, for the single-supply, pseudo differential, or true differential input configurations.
TRANSFER FUNCTION The AD7771 can operate with up to a 3.6 V reference, typical at 2.5 V, and converts the differential voltage between the analog inputs (AINx+ and AINx−) into a digital output. The ADC converts the voltage difference between the analog input pins (AINx+ − AINx−) into a digital code on the output. The 24-bit conversion result is in MSB first, twos complement format, as shown in Table 11 and Figure 106.
Table 11. Output Codes and Ideal Input Voltages for PGA = 1×
Condition
Analog Input ((AINx+) − (AINx−)), VREF = 2.5 V
Digital Output Code, Twos Complement (Hexadecimal)
FS − 1 LSB +2.499999702 V 0x7FFFFF Midscale + 1 LSB +298 nV 0x000001 Midscale 0 V 0x000000 Midscale − 1 LSB −298 nV 0xFFFFFF −FS + 1 LSB −2.499999702 V 0x800001 −FS −2.5 V 0x800000
100 ... 000100 ... 001100 ... 010
011 ... 101011 ... 110011 ... 111
AD
C C
OD
E (T
WO
S C
OM
PLEM
ENT)
ANALOG INPUT
+FSR – 1.5LSB+FSR – 1LSB–FSR + 1LSB–FSR
–FSR + 0.5LSB
1380
2-10
6
Figure 106. Transfer Function
AD7771 Data Sheet
Rev. 0 | Page 36 of 98
MCLK START
Σ-ΔMODULATOR
SIGNAL CHAIN FOR CHANNEL x
CONTROL BLOCK
PIN CONTROL
CONTROLOPTION
PIN OR SPI
DIGITALFILTERSINC3/SINC5SRC
GAINSCALING
ANDOFFSET
CORRECTION
CONVERSIONDATA INTERFACE
MODE0 TO MODE3 CS SCLK SDO SDI
SYNC_OUT SYNC_IN RESET
DRDY
DOUTxDCLK
FORMAT0ANDFORMAT1
AINx+
PGAGAIN 1, 2, 4, 8
ESDPROTECTION
AINx–
SPI CONTROL
1380
2-10
7
Figure 107. Top Level Core Signal Chain
CORE SIGNAL CHAIN Each Σ-Δ ADC channel on the AD7771 has an identical signal path from the analog input pins to the digital output pins. Figure 107 shows a top level implementation of this signal chain. Prior to each Σ-Δ ADC, a PGA maps sensor outputs into the ADC inputs, providing low input current in dc (±8 nA, input current, and ±2 nA differential input current for high resolution mode), an 8 pF input capacitance in ac, and configurable gains of 1, 2, 4, and 8. See the AN-1392 Application Note for more information. Each ADC channel has its own Σ-Δ modulator, which oversamples the analog input and passes the digital representation to the digital filter block. The data is filtered, scaled for gain and offset, and is then output on the data interface.
To minimize power consumption, the channels can be individually disabled.
CAPACITIVE PGA Each Σ-Δ ADC has a dedicated PGA, offering gain ranges of 1, 2, 4, and 8. This PGA reduces the need for an external input buffer and allows the user to amplify small sensor signals to use the full dynamic range of the AD7771.
The PGA maximizes the signal chain dynamic range for small sensor output signals.
The AD7771 uses chopping of the PGA to minimize offset and offset drift in the input amplifier, reducing the 1/f noise as well. For the AD7771, the chopping frequency is set to 128 kHz for high resolution mode, and 32 kHz for low power mode (see the AN-1392 Application Note for more information). The chopping tone is rejected by the sinc3 or sinc5 filters.
To minimize intermodulation effects that may cause an image in the band of interest, it is recommended to limit the input signal bandwidth to 2/3 of the chop frequency.
The capacitive PGA common-mode voltage does not depend on the gain, and can be any value as long as the input signal voltage is within AVSSx + 100 mV to AVDD1x − 100 mV. See Figure 105
for the maximum common-mode voltage at maximum differential input signals.
INTERNAL REFERENCE AND REFERENCE BUFFERS The AD7771 integrates a 2.5 V, ±10 ppm/°C (typical), voltage reference that is disabled at power-up. The buffered reference is available at Pin 49 and offers up to 10 mA of continuous current. A 100 nF capacitor is required if the reference is enabled.
In applications where a low noise reference is required, it is recommended to add a low-pass filter (LPF) with a cutoff frequency (fCUTOFF) below 10 Hz to the REF_OUT pin. Connect the output of this filter to REFx+, and connect AVSSx to REFx−. In this scenario, configure the Σ-Δ reference as external. An example of performance with and without the output filter is shown in Figure 108.
115
105
95
85
75
SNR
(dB)
0.05 0.50 1.00 2.00 2.50
DIFFERENTIAL INPUT VOLTAGE (V)
VREF = INTERNAL REFERENCEfCUTOFF = 10Hz
1380
2-10
8
Figure 108. SNR Adding External LPF with VREF = Internal Reference and
fCUTOFF = 10 Hz
The AD7771 can be used with an external reference connected between the REFx+ and REFx− pins. Recommended reference voltage sources for the AD7771 include the ADR441 and ADR4525 family of low noise, high accuracy voltage references.
Data Sheet AD7771
Rev. 0 | Page 37 of 98
ADCMODULATOR
SINCFILTER
DATAINTERFACECONTROL
MCLK DIVIDERHIGH RESOLUTION MODE: MCLK/4
LOW POWER MODE: MCLK/8
DCLK DIVIDER1, 2, 4, 8, 16, 32, 64, 128
DEC RATES = ×16, ×32, ×64, ×128, ×256, ×512, ×1024, ×2048, ×4095.99
MOD_MCLKDCLKxDRDY
DOUT3TODOUT0
PGAAINx+
MCLK
AINx–
1380
2-10
9
Figure 109. Clock Generation on the AD7771
The reference buffers can be operated in three different modes: buffer enabled mode, buffer bypassed mode, and buffer precharged mode.
In buffer enabled mode, the buffer is fully enabled, minimizing the current requirements from the external references. Note that the buffer output voltage headroom is ±100 mV from the rails.
In buffer bypassed mode, the external reference is directly connected to the ADC reference capacitors; the reference must provide enough current to correctly charge the internal ADC reference capacitors. In this mode of operation, a degradation in crosstalk is expected because the ADC channels are not isolated from each other.
Buffer precharged (pre-Q) mode is the default operation mode. It is a hybrid mode where the internal reference buffers are connected during the initial acquisition time to precharge the internal ADC reference capacitors. During the final phase of the acquisition, the reference is connected directly to the ADC capacitors. This mode has some benefits compared to the buffer enabled and buffer bypassed modes. In buffer pre-Q mode, the reference current requirements are minimized compared to buffer bypassed mode and the noise contribution from the internal reference buffers is removed (compared to buffer enabled mode).
In buffer pre-Q mode, the headroom/footroom of the buffer reference is not applicable because the reference sets the final voltage in the ADC reference capacitors.
INTEGRATED LDOs The AD7771 has three internal LDOs to regulate the internal supplies: two LDOs for the analog block and one LDO for the digital core. The internal LDOs requires an external 1 µF decoupling capacitor on the DREGCAP, AREG1CAP, and the AREG2CAP pins. The LDO slew rate may be low because it depends on the main supply slew rate; therefore, a hardware reset generated by pulsing the RESET pin at power-up is required to guarantee that the digital block initializes correctly.
CLOCKING AND SAMPLING The AD7771 includes eight Σ-Δ ADC cores. Each ADC receives the same master clock signal. The AD7771 requires a maximum external MCLK frequency of 8192 kHz for high resolution mode and 4096 kHz for low power mode. The MCLK is internally divided by 4 in high performance mode and by 8 in low power mode to produce the modulator MCLK (MOD_MCLK) signal used as the modulator sampling clock for the ADCs. The MCLK can be decreased to accommodate lower ODRs if the minimum ODR selected by the sinc3 filter is not low enough. If the external clock is lower than 250 kHz, set the CLK_QUAL_DIS bit (in SPI control mode only).
The AD7771 integrates an internal oscillator clock that initializes the internal registers at power-up. The CLK_SEL pin defines the external clock used after initialization (see Table 12).
Table 12. Clock Sources CLK_SEL State Clock Source Connection 0 CMOS Input to XTAL2/MCLK, IOVDD
logic level. XTAL1 must be tied to DGND.
1 Crystal Connected between XTAL1 and XTAL2/MCLK.
The MCLK signal generates the DCLK output signal, which in turn clocks the Σ-Δ conversion data from the AD7771, as shown in Figure 109.
DIGITAL RESET AND SYNCHRONIZATION PINS An external pulse in the SYNC_IN pin generates the internal reset of the digital block; this pulse does not affect the data programmed in the internal registers. A pulse in this pin is required in two cases as follows:
• After updating one or more registers directly related to the sinc filter (power mode, offset, gain, phase compensation, and sinc filter).
• To synchronize multiple devices.
The pulse in the SYNC_IN pin must be synchronous with MCLK.
AD7771 Data Sheet
Rev. 0 | Page 38 of 98
There are two different ways to achieve a synchronous pulse if the controller/processor cannot generate it as follows:
• Applying an asynchronous pulse on the START pin, which is then internally synchronized with the external MCLK clock, and the resulting synchronous signal is output on the SYNC_OUT pin.
• Triggering the SYNC_OUT internally. When the AD7771 is configured in SPI control mode, toggling Bit 0 in the GENERAL_USER_CONFIG_2 register generates a synchronous pulse that is output on the SYNC_OUT pin.
The SYNC_IN and SYNC_OUT pins must be externally connected if internal synchronization is used.
If multiple AD7771 devices must be synchronized, the SYNC_OUT pin of one device can be connected to multiple devices. This synchronization method requires the use of a common MCLK signal for all the AD7771 devices connected, as shown in Figure 110.
If the START pin is not used, tie it to DGND.
START
SYNC_IN
IOVDD
MCLK SYNC_OUT
START
SYNC_IN
MCLK SYNC_OUTNC
START
SYNC_IN
MCLK SYNC_OUTNC
AD7771
AD7771
AD7771
SYNCHRONIZATIONLOGIC
ASYNCHRONOUSPULSE
DIGITAL FILTER
SYNCHRONIZATIONLOGIC
DIGITAL FILTER
SYNCHRONIZATIONLOGIC
DIGITAL FILTER
MCLK
IOVDD
1380
2-11
0
Figure 110. Multiple AD7771 Devices Synchronization
DIGITAL FILTERING The AD7771 offers low latency sinc3 and sinc5 filters. Most precision Σ-Δ ADCs use sinc filters because the sinc filters offer a low latency path for applications requiring low bandwidth signals, for example, in control loops or where application specific postprocessing is required. The digital filter adds notches at multiples of the sampling frequency.
The digital sinc3 filter implements three main notches, one at the maximum ODR (128 kHz or 32 kHz, depending on the power mode) and another two at the ODR frequency selected to stop noise aliasing into the pass band. The sinc5 filter implements five notches, one at the maximum ODR (128 kHz or 32 kHz, depending on the power mode) and another four at the ODR frequency selected to stop noise aliasing into the pass band. It is recommended to select the sinc5 digital filter for output data rates higher than 24 kSPS.
Figure 111 and Figure 112 show the typical filter transfer function for the high resolution and low power modes using a decimation rate of 32 samples for the sinc3 and sinc5 filters.
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 6432 96 128 160 192 224 256
GA
IN (d
B)
FREQUENCY (MHz) 1380
2-11
1
SINC3SINC5
Figure 111. Sinc3/Sinc5 Frequency Response in High Resoltuion Mode
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0 168 24 32 40 48 56 64
GA
IN (d
B)
FREQUENCY (MHz) 1380
2-11
2
SINC3SINC5
Figure 112. Sinc3/Sinc5 Frequency Response in Low Power Mode
The sample rate converter feature allows fine tuning of the decimation rate, even for noninteger multiples of the decimation rate. See the Sample Rate Converter (SRC) section for more information on filter profiles for noninteger decimation rates.
SHUTDOWN MODE The AD7771 can be placed in shutdown mode by pulling AVDD2x to ground and connecting 1 MΩ resistance, pulled low, to XTAL2/MCLK. In this mode, the average current consumption is reduced to 1 mA, as shown in Figure 113.
Data Sheet AD7771
Rev. 0 | Page 39 of 98
–40–0.5
0
0.5
1.0
10TEMPERATURE (°C)
60 125
IAVDD1xIAVDD2xIAVDD4IIOVDD
AVDDx = 3.3VIOVDD = 3.3V
SUPP
LY C
UR
REN
T (m
A)
1380
2-11
3
Figure 113. Shutdown Current
CONTROLLING THE AD7771 The AD7771 can be controlled using either pin control mode or SPI control mode.
Pin control mode allows the AD7771 to be hardwired to predefined settings that offer a subset of the overall functionality of the AD7771. In this mode, the SRC and diagnostic features or extended errors source are not available.
Controlling the AD7771 over the SPI allows the user access to the full monitoring, diagnostic, and Σ-Δ control functionality. SPI control offers additional functionality such as offset, gain, and phase correction per channel, in addition to access to the flexible SRC to achieve a coherent sampling.
See Table 13 for more details about these different configurations.
PIN CONTROL MODE In pin control mode, the AD7771 is configured at power-up based on the level of the mode pins, MODE0, MODE1, MODE2, and MODE3. These four pins set the following functions on the AD7771: the mode of operation, the decimation rate/ODR, the PGA gain, and the reference source, as shown in Table 14.
Due to the limited number of mode pins and the number of options available, the PGA gain control is grouped into blocks of 4, and the ODR is selected for the maximum value defined by the decimation rate; ODR (kHz) = 2048/decimation for high resolution mode, and ODR (kHz) = 512/decimation for low power mode.
Depending on the mode selected, the device is configured to use an external or an internal reference.
The conversion data can be read back using the SPI or the data output interface, as shown in Table 13. If the data output interface is used to read back the data from the conversions, the number of DOUTx lines enabled and the number of clocks required for the Σ-Δ data transfer are determined by the logic level of the CONVST_SAR, FORMAT0, and FORMAT1 pins. In this case, the DCLK2, DCLK1, and DCLK0 pins select the Σ-Δ output interface and control the DCLKx divide function, which is a submultiple of MCLK, as shown in Table 15. The DCLKx divide function sets the frequency of the data output interface DCLKx signal. The DCLK minimum frequency depends on the decimation rate and operation mode. See the Data Output Interface section for more details about the minimum DCLKx frequency.
All the pins that define the AD7771 configuration mode are reevaluated each time the SYNC_IN pin is pulsed. The typical connection diagram for pin control mode is shown in Figure 114.
Table 13. Format of the Data Interface CONVST_SAR State FORMAT1 FORMAT0 Control Mode Data Output Mode 1 0 0 Pin SPI output 0 1 Pin SPI output 1 1 Pin SPI output 1 1 SPI Defined in Register 0x014 0 0 0 Pin DOUT0, Channel 0 and Channel 1 DOUT1, Channel 2 and Channel 3 DOUT2, Channel 4 and Channel 5 DOUT3, Channel 6 and Channel 7 0 1 Pin DOUT0, Channel 0 to Channel 3 DOUT1, Channel 4 to Channel 7 1 0 Pin DOUT0, Channel 0 to Channel 7 1 1 SPI Defined in Register 0x014
AD7771 Data Sheet
Rev. 0 | Page 40 of 98
Table 14. Pin Control Mode Options Pin State
Decimation Rate Power Mode
PGA Gain Channel Reference Source Filter MODE3 MODE2 MODE1 MODE0
Channel 0 to Channel 3
Channel 4 to Channel 7
0 0 0 0 16 High resolution 1 1 External Sinc5 0 0 0 1 16 High resolution 1 4 External Sinc5 0 0 1 0 32 High resolution 1 1 External Sinc5 0 0 1 1 32 High resolution 1 4 External Sinc5 0 1 0 0 64 High resolution 1 1 External Sinc5 0 1 0 1 64 High resolution 1 4 External Sinc5 0 1 1 0 128 High resolution 1 1 External Sinc5 0 1 1 1 128 High resolution 1 4 External Sinc5 1 0 0 0 256 High resolution 1 1 External Sinc5 1 0 0 1 16 High resolution 1 1 Internal Sinc5 1 0 1 0 32 High resolution 1 1 Internal Sinc5 1 0 1 1 64 High resolution 1 1 Internal Sinc5 1 1 0 0 16 Low power 1 1 External Sinc5 1 1 0 1 32 Low power 1 1 External Sinc5 1 1 1 0 64 Low power 1 1 External Sinc3 1 1 1 1 32 Low power 1 1 External Sinc3
Table 15. DCLKx Selection for Pin Control Mode State DCLK2/SCLK DCLK1/SDI DCLK0/SDO MCLK Divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
Data Sheet AD7771
Rev. 0 | Page 41 of 98
ADCDATA
SERIALINTERFACE
SPICONTROL
INTERFACE
FPGAOR
DSP
AVDD 3.3V
EXTERNALREFERENCE
AVSSx
AVSSx
AIN7+
AIN7–
AIN0+
AIN0–PGA
VCM
AVDD1x
BUFFER
BUFFER AD7771DREGCAP
CONVST_SARMODE3TO
MODE0
REFx+ REFx– REF_OUTAVDD4
AVSSxAVSSx
AVDD2x
AVDD3.3V AVDD3.3V IOVDD 2V TO 3.6V
AVSSx
AREGxCAP
AVSSxAVSSx
IOVDD
24-BITΣ-ΔADC
SINC3/SINC5SRC
SYNC_IN
DRDY
SYNC_OUTSTARTRESET
DCLK
CSSCLKSDO
CLK_SEL
XTAL2 DCLK2TO
DCLK0
XTAL1
DOUT0DOUT1
SPI/SPORTSLAVE
INTERFACE
DOUT2DOUT3
SPIMASTER
INTERFACE
PGA
VCM
SDI
FORMAT1AND
FORMAT0
CLOCKSOURCE 13
802-
114
Figure 114. Pin Control Mode Connection Diagram with External Reference
ADCDATA
SERIALINTERFACE
SPICONTROL
INTERFACE
FPGAOR
DSP
AVDD 3.3V
AVSSx
AVSSx
AIN7+
AIN7–
AIN0+
AIN0–PGA
VCM
AVDD1x
BUFFER
FULL BUFFER
BUFFER AD7771DREGCAP
CONVST_SARGPIO2TO
GPIO0
REFx+ REFx– REF_OUT AVDD4
AVSSx
AVDD2x
AVDD3.3V IOVDD 2V TO 3.6V
AVSSx
AREGxCAP
AVSSxAVSSx
IOVDD
AUXAIN+
AUXAIN–
24-BITΣ-ΔADC
12-BITSAR ADCMUX
DIAGNOSTICINPUTS
SINC3/SINC5SRC
SYNC_IN
DRDY
SYNC_OUTSTARTRESET
DCLK
CSSCLKSDOSDI
CLK_SEL
FORMAT0XTAL2 FORMAT1
IOVDD IOVDD
XTAL1
DOUT0DOUT1
SPI/SPORTSLAVE
INTERFACE
DOUT2DOUT3
SPIMASTER
INTERFACE
PGA
VCM
CLOCKSOURCE 13
802-
115
Figure 115. SPI Control Mode Connection Diagram with Internal Reference
AD7771 Data Sheet
Rev. 0 | Page 42 of 98
SPI CONTROL The second option for control and monitoring the AD7771 is via the SPI. This option allows access to the full functionality on the AD7771, including access to the SAR converter, phase synchronization, offset and gain adjustment, diagnostics, and the SRC. To use the SPI control, set the FORMAT0 and FORMAT1 pins to logic high.
In this mode, the SPI can also read the Σ-Δ conversation data by setting the SPI_SLAVE_MODE_EN bit.
The typical connection diagram for SPI control mode is shown in Figure 115.
Functionality Available in SPI Control Mode
SPI control of the AD7771 offers the super set of the functions and diagnostics. The SPI Control Functionality section describes the functionality and diagnostics offered when in SPI control mode.
Offset and Gain Correction
Offset and gain registers are available for system calibration. The gain register is preprogrammed during final production for a PGA gain of 1, but can be overwritten with a new value if required.
The gain register is 24 bits long and is split across three registers, CHx_GAIN_UPPER_BYTE, CHx_GAIN_MID_BYTE, and CHx_GAIN_LOWER_BYTE, which set the gain on a per channel basis.
The gain value is relative to 0x555555, which represents a gain of 1.
The offset register is 24 bits long and is spread across three byte registers, CHx_OFFSET_UPPER_BYTE, CHx_OFFSET_MID_ BYTE, and CHx_OFFSET_LOWER_BYTE. The default value is 0x000000 at power-up. Program the offset as a twos complement, signed 24-bit number. If the channel gain is set to its nominal value of 0x555555, an LSB of offset register adjustment changes the digital output by −4/3 LSBs.
As an example of calibration, the offset measured is −200 LSB (with both AINx± pins connected to the same potential).
An offset adjustment of −150 LSB changes the digital output by −150 × (−4/3) = 200 LSBs (gain value = 0x555555), representing this number as two complement, 0xFFFFFF − 0x96 + 1 = 0xFFFF70. Program the offset register as follows:
• CHx_OFFSET_UPPER_BYTE = 0xFF • CHx_OFFSET_MID_BYTE = 0xFF • CHx_OFFSET_LOWER_BYTE = 0x70
Note that the offset compensation is performed before the gain compensation. The gain is programmed during final testing for PGAGAIN = 1. The gain register values can be overwritten; however, after a reset or power cycle, the gain register values revert to the hard coded programmed factory setting.
If the gain required is 0.75 of the nominal value (0x555555), the value that must be programmed is
0x555555 × 0.75 = 0x400000
Then, an LSB of the offset register adjustment changes the digital output by −4/3 × 0.75 = 1 LSB. Program the gain register as follows:
• CHx_GAIN_UPPER_BYTE = 0x40 • CHx_GAIN_MID_BYTE = 0x00 • CHx_GAIN_LOWER_BYTE = 0x00
SPI Control Functionality
Global Control Functions
The following list details the global control functions of the AD7771:
• High resolution and low power modes of operation • ODR: SRC • Sinc3 and sinc5 filters • VCM buffer power-down • Internal/external reference selection • Enable, pre-Q, or bypassed reference buffer modes • Internal reference power-down • SAR diagnostic mux • SAR power-down • GPIO write/read • SPI SAR conversion readback • SPI slave mode—read Σ-Δ results • SDO and DOUTx drive strength • DOUTx mode • DCLK division • Internal LDO bypassed • Cyclic redundancy check (CRC) protection: enabled or
disabled
Per Channel Functions
The following list details the per channel functions of the AD7771:
• PGA gain. • Σ-Δ channel power-down. • Phase delay: synchronization phase offset per channel. • Calibration of offset. • Calibration of gain. • Σ-Δ input signal mux. • Channel error register. • PGA gain.
Phase Adjustment
The AD7771 phase delay can be adjusted to compensate for phase mismatches between channels due to sensors or signal channel phase errors connected to the AD7771. Achieve phase adjustment by programming the CHx_SYNC_OFFSET register. This programming delays the synchronization signal by a certain number of modulator clocks (MOD_MCLK) to individually initiate the digital filter for each Σ-Δ ADC.
The phase adjustment register is read during the pulse; conse-quently, any further changes on the register have no effect unless a pulse is generated (see the Digital Reset and Synchronization
Data Sheet AD7771
Rev. 0 | Page 43 of 98
Pins section for more information on how to generate a pulse in the pin).
The phase offset register is multiplied internally by a factor that depends on the decimation rate, as shown in Table 16.
Table 16. Phase Adjustment vs. Decimation Rate Phase Adjustment Compensation Decimation Rate ×1 ≤255 ×2 ≤511 ×4 ≤1023 ×8 ≤2047 ×16 ≤4095
The maximum phase delay cannot be equal to or greater than the decimation rate. If this is the case, the value changes internally to the decimation rate value minus 1.
As an example, the phase mismatch between Channel 0 and Channel 1 is 5°, and the ODR is 5 kSPS in high resolution mode. In this case, the decimation rate is 2048 kHz/5 kHz = 409.6, which means that the offset register value is multiplied internally by 2.
Assuming an input signal of 50 Hz, the number of MOD_ MCLK pulses required to sample a full period is 2048 kHz/ 50 Hz = 40960 > 360°/40960 = 0.00878°.
If a 5° delay is required, the number of MOD_MCLK delays must be 569 (5°/0.00878°) because the offset register is multiplied by 2; the final offset register value is 409.6/2 − 569/2, which gives a negative value. In this case, if the offset value programmed to the register is higher than 204 (for example, 210 × 2 = 420), the value is internally changed to 408, resulting in a phase compensation of 408 × 0.00878° = 3.58°.
PGA Gain
The PGA gain can be selected individually by appropriately select-ing Bits[7:6] in the CHx_CONFIG register, as shown in Table 17.
Table 17. PGA Gain Settings via CHx_CONFIG CHx_CONFIG, Bits[7:6] Setting PGA Gain Setting 00 ×1 01 ×2 10 ×4 11 ×8
If the Σ-Δ reference is updated, it is recommended to apply a pulse on the SYNC_IN pin to remove invalid samples during the transition of the reference.
Decimation
The decimation defines the sampling frequency as follows:
• In high resolution mode, the sampling frequency = MCLK/ (4 × decimation)
• In low power mode, the sampling frequency = MCLK/ (8 × decimation)
Refer to the Sample Rate Converter (SRC) section for more information.
GPIOx Pins
If the AD7771 operates in SPI control mode, the mode pins operate as GPIOx pins, as shown in Figure 116. The GPIOx pins can be configured as inputs or outputs in any order.
REGISTERMAP
GPIO0
GPIO1
GPIO2
1380
2-11
6
Figure 116. GPIOx Pin Functionality
Configuration control and readback of the GPIOx pins are set via Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 = output) and the GPIO_DATA register. Among other uses, the GPIOs can control an external mux connected to the auxiliary inputs of the SAR ADC. Use this mux to verify the results on the Σ-Δ ADCs.
In addition, the GPIOx pins can be used to externally trigger a new decimation rate. Refer to the Sample Rate Converter (SRC) section for more information about this functionality.
Σ-Δ Reference Configuration
The AD7771 can operate with internal or external references. In addition, for diagnostic purposes, the analog supply can be used as a reference, as shown in Table 18. REFx−/REFx+ allow the selection of a voltage reference where the REFx+ voltage is lower than the voltage on the REFx− pin.
Table 18. Σ-Δ References Setting for ADC_MUX_CONFIG, Bits[7:6]
Channel 0 to Channel 3
Channel 4 to Channel 7
00 REF1+/REF1− REF2+/REF2− 01 Internal reference Internal reference 10 AVDD1A/AVSS1A AVDD1B/AVSS1B 11 REF1−/REF1+ REF2−/REF2+
Reference buffer operation is described in Table 19. The selected reference and buffer operation mode affect all channels.
If the Σ-Δ reference is updated, it is recommended to apply a pulse on the SYNC_IN pin to remove invalid samples during the transition of the reference.
AD7771 Data Sheet
Rev. 0 | Page 44 of 98
Table 19. Reference Buffer Operation Modes Reference Buffer Operation Mode REFx+ REFx− Enabled BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0 BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0 Precharged BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1 BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1 Disabled BUFFER_CONFIG_1, Bit 4 = 0 BUFFER_CONFIG_1, Bit 3 = 0
Table 20. Additional Disable Power-Down Blocks Block Register Notes VCM GENERAL_USER_CONFIG_1, Bit 5 Enabled by default Reference Buffer BUFFER_CONFIG_1, Bits[4:3] Precharge mode by default Internal Reference Buffer GENERAL_USER_CONFIG_1, Bit 4 Disabled by default Σ-Δ Channel CH_DISABLE, Bits[7:0] All channels enabled SAR GENERAL_USER_CONFIG_1, Bit 3 Disabled by default Internal Oscillator GENERAL_USER_CONFIG_1, Bit 2 Enabled by default
Power Modes
The AD7771 offers different power modes to improve the power efficiency, high resolution and low power mode, which can be controlled via GENERAL_USER_CONFIG_1, Bit 6. To further reduce the power, additional blocks can be disabled independently, as described in Table 20.
If the power mode changes, a pulse on the SYNC_IN pin is required.
Sinc3 and Sinc5 Filters
The AD7771 implements sinc3 and sinc5 digital filters. By default, the device powers up with the sinc3 filter, but it can be changed by setting GENERAL_USER_CONFIG_2, Bit 6. If the sinc filter is changed, a pulse in the SYNC_IN pin is required.
LDO Bypassing
The internal LDOs can be individually bypassed and an external supply can be applied directly to the AREG1CAP, AREG2CAP, or DREGCAP pin. Table 21 shows the absolute minimum and maximum supplies for these pins, as well as the associated register used to bypass the regulator.
Table 21. LDO Bypassing
LDO BUFFER_CONFIG_2, Bits[2:0]1
Supply Max (V) Min (V)
AREG1CAP 1XX 1.9 1.85 AREG2CAP X1X 1.9 1.85 DREGCAP XX1 1.9 1.65 1 X means don’t care.
DIGITAL SPI The SPI serial interface on the AD7771 consists of four signals: CS, SDI, SCLK, and SDO. A typical connection diagram of the SPI is shown in Figure 117.
DSP/FPGAAD7771
CS
SCLK
SDI
SDO
1380
2-11
7
Figure 117. SPI Control Interface—AD7771 is the SPI Slave, Digital Signal
Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master
The SPIs operates in Mode 0 and Mode 3, CPOL = 0, CPHA = 0 (Mode 0) or CPOL = 1, CPHA = 1 (Mode 3).
In pin control mode, the SDI can read back the Σ-Δ results, depending on the level of the CONVST_SAR pin, as described in Table 13.
In SPI control mode, the SPI transfers data into the on-chip registers while the SDO pin reads back data from the on-chip registers or reads the SAR or the Σ-Δ conversions results, depending on the selected operation mode.
The SDO data source in SPI control mode is defined by the GENERAL_USER_CONFIG_2 and GENERAL_USER_ CONFIG_3 registers, as described in Table 22.
Table 22. SPI Operation Mode in SPI Control Mode GENERAL_USER_ CONFIG_2, Bit 5 Setting
GENERAL_USER_ CONFIG_3, Bit 4 Setting1 Mode
0 0 Internal register 0 1 Σ-Δ data conversion 1 X SAR conversion 1 X means don’t care.
Data Sheet AD7771
Rev. 0 | Page 45 of 98
In SPI control mode, there are four different levels of input/ output (I/O) strength on the SDO pin that can be selected in GENERAL_USER_CONFIG_2, Bits[4:3], as described in Table 23.
Table 23. SDO Strength GENERAL_USER_CONFIG_2, Bits[4:3] Setting Mode 00 Nominal 01 Strong 10 Weak 11 Extra strong
SCLK is the serial clock input for the device. All data transfers (on either SDO or SDI) occur with respect to this SCLK signal.
The SPI can operate in multiples of eight bits. For example, in SPI control mode, if the SDO pin is used to read back the data from the internal register or the SAR ADC, the data frame is 16 bits wide (CRC disabled), as shown in Figure 118, or 24 bits wide (CRC enabled), as shown in Figure 119. In this case, the controller can generate one frame of 16 bits or 24 bits (with and without the CRC enabled), or two or three frames of 8 bits (with and without the CRC enabled). When the SDO pin reads back the data from the Σ-Δ channels, 64 bits must be read back from the controller (in this case, the controller can generate a frame of 64 bits—either 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits).
SPI CRC—Checksum Protection (SPI Control Mode)
The AD7771 has a checksum mode that improves SPI robustness in SPI control mode. Using the checksum ensures that only valid data is written to a register and allows data read from the device to be validated. The SPI CRC can be enabled by setting the SPI_CRC_TEST_EN bit. If an error occurs during a register write, the SPI_CRC_ERR is set in the error register.
Enabling the SPI_CRC_TEST_EN bit results in a CRC checksum being performed on all the R/W operations. When SPI_CRC_ TEST_EN is enabled, an 8-bit CRC word is appended to every SPI transaction for SAR and register map operations. For more information on Σ-Δ readback operations, see the CRC Header section.
To ensure that the register write is successful, it is recommended to read back the register and verify the checksum.
For CRC checksum calculations, the following polynomial is always used: x8 + x2 + x + 1. See the SPI Control Mode Checksum section for more information.
SPI Read/Write Register Mode (SPI Control Mode)
The AD7771 has on-board registers to configure and control the device.
The registers have 7-bit addresses—the 7-bit register address on the SDI line selects the register for the read/write function. The 7-bit register address follows the R/W bit in the SDI data. The 8 bits on the SDI line following the 7-bit register address are the data to be written to the selected register if the SPI is a write transfer. Data on the SDI line is clocked into the AD7771 on the rising edge of SCLK, as shown in Figure 3.
The data on the SDO line during the SPI transfer contains the 8-bit 0010 0000 header: 8 bits of register data in the case of a read (R) operation, or 8 zeros in the case of a write (W) operation.
With the CRC disabled, the basic data frame on the SDI line during the transfer is 16 bits long, as shown in Figure 118. When the CRC is enabled, a minimum frame length of 24 SCLK periods are required on SPI transfers. The 24 bits of data on the SDO line consist of an 8-bit header (0010 0000), 8 bits of data, and an 8-bit CRC (see Figure 119).
R/W A6 A5 A4 A3 A2 A1 A0 D6D7 D5 D4 D3 D2 D1 D0
0SDO
CS
SCLK
SDI
0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0
1380
2-11
8
Figure 118. 16-Bit SPI Transfer—CRC Disabled
R/W A6 A5 A4 A3 A2 A1 A0 D6D7 D5 D4 D3 D2 D1 D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
0SDO
CS
SCLK
SDI
0 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
1380
2-11
9
Figure 119. 24-Bit SPI Transfer—CRC Enabled
AD7771 Data Sheet
Rev. 0 | Page 46 of 98
SPI SAR Diagnostic Mode (SPI Control Mode)
Setting Bit 5 in the GENERAL_USER_CONFIG_2 register configures the SDO line to shift out data from the SAR ADC conversions, as described in Table 22.
In SAR mode, the AD7771 internal registers can be written to, but any readback command is ignored because the SDO data frame is dedicated to shift out the conversion results from the SAR ADC.
To exit this mode of operation, reset Bit 5 in the GENERAL_ USER_CONFIG_2 register.
The data on the SDO line during the SPI transfer contains a 4-bit 0010 header and the 12-bit SAR conversion result if the CRC is disabled.
When the CRC is enabled, a minimum frame length of 24 SCLK periods is required on SPI transfers. The 24 bits of data on the SDO line consist of a 4-bit header (0010), the 12-bit data, and an 8-bit CRC, as shown in Figure 120.
Per the SPI read/write register mode (see the SPI Read/Write Register Mode section), the SDI line contains the R/W bit, a 7-bit register address, the 8-bit data, and an 8-bit CRC (if enabled). To avoid unwanted writes to the internal register while the SAR conversions are read back through the SDO line, it is recom-mended to send a readback command, for example, 0x8000,
to the device, which is ignored because the SDO pin shifts out the content of the SAR ADC.
If consecutive conversions are performed in the SAR ADC, read back the result from the previous conversion before a new conversion is generated. Otherwise, the results are corrupted.
Σ-Δ Data, ADC Mode
In pin control mode, the SPI can be used to read back the Σ-Δ conversions as described in Table 13. In SPI control mode, the SPI reads back the Σ-Δ conversions by setting GENERAL_USER_ CONFIG_3, Bit 4, as described in Table 22; in this mode, the AD7771 internal register can be written to, but any readback command is ignored because the SDO data frame is dedicated to shifting out the conversion results from the Σ-Δ ADCs. To avoid unwanted writes to the internal register, it is recommended to send a readback command, for example, 0x8000, to the device, which is ignored because the SDO pin shifts out the content of the Σ-Δ ADC.
The SDO pin data can be read back in any multiple of 8 bits, for example, as 64 bits, 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits.
SPI Software Reset
Keeping the SDI pin high during 64 consecutives clocks generates a software reset.
R/W A6 A5 A4 A3 A2 A1 A0 D6D7 D5 D4 D3 D2 D1 D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
0SDO
CS
SCLK
SDI
0 1 0 SAR11
SAR10
SAR9
SAR8
SAR6
SAR7
SAR5
SAR4
SAR3
SAR2
SAR1
SAR0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
1380
2-12
0
Figure 120. SAR ADC/Diagnostic Mode—CRC Enabled
Data Sheet AD7771
Rev. 0 | Page 47 of 98
RMS NOISE AND RESOLUTION Table 24 through Table 27 show the dynamic range (DR), rms noise (RTI), effective number of bits (ENOB), and effective resolution (ER) of the AD7771 for various output data rates and gain settings. The numbers given are for the bipolar input range with an external 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel.
It is important to note that the effective resolution is calculated using the rms noise; 16,384 consecutives samples were used to calculate the rms noise.
Effective Resolution = log2(Input Range/RMS Noise)
ENOB = (DR − 1.78)/6
HIGH RESOLUTION MODE
Table 24. DR and RTI for High Resolution Mode
Sinc Filter
Decimation Rate
Output Data Rate (SPS)
f−3 dB (Hz)
Gain = 1 Gain = 2 Gain = 4 Gain = 8
DR (dB)
RTI (µV rms)
DR (dB)
RTI (µV rms)
DR (dB)
RTI (µV rms)
DR (dB)
RTI (µV rms)
Sinc5 16 128,000 26542.34 95.1 31.32 91.7 22.68 87.1 19.39 82.0 17.11 32 64,000 13403.14 101.8 14.31 98.5 10.30 94.4 8.41 89.7 7.37 64 32,000 6833.54 107.1 7.90 105.3 4.85 101.5 3.65 96.9 3.14 256 8,000 1906.34 114.4 3.34 113.8 1.84 111.6 1.16 107.9 0.91
Sinc3 128 16,000 4878.83 105.7 9.01 105.2 4.88 103.2 2.99 99.6 2.26 256 8,000 2756.43 112.1 4.32 111.5 2.31 109.3 1.52 105.5 1.19 512 4,000 1695.23 115.8 2.86 115.6 1.51 113.5 0.96 109.5 0.75 1024 1,000 899.33 122.0 1.39 121.6 0.73 119.6 0.47 115.7 0.36
Table 25. ENOB and ER for High Resolution Mode
Sinc Filter
Decimation Rate
Output Data Rate (SPS)
f−3 dB (Hz)
Gain = 1 Gain = 2 Gain = 4 Gain = 8
ENOB (Bits)
ER (Bits)
ENOB (Bits)
ER (Bits)
ENOB (Bits)
ER (Bits)
ENOB (Bits)
ER (Bits)
Sinc5 16 128,000 26542.34 15.5 17.3 14.9 17.8 14.2 18.0 13.3 18.2 32 64,000 13403.14 16.6 18.4 16.1 18.9 15.4 19.2 14.6 19.4 64 32,000 6833.54 17.5 19.3 17.2 20.0 16.6 20.4 15.8 20.6 256 8,000 1906.34 18.7 20.5 18.6 21.4 18.2 22.0 17.6 22.4
Sinc3 128 16,000 4878.83 17.3 19.1 17.2 20.0 16.9 20.7 16.3 21.1 256 8,000 2756.43 18.3 20.1 18.2 21.0 17.9 21.6 17.2 22.0 512 4,000 1695.23 18.9 20.7 18.9 21.7 18.6 22.3 17.9 22.7 1024 1,000 899.33 20.0 21.8 19.9 22.7 19.6 23.3 18.9 23.7
AD7771 Data Sheet
Rev. 0 | Page 48 of 98
LOW POWER MODE
Table 26. DR and RTI for Low Power Mode
Sinc Filter
Decimation Rate
Output Data Rate (SPS)
f−3 dB (Hz)
Gain = 1 Gain = 2 Gain = 4 Gain = 8
DR (dB)
RTI (µV rms)
DR (dB)
RTI (µV rms)
DR (dB)
RTI (µV rms)
DR (dB)
RTI (µV rms)
Sinc5 16 32,000 6833.54 94.3 34.2 90.9 25.04 86.5 20.5 81.3 19.43 32 16,000 3548.74 100.9 15.7 97.8 11.22 93.6 9.0 87.9 8.39 64 8,000 1906.34 106.7 83.3 104.6 5.18 100.6 4.03 96.1 3.46 512 1,000 469.24 117.1 25.2 116.8 1.29 114.4 8.41 110.7 0.67
Sinc3 64 8,000 2756.43 95.5 29.86 95.0 15.26 93.7 8.9 90.8 6.11 128 4,000 1695.23 105.4 9.47 105.1 4.95 102.7 3.21 98.7 2.51 256 2,000 1164.63 111.7 4.62 111.2 2.41 108.9 1.57 104.8 1.27 1024 500 766.68 118.6 2.1 118.2 1.07 116.2 0.7 112.5 0.54
Table 27. ENOB and ER for Low Power Mode
Sinc Filter
Decimation Rate
Output Data Rate (SPS)
f−3 dB (Hz)
Gain = 1 Gain = 2 Gain = 4 Gain = 8
ENOB (Bits)
ER (Bits)
ENOB (Bits)
ER (Bits)
ENOB (Bits)
ER (Bits)
ENOB (Bits)
ER (Bits
Sinc5 16 32,000 6833.54 15.4 17.2 14.8 17.6 14.1 17.9 13.2 18.0 32 16,000 3548.74 16.5 18.3 16.0 18.8 15.3 19.1 14.3 19.2 64 8000 1906.34 17.4 15.9 17.1 19.9 16.4 20.2 15.7 20.5 512 1000 469.24 19.2 17.6 19.1 21.9 18.7 19.2 18.1 22.8
Sinc3 64 8,000 2756.43 15.6 17.4 15.5 18.3 15.3 19.1 14.8 19.6 128 4,000 1695.23 17.2 19.0 17.2 19.9 16.8 20.6 16.1 20.9 256 2,000 1164.63 18.3 20.0 18.2 21.0 17.8 21.6 17.1 21.9 1024 500 766.68 19.4 21.2 19.3 22.2 19.0 22.8 18.4 23.1
Data Sheet AD7771
Rev. 0 | Page 49 of 98
DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR The AD7771 includes self diagnostic features to guarantee the correct operation. If an error is detected, the ALERT pin (Pin 18 when using pin control mode or Pin 16 when using SPI control mode) is pulled high to generate an external interruption to the controller. In addition, the header of the Σ-Δ output data contains an alert bit that informs the controller of a chip error (see the ADC Conversion Output—Header and Data section).
Both the ALERT pin and bit (status header) are automatically cleared if the error is no longer present. The errors related to the SPI do not recover automatically; read back the appropriate register to clear the error. The ALERT pin and bit reset in the next SPI access after the bit is read back.
If an error detector is manually disabled, it does not generate an internal error and, consequently, the register map or the ALERT pin and bit are not triggered.
There are different sources of errors, as described in Table 28. In pin control code, it is not possible to check the error source, and some sources of error are not enabled. In SPI control mode, check the source of an error by reading the appropriate register bit.
The STATUS_REG_x register bits identify the register that generates an error, as summarized in Table 28.
Table 28. Register Error Source Bit Name Register Source ERR_LOC_GEN2 GEN_ERR_REG_2 ERR_LOC_GEN1 GEN_ERR_REG_1 ERR_LOC_CH7 CH7_ERR_REG ERR_LOC_CH6 CH6_ERR_REG ERR_LOC_CH5 CH5_ERR_REG ERR_LOC_CH4 CH4_ERR_REG ERR_LOC_CH3 CH3_ERR_REG ERR_LOC_CH2 CH2_ERR_REG ERR_LOC_CH1 CH1_ERR_REG ERR_LOC_CH0 CH0_ERR_REG ERR_LOC_SAT_CH6_7 CH6_7_SAT_ERR ERR_LOC_SAT_CH4_5 CH4_5_SAT_ERR ERR_LOC_SAT_CH2_3 CH2_3_SAT_ERR ERR_LOC_SAT_CH0_1 CH0_1_SAT_ERR
In addition, the STATUS_REG_x registers have a bit that indicates if any internal error bit is set, CHIP_ERROR. This bit clears if the error is no longer present and the register is read back.
The INIT_COMPLETE bit in the STATUS_REG_3 indicates that the device is initialized correctly. This bit is not an error bit but an indicator.
General Errors
MCLK Switch Error (SPI Control Mode)
After power-up, the AD7771 initiates a clocking handover sequence to pass clocking control to the external oscillator, or
the CMOS clock. In SPI control mode, if an error occurs in the handover, the EXT_MCLK_SWITCH_ERR bit is set in the general error register, GEN_ERR_REG_2.
If EXT_MCLK_SWITCH_ERR is set, this means that the device is operating using the internal oscillator.
To use a slow external clock (<265 kHz), set the CLK_QUAL_ DIS bit. Setting this bit also clears the error bit.
If the external clock is between 132 kHz and 265 kHz, depending on the internal synchronization between the internal oscillator and the external clock, the error may not trigger. However, it is still recommended to set the CLK_QUAL_DIS bit.
If a slow clock is not in use and the error triggers, a reset is required.
Reset Detection
The AD7771 general error register contains a RESET_DETECTED bit. This bit is asserted if a reset pulse is applied to the AD7771 and is cleared by reading the general error register. This bit indicates that the power-on reset (POR) initialized correctly on the device. In addition, this bit can be used to detect an unexpected device reset or glitch on the RESET pin. To reset this error signal in SPI control mode, toggle the SYNC_IN pin or read from the general error register, GEN_ERR_REG_2. To reset this error signal in pin control mode, toggle the SYNC_IN pin.
Internal LDO Status
The AD7771 has three internal LDOs to regulate the internal analog and digital supply rails. The LDOs have internal power supply monitors. Internal comparators monitor and flag errors with these supplies after they pass a predetermined limit.
The ALDO1_PSM_ERR, ALDO2_PSM_ERR, and DLDO_PSM_ ERR bits indicate either an LDO malfunction, or, if the LDOs are bypassed, an incorrect external supply.
The internal analog and digital voltage monitors can be disabled by appropriately selecting the LDO_PSM_TEST_EN bits.
Use the SAR ADC to verify the error.
Additionally, the levels of the internal monitors can be manually triggered to check if the detector works correctly by appropriately setting the LDO_PSM_TRIP_TEST_EN bits. These bits increase the comparator window threshold above the LDO outputs, forcing the comparator to trigger.
ROM and Memory Map CRC
If an error is found at power-up during the ROM verification, or if the internal memory map is corrupted, the AD7771 generates an error and sets MEMMAP_CRC_ERR or ROM_ CRC_ERR, depending on the source of the error.
The checker can be disabled by clearing the MEMMAP_ CRC_TEST_EN and ROM_CRC_TEST_EN bits.
The device must be reset if any of these errors trigger.
AD7771 Data Sheet
Rev. 0 | Page 50 of 98
Σ-Δ ADC Errors
Reference Detect (SPI Control Mode)
In SPI control mode, the AD7771 includes on-chip circuitry to detect if there is a valid reference for conversions or calibrations. If the voltage between the selected REFx+ and REFx− pins goes below 0.7 V, the AD7771 detects that it no longer has a valid reference. CHx_ERR_REF_DET can be interrogated to identify the affected channel, which clears the bits if the error is no longer present. The voltage detector can be disabled by clearing the REF_DET_TEST_EN bit.
Use the Σ-Δ ADC diagnostic or the SAR ADC to verify the error.
Overvoltage and Undervoltage Events
The AD7771 includes on-chip overvoltage/undervoltage circuitry on each analog input pin. When the voltage on an analog input pin goes above AVDD1x + 0.04 mV, the CHx_ ERR_AINx_OV bit is set. The error disappears if the input voltage falls below AVDD1x − 40 mV.
If an undervoltage event occurs (AVSSx − 40 mV), the CHx_ ERR_AINx_UV bit is set. The error disappears if the input voltage increases to AVSSx + 0.04 V.
The CHx_ERR_AINM_UV, CHx_ERR_AINM_OV, CHx_ERR_ AINP_UV, and CHx_ERR_AINP_OV bits can be read back to verify the affected channel input, which clears the bits if the error is no longer present. The overvoltage and undervoltage detection can be disabled independently by clearing the AINM_ UV_TEST_EN, AINM_OV_TEST_EN, AINP_UV_TEST_EN, or AINP_OV_TEST_EN bit.
The input voltage can be checked independently with the SAR ADC.
Modulator Saturation
The AD7771 includes modulator saturation detection on each of the Σ-Δ ADCs. If 20 consecutive codes for the modulator are either all 1s or 0s, this condition is flagged as a modulator saturation event. Reading CHx_ERR_MOD_SAT clears the bit if the error corrects itself.
Modulator saturation detection can be disabled by clearing the MOD_SAT_TEST_EN bit.
Note that the modulator input voltage is attenuated internally, which means that a modulator output of all 1s or 0s represents a modulator that is out of bounds and that a RESET pulse is required.
Filter Saturation
TheAD7771 includes digital filter saturation detection on each Σ-Δ ADC channel. This detection indicates that the filter output is out of bounds, which represents an output code approximately 20% higher than positive or negative full scale. Reading the CHx_ERR_ FILTER_SAT bit clears the bit if the error corrects itself.
The detection can be disabled by clearing FILTER_SAT_TEST_ EN bit.
Output Saturation
An output saturation event can occur when gain and offset calibration causes the output from the digital filter to clip at either positive or negative full scale. The output does not wrap. Reading the CHx_ERR_OUTPUT_SAT bit clears the bit if the error corrects itself.
The detection can be disabled by clearing OUTPUT_SAT_ TEST_EN bit.
SPI Transmission Errors (SPI Control Mode)
All SPI errors clear after reading GEN_ERR_REG_1, which contains the SPI errors. These errors are not recovered automatically and, consequently, the ALERT pin and the ALERT bit remain set until the error register is read back.
CRC Checksum Error
If the CRC checksum is enabled by setting the SPI_CRC_ TEST_EN bit, an error bit, SPI_CRC_ERR, is raised if the CRC message does not match the message computed by the AD7771 internal CRC block. If the CRC message does not match the internally computed message, the register is not updated.
SCLK Counter
If the number of clocks generated by the controller is not a multiple of 8 after CS is pulled high, an error bit, SPI_CLK_ COUNT_ERR is raised. The last command multiple of 8 is executed; however, the SCLK counter can be disabled by setting the SPI_CLK_COUNT_TEST_EN bit.
Invalid Read
When attempting to read back an invalid register address, the SPI_INVALID_READ_ERR bit is set.
The invalid readback address detection can be disabled by setting the SPI_INVALID_READ_TEST_EN bit.
Invalid Write
When attempting to write to an invalid register address, the SPI_INVALID_WRITE_ERR bit is set.
The invalid write address detection can be disabled by setting the SPI_INVALID_WRITE_TEST_EN bit.
MONITORING USING THE AD7771 SAR ADC (SPI CONTROL MODE) The AD7771 contains an on-chip SAR ADC for chip diagnostics, system diagnostics, or measurement verification. The SAR ADC has a 12-bit resolution. The AVDD4 and AVSS4 pins operate in complete independence of the Σ-Δ ADC supplies and, therefore, can be used for chip diagnostics in systems where functional safety is important. The reference for the SAR conversion process is taken from the SAR ADC supply voltage (AVDD4/ AVSS4) and, therefore, the SAR analog input range is from AVSS4 to AVDD4.
Data Sheet AD7771
Rev. 0 | Page 51 of 98
The SAR ADC has a maximum throughput rate of 256 kSPS. The CONVST_SAR pin initiates a conversion on the SAR ADC. The maximum allowable frequency of the CONVST_SAR pin is 256 kHz. If consecutive conversions are performed in the SAR ADC, read back the result from the previous conversion before a new conversion is generated. Otherwise, the results are corrupted.
The SAR ADC is only available in SPI control mode. To read conversion results from the SAR ADC, set the SAR_DIAG_ MODE_EN bit. After this bit is set, all data shifted out from the SDO pin originates from the SAR ADC conversion, as shown in Figure 121.
The CONVST_SAR signal can be internally deglitched to avoid false triggers.
Table 29. SAR Synchronization and Deglitching CONVST_DEGLITCH_DIS (Register 0x013, Bits[7:6]) Effect on CONVST_SAR 11 CONVST_SAR goes directly to the SAR 10 CONVST_SAR reaches the SAR when
it is 1.5/MCLK cycles wide
Increase the acquisition time by 1.5/MCLK when the deglitch circuitry is enabled.
Prior to the SAR ADC, the AD7771 contains an internal multiplexer. This multiplexer can be configured over the SPI to set the inputs to the SAR ADC to be either internal circuit nodes (in the case of diagnostics) or to select the external AUXAIN+ and AUXAIN− pins.
Along with converting external voltages, the SAR ADC monitors the internal nodes on the AVDD, IOVDD, and DGND pins, and the DLDO and analog LDO (ALDO) outputs. Some voltages are internally attenuated by 6, and the resulting voltage is applied to the SAR ADC, as shown in Table 30. This is useful because variations in the power supply voltage can be monitored.
The input multiplexer of the SAR is controlled by the GLOBAL_ MUX_CONFIG register, and the different inputs available are described in Table 30.
The SAR ADC also contains an SAR driver amplifier, as shown in Figure 122. This amplifier settles the SAR input to 12-bit accuracy within the t33 time. This driver amplifier helps minimize the kickback from the SAR converter to the global diagnostic mux input circuit nodes.
Use the auxiliary inputs, AUXAIN+ and AUXAIN−, to validate the Σ-Δ measurements. While operating in SPI control mode, the AD7771 has three available GPIOx ports controlled via the SPI. The GPIOx pins can be used to control an external, dual 8:1 multiplexer, which, in turn, samples the eight Σ-Δ channels. Use this diagnostic in applications where functional safety is required. This diagnostic aids in removing the need for a secondary external ADC to validate primary measurements on the Σ-Δ channels.
Temperature Sensor
The internal die temperature can be measured with an accuracy of ±2°C. The differential voltage base emitter (DVBE) is proportional to the temperature measured referred to 25°C.
Temperature (°C) = mV2
V6.0−BEDV
Table 30. SAR Mux Inputs SAR Input
Positive Signal
Negative Signal Attenuation ÷ 6
0 AUXAIN+ AUXAIN− No 1 DVBE AVSSx No 2 REF1+ REF1− No 3 REF2+ REF2− No 4 REF_OUT AVSSx No 5 VCM AVSSx No 6 AREG1CAP AVSSx Yes 7 AREG2CAP AVSSx Yes 8 DREGCAP DGND Yes 9 AVDD1A AVSSx Yes 10 AVDD1B AVSSx Yes 11 AVDD2A AVSSx Yes 12 AVDD2B AVSSx Yes 13 IOVDD DGND Yes 14 AVDD4 AVSSx No 15 DGND AVSSx Yes 16 DGND AVSSx Yes 17 DGND AVSSx Yes 18 AVDD4 AVSSx Yes 19 REF1+ AVSSx No 20 REF2+ AVSSx No 21 AVSSx AVDD4 Yes
CS
SDI
SDO
SET BIT 5GENERAL_USER_CONFIG_2 REG WRITE TO ADC MUX REGISTER WRITE TO ADC MUX REGISTER
ADC CONVERSION RESULT REG ADC CONVERSION RESULT REG
1380
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1
Figure 121. Configuring the AD7771 to Operate the SPI to Read from the SAR ADC
AD7771 Data Sheet
Rev. 0 | Page 52 of 98
SAR DRIVER
CONTROL LOGIC
FIFO
ON-CHIPDIAGNOSTICS
SPI
AUXAIN+
AUXAIN–
AVDD4
AVSS4
CONVST_SAR
MUX
DEGLITCH
SAR ADC
REF
1380
2-12
2
Figure 122. SAR ADC Configuration and Control
Table 31. Σ-Δ Diagnostic Input Voltage Recommended Voltage Reference Notes/Result 0 Floating Not applicable Not applicable 1 Floating Not applicable Not applicable 2 280 mV differential signal Internal/external PGA gain verification 3 External reference, positive/negative External Positive full scale 4 External reference, negative/positive External Negative full scale 5 External reference, negative/negative External Zero scale 6 Internal reference, positive/negative Internal Positive full scale 7 Internal reference, negative/positive Internal Negative full scale 8 Internal reference, positive/positive Internal Zero scale 9 External reference, positive/positive External Zero scale
Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) The AD7771 Σ-Δ ADC diagnostic functions are accessible through the SPI. The internal mux placed before the PGA has different inputs, allowing the user to select a zero-scale, positive full-scale, or negative full-scale input to the Σ-Δ ADC, which can be converted to verify the correct operation of the Σ-Δ ADC channel.
The diagnostic mux control signals are shared across all the Σ-Δ channels. Depending on the diagnostic selected, connect the Σ-Δ ADC reference to a different reference source to guarantee that the conversion is within the measurable range.
There are two different ways to enable the diagnostic mux, as follows:
• Setting the CHx_RX bit. This bit enables the input Σ-Δ mux. The multiplexer inputs are described in Table 31. The reference used during the conversions are controlled by the REF_MUX_CTRL bits.
• Setting CHx_REF_MONITOR. This bit has the same effect as enabling the CHx_RX bit and selects the VDD1x/ AVSSx supplies as the main reference.
If the AINx± pin is connected to AVSSx, the input range is outside the range of AVSSx + 100 mV; therefore, results may differ slightly from the expected value.
Alternatively, the inputs can be used to calibrate gain and offset errors.
Data Sheet AD7771
Rev. 0 | Page 53 of 98
Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA The AD7771 Σ-Δ conversion results are output on the DOUT0 to DOUT3 pins or over the SPI, depending on the selected interface. If the DOUTx interface is selected, the AD7771 acts as the master in the transmission. If the SPI is selected, the controller is the master.
The DRDY signal indicates the end of conversion independent of the interface selected to read back the Σ-Δ conversion. When the SPI reads back the Σ-Δ conversion, if a new conversion is completed (DRDY falling edge) before the previous conversion is read back, the results from previous conversion are overwritten and, consequently, the previous conversion data is corrupted.
For each channel, the width is 32 bits long: 8 bits for the header and 24 bits for the Σ-Δ conversion, as shown in Figure 123.
ADC DATA NN – 1
24-BITS8-BITS
DOUTx
DRDY
HEADER N
1380
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3
Figure 123. ADC Output—8-Bit Header Plus 24-Bit Conversion Data
In pin control mode, the header is fixed to the CRC while in SPI mode, and can be selected between the CRC and error headers.
CRC Header
The CRC header is the header generated in pin control mode or in SPI control mode if DOUT_HEADER_FORMAT is set.
As shown in Figure 124, the header consists of an alert bit, three bits for the ADC channel ID, as shown in Table 32, and four bits for the CRC.
The alert bit is set high if an error is detected in any channel, as explained in the General Errors section. The alert bit remains set to 1 until the error disappears.
ALERT CHANNELNUMBER
CHANNELNUMBER
CHANNELNUMBER CRC CRC CRC CRC
1380
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4
Figure 124. CRC Header
Table 32. Channel ID Channel CH_ID_2 CH_ID_1 CH_ID_0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1
The CRC generated is eight bits long; the 4 MSBs are placed on the header for the first channel in the pairing and the 4 LSBs on the header of the second channel in the pairing, as shown in Table 33. If a channel is disabled, the 24-bit output data for this channel is 0x000000.
Table 33. 8-Bit CRC, Header Configuration (Channel 2) CE 0 1 0 CRC7 CRC6 CRC5 CRC4
Table 34. 8-Bit CRC, Header Configuration (Channel 3) CE 0 1 1 CRC3 CRC2 CRC1 CRC0
Error Header (SPI Control Mode)
In SPI control mode, the default header can be replaced by an error header. If the Σ-Δ conversion is read back through the SPI, disable the CRC by clearing the SPI_CRC_TEST_EN bit. If the DOUTx interface is used, clear the DOUT_HEADER_ FORMAT bit.
The error header provides information of common error sources specific for each channel, as shown in Table 35. Modulator and filter errors are indicated even if the checker for these errors are specifically disabled, as described in the Σ-Δ ADC Errors section.
Table 35. Status Header Output Bits Name Description 7 Alert This bit is set high if any of the enabled diagnostic functions have detected an error, including an
external clock not detected, a memory map bit flip, or an internal CRC error. This bit is not channel specific. This bit clears if the error is no longer present.
6:4 CH_ID_[2:0] These bits indicate which ADC channel the following conversion data came from (see Table 32). 3 RESET_DETECTED This bit indicates if a reset condition occurs. This bit is not channel specific. 2 MODULATOR_SATURATE This bit indicates that the modulator output is 20 consecutive 0s or 1s. The bit resets automatically
after the error is no longer present. 1 FILTER_SATURATE This bit indicates that the filter output is out of bounds. The bit resets automatically after the error is
no longer present. 0 AIN_OV_UVERROR This bit indicates that there is an AINx± overvoltage/undervoltage condition on the inputs. This bit is
set until the appropriate register is read back and the error is no longer present.
AD7771 Data Sheet
Rev. 0 | Page 54 of 98
SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) The AD7771 implements a patented featured called the SRC on each Σ-Δ channel that allows the user to configure the output data rate or sampling frequency to any desired value, including noninteger values. The SRC achieves fine resolution control over the Σ-Δ ADC ODR, up to 15.2 µSPS. In applications where the ODR must change based on changes in the input signal to maintain sampling coherency, the SRC provides fine control over the ODR. For example, to achieve the highest classification standard, Class A, in power quality applications, coherency must be maintained for 0.01 Hz changes in the input power line. Use the SRC to achieve this sampling frequency accuracy.
In pin control mode, the ODR is fixed per the predefined pin control options. Consequently, a noninteger number cannot be selected, as shown in Table 13.
To set the ODR, the user must program up to four registers, depending on the decimation value: two registers to program the integer value, N (the effective decimation rate), and two registers to program the decimal value, the interpolation factor (IF).
The integer value registers are SRC_N_MSB, Bits[3:0] and SRC_N_LSB, Bits[7:0]. The decimal part value registers are SRC_IF_MSB, Bits[7:0] and SRC_IF_LSB, Bits[7:0].
As an example, if an output data rate of 2.8 kHz is required, the decimation rate equates to
• High resolution mode = 2048/2.8 = 731.428 • Low power mode = 512/2.8 = 182.857
The register values for high resolution mode are as follows:
• 731 (decimal) = 0x2DB • SRC_N_MSB, Bits[3:0] = 0x02 • SRC_N_LSB, Bits[7:0] = 0xDB • 0.428 (decimal) = 0.428 × 216 = 28049 (decimal) = 0x6D91 • SRC_IF_MSB, Bits[7:0] = 0x6D • SRC_IF_LSB, Bits[7:0] = 0x91
The SRC resolution depends on the decimal number used in the decimation, as well as the modulator clock (MOD_MCLK), as follows:
16216
21232 ×+×+×
=DECDEC
MODResolution MCLK
where: MODMCLK is the modulator frequency. DEC is the decimal portion of the decimation rate.
In high resolution mode, for a decimal decimation of 450, the resolution is defined as
SPS102.15
2145034502
2048 6–
162216
×=××+×
The ODR can be updated on the fly, but a new ODR is effective in three conversion cycles of the Σ-Δ ADCs. This condition guarantees a smooth transition with no conversion results out of range.
There are two different ways to change the ODR after a new value is written in the SRC registers: via software or via hardware, depending on the SRC_LOAD_SOURCE bit (SRC_UPDATE register, Bit 7).
If the SRC_LOAD_SOURCE bit is clear, the new ODR value is updated by setting the SRC_LOAD_UPDATE bit to 1. This bit must be held high for at least two MLCK periods; return the bit to 0 before attempting another update.
If SRC_LOAD_SOURCE is set, the GPIO0 pin controls the ODR update externally. Apply a pulse in the GPIO2 pin, which is then internally synchronized with the external MCLK clock, and the resultant synchronous signal is output on the GPIO1 pin.
The GPIO1 and GPIO0 pins must be externally connected.
If multiple AD7771 devices must be synchronized, the GPIO1 pin of one device can be connected to multiple devices. This synchro-nization method requires the use of a common MCLK signal for all the AD7771 devices connected, as shown in Figure 125.
GPIO2
GPIO0
GPIO0
GPIO0
MCLK GPIO1
GPIO2MCLK GPIO1
NC
GPIO2MCLK GPIO1
NC
AD7771
AD7771
AD7771
SYNCHRONIZATIONLOGIC
PULSE
DIGITAL FILTER
SYNCHRONIZATIONLOGIC
DIGITAL FILTER
SYNCHRONIZATIONLOGIC
DIGITAL FILTER
MCLK
1380
2-12
5
Figure 125. Hardware ODR Update
Data Sheet AD7771
Rev. 0 | Page 55 of 98
SRC Bandwidth
The sinc3 and sinc5 filters architecture allows the user to select a noninteger value as the decimation range This versatility means that the filter notches must be adjusted dynamically: two notches (sinc3) or four notches (sinc5) at the variable frequency, and one fixed notch to remove the PGA chopping tone. Consequently, the traditional formula for the −0.1 dB and −3 dB bandwidth must be adjusted depending on the selected decimation rate.
The bandwidth transfer function is not linear but can be approximated by using a linear function.
Figure 126 to Figure 129 show the correction factor for the −0.1 dB and −3 dB bandwidth, respectively. In low power mode, the offset must be divided by 4. For example, for sinc5 when the ODR = 1000 SPS, the −0.1 dB point is
BW = 0.0377 × 1000 + 4355.49
= 50.03 Hz
7
0
1
2
3
4
5
6
0 10050
–0.1
dB F
REQ
UEN
CY
(kH
z)
ODR (kHz) 1380
2-12
6
y = 0.049x + 120.41
Figure 126. −0.1 dB Correction Factor, Sinc3 Filter Enabled
6
0
1
2
3
4
5
0 10050
–0.1
dB F
REQ
UEN
CY
(kH
z)
ODR (kHz) 1380
2-12
7
y = 0.0377x + 49.355
Figure 127. −0.1 dB Correction Factor, Sinc5 Filter Enabled
40
0
5
10
15
20
25
30
35
0 10050
–3dB
FR
EQU
ENC
Y (k
Hz)
ODR (kHz) 1380
2-12
8
y = 0.2653x + 634.03
Figure 128. −3 dB Correction Factor, Sinc3 Filter Enabled
30
0
5
10
15
20
25
0 10050
–3dB
FR
EQU
ENC
Y (k
Hz)
ODR (kHz) 1380
2-12
9
y = 0.2053x + 263.94
Figure 129. −3 dB Correction Factor, Sinc5 Filter Enabled
SRC Group Delay
The SRC group delay depends on the selected ODR and is defined by the following equation:
SRC Group Delay = ODRNSRC
NSRCPM×
+_
_
where: PM is a constant equal to 8. SRC_N is the integer value of the programmed ODR. ODR is the programmed output data rate.
When using the sinc5 filter, the equation that defines the group delay is
SRC Group Delay = ODRNSRC
NSRCPM×
×+_
_2
The latency is the contribution of the group delay and the calibration time.
Latency = Group Delay + tCAL
In high resolution mode, the calibration delay is defined as 62 × tMCLK, with a maximum error of 2 × tMCLK. In low power mode, the calibration delay is defined as 121 × tMCLK, with a maximum error of 4 × tMCLK. tMCLK is the modulator period and is 488 ns in high resolution mode and 1.9 µs in low power mode.
AD7771 Data Sheet
Rev. 0 | Page 56 of 98
Settling Time
The settling time is defined by the contribution of all the internal stages, the filter delay, and the block calibration.
When using the sinc3 filter option, the filter delay is defined as 3/ODR. In some extreme cases, such as when an external pulse is applied, this value may increase to 4/ODR. If using the sinc5 filter, the filter delay is defined as 5/ODR, or 6/ODR for extreme cases.
DATA OUTPUT INTERFACE The Σ-Δ output data interface is defined by the CONVST_SAR, FORMAT0, and FORMAT1 pins in pin control mode at power-up. The FORMATx pins cannot be changed dynamically. Table 14 shows the available options for pin control mode. If the device
is configured in SPI control mode, the SPI_SLAVE_MODE_ EN bit enables the SPI to transmit the Σ-Δ ADC conversion results, as shown in Table 22.
DOUT3 to DOUT0 Data Interface
Standalone Mode
In standalone mode, the AD7771 interface acts as a master. There are three different DOUT configurations, configurable through the FORMATx pins in pin control mode, as shown in Figure 130 through Figure 132, or via the DOUT_FORMAT bits, Bits[7:6], in SPI control mode, as described in Table 36.
Figure 133, Figure 134, and Figure 135 show the expected data outputs for different DOUTx output modes.
Table 36. DOUTx Channels DOUT_FORMAT Bits/ FORMATx Pins
Number of DOUTx Lines Enabled Associated Channels
00 4 DOUT0—Channel 0 and Channel 1 DOUT1—Channel 2 and Channel 3 DOUT2—Channel 4 and Channel 5 DOUT3—Channel 6 and Channel 7 01 2 DOUT0—Channel 0, Channel 1, Channel 2, and Channel 3 DOUT1—Channel 4, Channel 5, Channel 6, and Channel 7 10 or 11 1 DOUT0—Channel 0, Channel 1, Channel 2, Channel 3, Channel 4, Channel 5,
Channel 6, and Channel 7
DOUT0
DOUT1
DOUT2
DOUT3
DCLK
DRDY
FORMAT1
DAISY-CHAINING IS NOT POSSIBLE IN THIS FORMAT
FORMAT0
AD7771
CH 0 CH 1
CH 0 CH 1
CH 0 CH 1
CH 0 CH 1
1380
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0
DGND
DOUT0: CH 0, CH 1DOUT1: CH 2, CH 3DOUT2: CH 4, CH 5DOUT3: CH 6, CH 7
00
00
Figure 130. FORMATx Pin Configuration—FORMAT0 = 0, FORMAT1 = 0
DOUT0
DOUT1
DCLK
DRDY
FORMAT1
IOVDD
DAISY-CHAINING IS POSSIBLE IN THIS FORMAT
DGND
FORMAT0CH 0, CH 1, CH 2, CH 3
OUTPUT ON DOUT0
CH 4, CH 5, CH 6, CH 7OUTPUT ON DOUT1
01
10
AD7771
CH 4 CH 5 CH 6 CH 7
CH 0 CH 1 CH 2 CH 3
1380
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1
Figure 131. FORMATx Pin Configuration—FORMAT0 = 1, FORMAT1 = 0
DOUT0
DCLK
DRDY
FORMAT1
IOVDD
DAISY-CHAINING IS POSSIBLE IN THIS FORMAT
DGND
FORMAT0CH 0 TO CH 7OUTPUT ON DOUT0
1001
AD7771
CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7
1380
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2
Figure 132. FORMATx Pin Configuration—FORMAT0 = 0, FORMAT1 = 1
Data Sheet AD7771
Rev. 0 | Page 57 of 98
CH0-S0 CH1-S0
CH2-S0 CH3-S0
CH0-S1 CH1-S1
CH2-S1 CH3-S1
DCLK
DRDY
DOUT0
SAMPLE N SAMPLE N + 1
DOUT1
CH4-S0 CH5-S0
CH6-S0 CH7-S0
CH4-S1 CH5-S1
CH6-S1 CH7-S1
DOUT0
DOUT1
1380
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3
Figure 133. FORMAT0 = 0, FORMAT1 = 0—Each DOUTx Outputs Two ADC Conversions (S0 Means Sample 0 and S1 Means Sample 1)
CH0-S0 CH1-S0 CH2-S0 CH3-S0
CH7-S0CH4-S0 CH5-S0 CH6-S0
CH0-S1 CH1-S1 CH2-S1 CH3-S1
CH7-S1CH4-S1 CH5-S1 CH6-S1
DCLK
DRDY
DOUT0
SAMPLE N SAMPLE N + 1
DOUT1
DOUT3
DOUT2
1380
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4
Figure 134. FORMAT0 = 0, FORMAT1 = 1—Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1 (S0 Means Sample 0 and S1 Means Sample 1)
DCLK
DRDY
DOUT0
SAMPLE N SAMPLE N + 1 SAMPLE N + 2
DOUT3
DOUT2
DOUT1
CH0-S0 CH1-S0 CH2-S0 CH...-S0 CH6-S0 CH7-S0 CH0-S1 CH0-S2 CH0-S3CH1-S1 CH2-S1 CH...-S1 CH6-S1 CH7-S2 CH1-S2 CH2-S2 CH...-S2 CH6-S2 CH7-S2
1380
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5
Figure 135. FORMAT0 = 1, FORMAT1 = 0—Channel 0 to Channel 7 Output on DOUT0 Only (S0 Means Sample 0 and S1 Means Sample 1)
AD7771 Data Sheet
Rev. 0 | Page 58 of 98
Daisy-Chain Mode
Daisy-chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple ADCs from separate AD7771 devices. In daisy-chain configura-tion, only one device has a direct connection between the DOUTx interface and the digital host. For the AD7771, daisy-chain capability is implemented by cascading DOUT0 and DOUT1 through a number of devices, or by just using DOUT0 (the number of DOUTx pins available depends on the selected DOUTx mode). The ability to daisy-chain devices and the limit on the number of devices that can be handled by the chain is dependent on the selected DOUTx mode and the decimation rate employed.
When operating in daisy-chain mode, it is required that all AD7771 devices in the chain are correctly synchronized. See
the Digital Reset and Synchronization Pins section for more information.
This feature is especially useful for reducing the component count and wiring connections in, for example, isolated multiconverter applications or for systems with a limited interfacing capacity.
For daisy-chain operation, there are two different configurations possible, as described in Table 37.
Using the FORMATx = 10 mode, DOUT2 acts as an input pin, as shown in Figure 136. In this case, the DOUT0 pin of the AD7771 devices is cascaded to the DOUT2 pin of the next device in the chain. Data readback is analogous to clocking a shift register where data is clocked on the rising edge of DCLK.
Table 37. DOUTx Modes in Daisy-Chain Operation DOUT_FORMAT Bits/ FORMATx Pins Number of DOUTx Lines Enabled Associated Channels 01 2 DOUT0—Channel 0 to Channel 3 and DOUT2 DOUT1—Channel 4 to Channel 7 and DOUT3 DOUT2—input channel DOUT3—input channel 10 1 DOUT0—Channel 0 to Channel 7 and DOUT2 DOUT2—input channel
U2 S0 CH0 TO CH7
U2 S0 CH0 TO CH7
U1 S0 CH0 TO CH7
0
0
U2 S0 CH0 TO CH7
U1 S0 CH0 TO CH7
0
U2 S1 CH0 TO CH7
U2 S1 CH0 TO CH7
U1 S1 CH0 TO CH7
0
0
U2 S1 CH0 TO CH7
U2 S3 CH0 TO CH7
0
U2 S0 CH0 TO CH7
U2 S0 CH0 TO CH7
U1 S1 CH0 TO CH7
0
U2 DOUT0
U1 DOUT2/DIN0
U1 DOUT0
U2 DOUT2/DIN0
DRDY
DCLK
U2
DOUT2/DIN0 DOUT0
U2
DOUT2/DIN0 DOUT0
1380
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6
Figure 136. Daisy-Chain Connection Mode, FORMAT0 = 1, FORMAT1 = 0 (S0 Means Sample 0 and S1 Means Sample 1); When Connected in Daisy-Chain Mode,
DOUT2 Acts as an Input Pin, Represented by DIN0
Data Sheet AD7771
Rev. 0 | Page 59 of 98
Minimum DCLKx Frequency
Select the DCLKx frequency ratio in such a way that the data is completely shifted out before a new conversion is completed; otherwise, the previous conversion is overwritten and the trans-mission becomes corrupt. The minimum DCLKx frequency ratio is defined by the decimation rate, the operation mode, and the lines enabled on the DOUT3 to DOUT0 data interface as described in the following equations:
In standalone, high resolution mode,
DCLKMIN_RATIO < Decimation/(8 × DOUT_FORMAT)
In standalone, low power mode,
DCLKMIN_RATIO < Decimation/(4 × DOUT_FORMAT)
In daisy-chain, high resolution mode,
DCLKMIN_RATIO < Decimation/(8 × Devices × DOUTx Channels)
In daisy-chain, low power mode,
DCLKMIN_RATIO < Decimation/(4 × Devices × DOUTx Channels)
As an example, when operating in master interface mode, FORMATx = 01, the DOUT0 and DOUT1 pins shift out four Σ-Δ channels each and, assuming a maximum output rate in high resolution mode, the decimation = 128.
DCLKMIN < 128/(8 × 4) = 4
If the DCLKMIN_RATIO is selected above the necessary minimum, a Logic 0 is continuously transmitted until a new sample is available.
An example in daisy-chain mode, assuming FORMATx = 01, and with three devices connected and a decimation rate of 256 in high resolution mode, is as follows:
DCLKMIN_RATIO < 256/(8 × 3 × 4) = 2.66 = 2
The different ratios are summarized in Table 38.
Table 38. Available DCLK Ratios DCLK_CLK_DIV (SPI Control Mode), DCLKx (Pin Control Mode) DCLKx Ratio 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128
There are maximum achievable ODRs and minimum DCLKx frequencies required for a given DOUTx pin configuration, as shown in Table 39 and Table 40.
Table 39. Maximum ODRs and Minimum DCLKx Frequencies in High Resolution Mode
Decimation Rate
ODR (kSPS)
Minimum DCLKx (kHz)1 1 × DOUTx 2 × DOUTx 4 × DOUTx
4095 0.500122 128 64 32 2048 1 256 128 64 1024 2 512 256 128 512 4 1024 512 256 256 8 2048 1024 512 128 16 4096 2048 1024 64 32 8192 4096 2048 32 64 N/A 8192 4096 16 128 N/A N/A 8192 1 N/A means not applicable.
Table 40. Maximum ODRs and Minimum DCLK Frequencies in Low Power Mode
Decimation Rate
ODR (kSPS)
Minimum DCLKx (kHz) 1 × DOUTx 2 × DOUTx 4 × DOUTx
2048 0.25 64 32 16 1024 0.5 128 64 32 512 1 256 128 64 256 2 512 256 128 128 4 1024 512 256 64 8 2048 1024 512 32 16 4096 2048 1024 16 32 N/A1 4096 2048 1 N/A means not applicable.
If the AD7771 operates in SPI control mode, it is possible to adjust the DOUTx strength, which can be selected in the DOUT_DRIVE_STR bits, as described in Table 41.
Table 41. DOUTx Strength DOUT_DRIVE_STR Mode 00 Nominal 01 Strong 10 Weak 11 Extra strong
SPI
The SPI gives the user flexibility to read the conversion from the Σ-Δ ADC where the processor or microcontroller is the master.
When a new conversion is completed, the DRDY signal is toggled to indicate that data can be accessed. When DRDY toggles, the internal channel counter is reset and the next SPI read originates from Channel 0 again. Conversely, after the last channel data is read, all successive reads before the next DRDY signal originate from Channel 7 (LSB).
AD7771 Data Sheet
Rev. 0 | Page 60 of 98
CH0_HEADER _+_CH0_8_BITS_MSB CH0_16_BITS_LSB
1380
2-13
7CS
SDO Figure 137. SPI Readback, 16 Bits per Frame
CS
SDO CH0_HEADER _+_CH0_16_BITS_MSB CH0_8_BITS_LSB_+_CH1_HEADER_+CH1_8_BITS_MSB
1380
2-13
8
Figure 138. SPI Readback, 24 Bits per Frame
The SPI operates in multiples of 8 bits per frame; Figure 137 shows a readback example in 16 bits per frames, and Figure 138 shows a readback in 24 bits per frame.
Note that if the device is configured in SPI control mode, the AD7771 generates a software reset if the SDI pin is sampled high for 64 consecutive clocks. To avoid a reset or unwanted register writes, it is recommended to transfer a 0x8000 command, which generates a readback command that is ignored by the device, as explained in the SPI Software Reset section.
CALCULATING THE CRC CHECKSUM The AD7771 implements two different CRC checksum generators, one for the Σ-Δ results and another for the SPI control mode.
The AD7771 uses a CRC polynomial to calculate the CRC checksum value. The 8-bit CRC polynomial used is x8 + x2 + x + 1.
The polynomial is aligned so that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum.
An example of CRC calculation for 12-bit data is shown in Table 42.
Table 42. Example CRC Calculation for 12-Bit Data1 Data 0 1 1 0 0 1 0 0 1 1 1 0 Polynomial 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 CRC 0 1 0 1 1 1 1 0 1 This table represents the division of the data; blank cells are for formatting
purposes.
Σ-Δ CRC Checksum
The CRC message is calculated internally by the AD7771 on ADC pairs. The CRC is calculated using the ADC output data from two ADCs and Bits[7:4] from the header. Therefore, 56 bits are used to calculate the 8-bit CRC. This CRC is split between the two channel headers. The CRC data covers channel pairings as follows: Channel 0 and Channel 1, Channel 2 and Channel 3, Channel 4 and Channel 5, and Channel 6 and Channel 7.
To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 1s.
The CRC is calculated from 56 bits across two consecutive/ channel pairings (Channel 0 and Channel 1, Channel 2 and Channel 3, Channel 4 and Channel 5, Channel 6, and Channel 7). The 56 bits consist of the alert bit, the 3 bits for the first ADC pairing channel, and the 24 bits of data of each pairing channel. For example, for the second channel pairing, Channel 2 and Channel 3,
56 bits = alert bit + 3 ADC channel bits (010) + 24 data bits (Channel 2) + alert bit + 3 ADC channel bits (011) + 24 data bits (Channel 3)
SPI Control Mode Checksum
The CRC message is calculated internally by the AD7771. The data transferred to the AD7771 uses the R/W bit, a 7-bit address, and 8 bits of data for the CRC calculation.
The CRC calculated and appended to the data that is shifted out uses a 0010 0000 header and 8 bits of data for the register readback, as well as the 0010 header and 12 bits of SAR conversion data for the SAR readback transfers.
Data Sheet AD7771
Rev. 0 | Page 61 of 98
REGISTER SUMMARY Table 43. Register Summary
Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x000 CH0_CONFIG [7:0] CH0_GAIN CH0_REF_ MONITOR
CH0_RX RESERVED 0x00 /W R
0x001 CH1_CONFIG [7:0] CH1_GAIN CH1_REF_ MONITOR
CH1_RX RESERVED 0x00 R/W
0x002 CH2_CONFIG [7:0] CH2_GAIN CH2_REF_ MONITOR
CH2_RX RESERVED 0x00 R/W
0x003 CH3_CONFIG [7:0] CH3_GAIN CH3_REF_ MONITOR
CH3_RX RESERVED 0x00 R/W
0x004 CH4_CONFIG [7:0] CH4_GAIN CH4_REF_ MONITOR
CH4_RX RESERVED 0x00 R/W
0x005 CH5_CONFIG [7:0] CH5_GAIN CH5_REF_ MONITOR
CH5_RX RESERVED 0x00 R/W
0x006 CH6_CONFIG [7:0] CH6_GAIN CH6_REF_ MONITOR
CH6_RX RESERVED 0x00 R/W
0x007 CH7_CONFIG [7:0] CH7_GAIN CH7_REF_ MONITOR
CH7_RX RESERVED 0x00 R/W
0x008 CH_DISABLE [7:0] CH7_ DISABLE
CH6_ DISABLE
CH5_DISABLE CH4_ DISABLE
CH3_ DISABLE
CH2_ DISABLE
CH1_ DISABLE
CH0_ DISABLE
0x00 R/W
0x009 CH0_SYNC_ OFFSET
[7:0] CH0_SYNC_OFFSET 0x00 R/W
0x00A CH1_SYNC_ OFFSET
[7:0] CH1_SYNC_OFFSET 0x00 R/W
0x00B CH2_SYNC_ OFFSET
[7:0] CH2_SYNC_OFFSET 0x00 R/W
0x00C CH3_SYNC_ OFFSET
[7:0] CH3_SYNC_OFFSET 0x00 R/W
0x00D CH4_SYNC_ OFFSET
[7:0] CH4_SYNC_OFFSET 0x00 R/W
0x00E CH5_SYNC_ OFFSET
[7:0] CH5_SYNC_OFFSET 0x00 R/W
0x00F CH6_SYNC_ OFFSET
[7:0] CH6_SYNC_OFFSET 0x00 R/W
0x010 CH7_SYNC_ OFFSET
[7:0] CH7_SYNC_OFFSET 0x00 R/W
0x011 GENERAL_ USER_ CONFIG_1
[7:0] ALL_ CH_DIS_MCLK_EN
POWER-MODE
PDB_VCM PDB_ REFOUT_BUF
PDB_ SAR
PDB_ RC_OSC
SOFT_RESET 0x24 R/W
0x012 GENERAL_ USER_ CONFIG_2
[7:0] RESERVED FILTER_ MODE
SAR_DIAG_ MODE_EN
SDO_DRIVE_STR DOUT_DRIVE_STR SPI_SYNC 0x09 R/W
0x013 GENERAL_ USER_ CONFIG_3
[7:0] CONVST_ DEGLITCH_DIS
RESERVED SPI_SLAVE_ MODE_EN
RESERVED CLK_ QUAL_DIS
0x80 R/W
0x014 DOUT_FORMAT [7:0] DOUT_FORMAT DOUT_ HEADER_ FORMAT
RESERVED DCLK_CLK_DIV RESERVED 0x20 R/W
0x015 ADC_MUX_ CONFIG
[7:0] REF_MUX_CTRL MTR_MUX_CTRL RESERVED 0x00 R/W
0x016 GLOBAL_MUX_ CONFIG
[7:0] GLOBAL_MUX_CTRL RESERVED 0x00 R/W
0x017 GPIO_CONFIG [7:0] RESERVED GPIO_OP_EN 0x00 R/W
0x018 GPIO_DATA [7:0] RESERVED GPIO_READ_DATA GPIO_WRITE_DATA 0x00 R/W
0x019 BUFFER_ CONFIG_1
[7:0] RESERVED REF_BUF_ POS_EN
REF_ BUF_ NEG_EN
RESERVED 0x38 R/W
0x01A BUFFER_ CONFIG_2
[7:0] REF-BUFP_ PREQ
REF-BUFN_ PREQ
RESERVED PDB_ ALDO1_OVRDRV
PDB_ ALDO2_ OVRDRV
PDB_ DLDO_ OVRDRV
0xC0 R/W
0x01C CH0_OFFSET_ UPPER_BYTE
[7:0] CH0_OFFSET_ALL[23:16] 0x00 R/W
0x01D CH0_OFFSET_ MID_BYTE
[7:0] CH0_OFFSET_ALL[15:8] 0x00 R/W
AD7771 Data Sheet
Rev. 0 | Page 62 of 98
Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x01E CH0_OFFSET_ LOWER_BYTE
[7:0] CH0_OFFSET_ALL[7:0] 0x00 R/W
0x01F CH0_GAIN_ UPPER_BYTE
[7:0] CH0_GAIN_ALL[23:16] 0x00 R/W
0x020 CH0_GAIN_ MID_BYTE
[7:0] CH0_GAIN_ALL[15:8] 0x00 R/W
0x021 CH0_GAIN_ LOWER_BYTE
[7:0] CH0_GAIN_ALL[7:0] 0x00 R/W
0x022 CH1_OFFSET_ UPPER_BYTE
[7:0] CH1_OFFSET_ALL[23:16] 0x00 R/W
0x023 CH1_OFFSET_ MID_BYTE
[7:0] CH1_OFFSET_ALL[15:8] 0x00 R/W
0x024 CH1_OFFSET_ LOWER_BYTE
[7:0] CH1_OFFSET_ALL[7:0] 0x00 R/W
0x025 CH1_GAIN_ UPPER_BYTE
[7:0] CH1_GAIN_ALL[23:16] 0x00 R/W
0x026 CH1_GAIN_ MID_BYTE
[7:0] CH1_GAIN_ALL[15:8] 0x00 R/W
0x027 CH1_GAIN_ LOWER_BYTE
[7:0] CH1_GAIN_ALL[7:0] 0x00 R/W
0x028 CH2_OFFSET_ UPPER_BYTE
[7:0] CH2_OFFSET_ALL[23:16] 0x00 R/W
0x029 CH2_OFFSET_ MID_BYTE
[7:0] CH2_OFFSET_ALL[15:8] 0x00 R/W
0x02A CH2_OFFSET_ LOWER_BYTE
[7:0] CH2_OFFSET_ALL[7:0] 0x00 R/W
0x02B CH2_GAIN_ UPPER_BYTE
[7:0] CH2_GAIN_ALL[23:16] 0x00 R/W
0x02C CH2_GAIN_ MID_BYTE
[7:0] CH2_GAIN_ALL[15:8] 0x00 R/W
0x02D CH2_GAIN_ LOWER_BYTE
[7:0] CH2_GAIN_ALL[7:0] 0x00 R/W
0x02E CH3_OFFSET_ UPPER_BYTE
[7:0] CH3_OFFSET_ALL[23:16] 0x00 R/W
0x02F CH3_OFFSET_ MID_BYTE
[7:0] CH3_OFFSET_ALL[15:8] 0x00 R/W
0x030 CH3_OFFSET_ LOWER_BYTE
[7:0] CH3_OFFSET_ALL[7:0] 0x00 R/W
0x031 CH3_GAIN_ UPPER_BYTE
[7:0] CH3_GAIN_ALL[23:16] 0x00 R/W
0x032 CH3_GAIN_ MID_BYTE
[7:0] CH3_GAIN_ALL[15:8] 0x00 R/W
0x033 CH3_GAIN_ LOWER_BYTE
[7:0] CH3_GAIN_ALL[7:0] 0x00 R/W
0x034 CH4_OFFSET_ UPPER_BYTE
[7:0] CH4_OFFSET_ALL[23:16] 0x00 R/W
0x035 CH4_OFFSET_ MID_BYTE
[7:0] CH4_OFFSET_ALL[15:8] 0x00 R/W
0x036 CH4_OFFSET_ LOWER_BYTE
[7:0] CH4_OFFSET_ALL[7:0] 0x00 R/W
0x037 CH4_GAIN_ UPPER_BYTE
[7:0] CH4_GAIN_ALL[23:16] 0x00 R/W
0x038 CH4_GAIN_ MID_BYTE
[7:0] CH4_GAIN_ALL[15:8] 0x00 R/W
0x039 CH4_GAIN_ LOWER_BYTE
[7:0] CH4_GAIN_ALL[7:0] 0x00 R/W
0x03A CH5_OFFSET_ UPPER_BYTE
[7:0] CH5_OFFSET_ALL[23:16] 0x00 R/W
0x03B CH5_OFFSET_ MID_BYTE
[7:0] CH5_OFFSET_ALL[15:8] 0x00 R/W
0x03C CH5_OFFSET_ LOWER_BYTE
[7:0] CH5_OFFSET_ALL[7:0] 0x00 R/W
0x03D CH5_GAIN_ UPPER_BYTE
[7:0] CH5_GAIN_ALL[23:16] 0x00 R/W
0x03E CH5_GAIN_ MID_BYTE
[7:0] CH5_GAIN_ALL[15:8] 0x00 R/W
Data Sheet AD7771
Rev. 0 | Page 63 of 98
Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x03F CH5_GAIN_ LOWER_BYTE
[7:0] CH5_GAIN_ALL[7:0] 0x00 R/W
0x040 CH6_OFFSET_ UPPER_BYTE
[7:0] CH6_OFFSET_ALL[23:16] 0x00 R/W
0x041 CH6_OFFSET_ MID_BYTE
[7:0] CH6_OFFSET_ALL[15:8] 0x00 R/W
0x042 CH6_OFFSET_ LOWER_BYTE
[7:0] CH6_OFFSET_ALL[7:0] 0x00 R/W
0x043 CH6_GAIN_ UPPER_BYTE
[7:0] CH6_GAIN_ALL[23:16] 0x00 R/W
0x044 CH6_GAIN_ MID_BYTE
[7:0] CH6_GAIN_ALL[15:8] 0x00 R/W
0x045 CH6_GAIN_ LOWER_BYTE
[7:0] CH6_GAIN_ALL[7:0] 0x00 R/W
0x046 CH7_OFFSET_ UPPER_BYTE
[7:0] CH7_OFFSET_ALL[23:16] 0x00 R/W
0x047 CH7_OFFSET_ MID_BYTE
[7:0] CH7_OFFSET_ALL[15:8] 0x00 R/W
0x048 CH7_OFFSET_ LOWER_BYTE
[7:0] CH7_OFFSET_ALL[7:0] 0x00 R/W
0x049 CH7_GAIN_ UPPER_BYTE
[7:0] CH7_GAIN_ALL[23:16] 0x00 R/W
0x04A CH7_GAIN_ MID_BYTE
[7:0] CH7_GAIN_ALL[15:8] 0x00 R/W
0x04B CH7_GAIN_ LOWER_BYTE
[7:0] CH7_GAIN_ALL[7:0] 0x00 R/W
0x04C CH0_ERR_REG [7:0] RESERVED CH0_ERR_ AINM_UV
CH0_ERR_ AINM_OV
CH0_ERR_ AINP_UV
CH0_ERR_ AINP_OV
CH0_ERR_ REF_DET
0x00 R
0x04D CH1_ERR_REG [7:0] RESERVED CH1_ERR_ AINM_UV
CH1_ERR_ AINM_OV
CH1_ERR_ AINP_UV
CH1_ERR_ AINP_OV
CH1_ERR_ REF_DET
0x00 R
0x04E CH2_ERR_REG [7:0] RESERVED CH2_ERR_ AINM_UV
CH2_ERR_ AINM_OV
CH2_ERR_ AINP_UV
CH2_ERR_ AINP_OV
CH2_ERR_ REF_DET
0x00 R
0x04F CH3_ERR_REG [7:0] RESERVED CH3_ERR_ AINM_UV
CH3_ERR_ AINM_OV
CH3_ERR_ AINP_UV
CH3_ERR_ AINP_OV
CH3_ERR_ REF_DET
0x00 R
0x050 CH4_ERR_REG [7:0] RESERVED CH4_ERR_ AINM_UV
CH4_ERR_ AINM_OV
CH4_ERR_ AINP_UV
CH4_ERR_AINP_OV
CH4_ERR_ REF_DET
0x00 R
0x051 CH5_ERR_REG [7:0] RESERVED CH5_ERR_ AINM_UV
CH5_ERR_ AINM_OV
CH5_ERR_ AINP_UV
CH5_ERR_ AINP_OV
CH5_ERR_ REF_DET
0x00 R
0x052 CH6_ERR_REG [7:0] RESERVED CH6_ERR_ AINM_UV
CH6_ERR_ AINM_OV
CH6_ERR_ AINP_UV
CH6_ERR_ AINP_OV
CH6_ERR_ REF_DET
0x00 R
0x053 CH7_ERR_REG [7:0] RESERVED CH7_ERR_ AINM_UV
CH7_ERR_ AINM_OV
CH7_ERR_ AINP_UV
CH7_ERR_ AINP_OV
CH7_ERR_ REF_DET
0x00 R
0x054 CH0_1_SAT_ ERR
[7:0] RESERVED CH1_ERR_ MOD_SAT
CH1_ERR_ FILTER_SAT
CH1_ERR_ OUTPUT_ SAT
CH0_ERR_ MOD_SAT
CH0_ERR_ FILTER_SAT
CH0_ERR_ OUTPUT_ SAT
0x00 R
0x055 CH2_3_SAT_ ERR
[7:0] RESERVED CH3_ERR_ MOD_SAT
CH3_ERR_ FILTER_SAT
CH3_ERR_ OUTPUT_ SAT
CH2_ERR_ MOD_SAT
CH2_ERR_ FILTER_SAT
CH2_ERR_ OUTPUT_ SAT
0x00 R
0x056 CH4_5_SAT_ ERR
[7:0] RESERVED CH5_ERR_ MOD_SAT
CH5_ERR_ FILTER_SAT
CH5_ERR_ OUTPUT_ SAT
CH4_ERR_ MOD_SAT
CH4_ERR_ FILTER_SAT
CH4_ERR_ OUTPUT_ SAT
0x00 R
0x057 CH6_7_SAT_ ERR
[7:0] RESERVED CH7_ERR_ MOD_SAT
CH7_ERR_ FILTER_SAT
CH7_ERR_ OUTPUT_ SAT
CH6_ERR_ MOD_SAT
CH6_ERR_ FILTER_SAT
CH6_ERR_ OUTPUT_ SAT
0x00 R
0x058 CHX_ERR_ REG_EN
[7:0] OUTPUT_SAT_ TEST_EN
FILTER_ SAT_ TEST_EN
MOD_SAT_ TEST_EN
AINM_UV_ TEST_EN
AINM_OV_ TEST_EN
AINP_UV_ TEST_EN
AINP_OV_ TEST_EN
REF_DET_ TEST_EN
0xFE R/W
0x059 GEN_ERR_ REG_1
[7:0] RESERVED MEMMAP_ CRC_ERR
ROM_CRC_ ERR
SPI_CLK_ COUNT_ ERR
SPI_ INVALID_ READ_ERR
SPI_ INVALID_ WRITE_ERR
SPI_CRC_ ERR
0x00 R
0x05A GEN_ERR_ REG_1_EN
[7:0] RESERVED MEMMAP_ CRC_TEST_EN
ROM_CRC_ TEST_EN
SPI_CLK_ COUNT_ TEST_EN
SPI_ INVALID_ READ_ TEST_EN
SPI_ INVALID_ WRITE_ TEST_EN
SPI_CRC_ TEST_EN
0x3E R/W
0x05B GEN_ERR_ REG_2
[7:0] RESERVED RESET_ DETECTED
EXT_MCLK_ SWITCH_ERR
RESERVED ALDO1_ PSM_ERR
ALDO2_ PSM_ERR
DLDO_ PSM_ERR
0x00 R
0x05C GEN_ERR_ REG_2_EN
[7:0] RESERVED RESET_ DETECT_EN
RESERVED LDO_PSM_TEST_EN LDO_PSM_TRIP_TEST_EN 0x3C R/W
AD7771 Data Sheet
Rev. 0 | Page 64 of 98
Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x05D STATUS_REG_1 [7:0] RESERVED CHIP_ERROR ERR_LOC_ CH4
ERR_LOC_ CH3
ERR_LOC_ CH2
ERR_LOC_ CH1
ERR_LOC_CH0
0x00 R
0x05E STATUS_REG_2 [7:0] RESERVED CHIP_ERROR ERR_LOC_ GEN2
ERR_LOC_ GEN1
ERR_LOC_ CH7
ERR_LOC_ CH6
ERR_LOC_CH5
0x00 R
0x05F STATUS_REG_3 [7:0] RESERVED CHIP_ERROR INIT_ COMPLETE
ERR_LOC_ SAT_CH6_7
ERR_LOC_ SAT_CH4_5
ERR_LOC_ SAT_CH2_3
ERR_LOC_ SAT_CH0_1
0x00 R
0x060 SRC_N_MSB [7:0] RESERVED SRC_N_ALL[11:8] 0x00 R/W
0x061 SRC_N_LSB [7:0] SRC_N_ALL[7:0] 0x80 R/W
0x062 SRC_IF_MSB [7:0] SRC_IF_ALL[15:8] 0x00 R/W
0x063 SRC_IF_LSB [7:0] SRC_IF_ALL[7:0] 0x00 R/W
0x064 SRC_UPDATE [7:0] SRC_ LOAD_ SOURCE
RESERVED SRC_LOAD_ UPDATE
0x00 R/W
Data Sheet AD7771
Rev. 0 | Page 65 of 98
REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER Address: 0x000, Reset: 0x00, Name: CH0_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH0_GAIN (R/W) [2:0] RESERVED
[5] CH0_REF_MONITOR (R/W)
[3] RESERVED
[4] CH0_RX (R/W)
Table 44. Bit Descriptions for CH0_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH0_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH0_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH0_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
CHANNEL 1 CONFIGURATION REGISTER Address: 0x001, Reset: 0x00, Name: CH1_CONFIG
AFE Gain
11: Gain = 8.10: Gain = 4.01: Gain = 2.00: Gain = 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH1_GAIN (R/W) [2:0] RESERVED
[5] CH1_REF_MONITOR (R/W)
[3] RESERVED
[4] CH1_RX (R/W)
Table 45. Bit Descriptions for CH1_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH1_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH1_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH1_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 66 of 98
CHANNEL 2 CONFIGURATION REGISTER Address: 0x002, Reset: 0x00, Name: CH2_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH2_GAIN (R/W) [2:0] RESERVED
[5] CH2_REF_MONITOR (R/W)
[3] RESERVED
[4] CH2_RX (R/W)
Table 46. Bit Descriptions for CH2_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH2_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH2_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH2_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
CHANNEL 3 CONFIGURATION REGISTER Address: 0x003, Reset: 0x00, Name: CH3_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH3_GAIN (R/W) [2:0] RESERVED
[5] CH3_REF_MONITOR (R/W)
[3] RESERVED
[4] CH3_RX (R/W)
Table 47. Bit Descriptions for CH3_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH3_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH3_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH3_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 67 of 98
CHANNEL 4 CONFIGURATION REGISTER Address: 0x004, Reset: 0x00, Name: CH4_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH4_GAIN (R/W) [2:0] RESERVED
[5] CH4_REF_MONITOR (R/W)
[3] RESERVED
[4] CH4_RX (R/W)
Table 48. Bit Descriptions for CH4_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH4_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH4_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH4_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
CHANNEL 5 CONFIGURATION REGISTER Address: 0x005, Reset: 0x00, Name: CH5_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH5_GAIN (R/W) [2:0] RESERVED
[5] CH5_REF_MONITOR (R/W)
[3] RESERVED
[4] CH5_RX (R/W)
Table 49. Bit Descriptions for CH5_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH5_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH5_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH5_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 68 of 98
CHANNEL 6 CONFIGURATION REGISTER Address: 0x006, Reset: 0x00, Name: CH6_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH6_GAIN (R/W) [2:0] RESERVED
[5] CH6_REF_MONITOR (R/W)
[3] RESERVED
[4] CH6_RX (R/W)
Table 50. Bit Descriptions for CH6_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH6_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH6_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH6_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
CHANNEL 7 CONFIGURATION REGISTER Address: 0x007, Reset: 0x00, Name: CH7_CONFIG
AFE Gain
11: Gain 8.10: Gain 4.01: Gain 2.00: Gain 1.
Channel used as Reference monitor
Channel Meter Mux RX Mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] CH7_GAIN (R/W) [2:0] RESERVED
[5] CH7_REF_MONITOR (R/W)
[3] RESERVED
[4] CH7_RX (R/W)
Table 51. Bit Descriptions for CH7_CONFIG Bits Bit Name Settings Description Reset Access [7:6] CH7_GAIN AFE Gain 0x0 R/W 00 Gain = 1 01 Gain = 2 10 Gain = 4 11 Gain = 8 5 CH7_REF_MONITOR Channel Used as Reference Monitor 0x0 R/W 4 CH7_RX Channel Meter Mux Rx Mode 0x0 R/W [3:0] RESERVED Reserved 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 69 of 98
DISABLE CLOCKS TO ADC CHANNEL REGISTER Address: 0x008, Reset: 0x00, Name: CH_DISABLE
Channel 7 Disable Channel 0 Disable
Channel 6 Disable Channel 1 Disable
Channel 5 Disable Channel 2 Disable
Channel 4 Disable Channel 3 Disable
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] CH7_DISABLE (R/W) [0] CH0_DISABLE (R/W)
[6] CH6_DISABLE (R/W) [1] CH1_DISABLE (R/W)
[5] CH5_DISABLE (R/W) [2] CH2_DISABLE (R/W)
[4] CH4_DISABLE (R/W) [3] CH3_DISABLE (R/W)
Table 52. Bit Descriptions for CH_DISABLE Bits Bit Name Settings Description Reset Access 7 CH7_DISABLE Channel 7 Disable 0x0 R/W 6 CH6_DISABLE Channel 6 Disable 0x0 R/W 5 CH5_DISABLE Channel 5 Disable 0x0 R/W 4 CH4_DISABLE Channel 4 Disable 0x0 R/W 3 CH3_DISABLE Channel 3 Disable 0x0 R/W 2 CH2_DISABLE Channel 2 Disable 0x0 R/W 1 CH1_DISABLE Channel 1 Disable 0x0 R/W 0 CH0_DISABLE Channel 0 Disable 0x0 R/W
CHANNEL 0 SYNC OFFSET REGISTER Address: 0x009, Reset: 0x00, Name: CH0_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_SYNC_OFFSET (R/W)
Table 53. Bit Descriptions for CH0_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH0_SYNC_OFFSET Channel Sync Offset 0x0 R/W
CHANNEL 1 SYNC OFFSET REGISTER Address: 0x00A, Reset: 0x00, Name: CH1_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_SYNC_OFFSET (R/W)
Table 54. Bit Descriptions for CH1_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH1_SYNC_OFFSET Channel Sync Offset 0x0 R/W
CHANNEL 2 SYNC OFFSET REGISTER Address: 0x00B, Reset: 0x00, Name: CH2_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_SYNC_OFFSET (R/W)
Table 55. Bit Descriptions for CH2_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH2_SYNC_OFFSET Channel Sync Offset 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 70 of 98
CHANNEL 3 SYNC OFFSET REGISTER Address: 0x00C, Reset: 0x00, Name: CH3_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_SYNC_OFFSET (R/W)
Table 56. Bit Descriptions for CH3_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH3_SYNC_OFFSET Channel Sync Offset 0x0 R/W
CHANNEL 4 SYNC OFFSET REGISTER Address: 0x00D, Reset: 0x00, Name: CH4_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_SYNC_OFFSET (R/W)
Table 57. Bit Descriptions for CH4_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH4_SYNC_OFFSET Channel Sync Offset 0x0 R/W
CHANNEL 5 SYNC OFFSET REGISTER Address: 0x00E, Reset: 0x00, Name: CH5_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_SYNC_OFFSET (R/W)
Table 58. Bit Descriptions for CH5_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH5_SYNC_OFFSET Channel Sync Offset 0x0 R/W
CHANNEL 6 SYNC OFFSET REGISTER Address: 0x00F, Reset: 0x00, Name: CH6_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_SYNC_OFFSET (R/W)
Table 59. Bit Descriptions for CH6_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH6_SYNC_OFFSET Channel Sync Offset 0x0 R/W
CHANNEL 7 SYNC OFFSET REGISTER Address: 0x010, Reset: 0x00, Name: CH7_SYNC_OFFSET
Channel Sync Offset
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_SYNC_OFFSET (R/W)
Table 60. Bit Descriptions for CH7_SYNC_OFFSET Bits Bit Name Settings Description Reset Access [7:0] CH7_SYNC_OFFSET Channel Sync Offset 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 71 of 98
GENERAL USER CONFIGURATION 1 REGISTER Address: 0x011, Reset: 0x24, Name: GENERAL_USER_CONFIG_1
If all SD channels are disabled, settingthis bit high allows DCLK to continuetoggling
Soft Reset
11: 1st write.10: 2nd write.01: No Effect.00: No Effect.
Power Mode
1: High Resolution.0: Low Power (1/4)
Power-Down signal for internal oscillator.Active Low
Power-Down VCM Buffer. Active LowPower-Down SAR. Active Low
Power-Down Internal Reference OutputBuffer. Active Low
0
0
1
0
2
1
3
0
4
0
5
1
6
0
7
0
[7] ALL_CH_DIS_MCLK_EN (R/W) [1:0] SOFT_RESET (R/W)
[6] POWERMODE (R/W)
[2] PDB_RC_OSC (R/W)
[5] PDB_VCM (R/W)[3] PDB_SAR (R/W)
[4] PDB_REFOUT_BUF (R/W)
Table 61. Bit Descriptions for GENERAL_USER_CONFIG_1 Bits Bit Name Settings Description Reset Access 7 ALL_CH_DIS_MCLK_EN If all Σ-Δ channels are disabled, setting this bit high allows DCLK to
continue toggling. 0x0 R/W
6 POWERMODE Power Mode. 0x0 R/W 0 Low power (1/4). 1 High resolution. 5 PDB_VCM Power-Down VCM Buffer. Active low. 0x1 R/W 4 PDB_REFOUT_BUF Power-Down Internal Reference Output Buffer. Active low. 0x0 R/W 3 PDB_SAR Power-Down SAR. Active low. 0x0 R/W 2 PDB_RC_OSC Power-Down Signal for Internal Oscillator. Active low. 0x1 R/W [1:0] SOFT_RESET Soft Reset 0x0 R/W 00 No effect 01 No effect 10 2nd write 11 1st write
AD7771 Data Sheet
Rev. 0 | Page 72 of 98
GENERAL USER CONFIGURATION 2 REGISTER Address: 0x012, Reset: 0x09, Name: GENERAL_USER_CONFIG_2
SYNC pulse generated thru SPI
1:STARTb pin in the control module.This bit is ANDed with the value on
0:
generate a pulse in /SYNC_IN pin.on STARTb pin in the control module,This signal is ANDed with the value
0=Sinc3. 1=Sinc5
DOUT Drive Strength
11: Extra Strong.10: Weak.01: Strong.00: Nominal.
Sets SPI interface to read back SARresult on SDO
SDO Drive Strength
11: Extra Strong.10: Weak.01: Strong.00: Nominal.
0
1
1
0
2
0
3
1
4
0
5
0
6
0
7
0
[7] RESERVED [0] SPI_SYNC (R/W)
[6] FILTER_MODE (R/W)
[2:1] DOUT_DRIVE_STR (R/W)
[5] SAR_DIAG_MODE_EN (R/W)
[4:3] SDO_DRIVE_STR (R/W)
Table 62. Bit Descriptions for GENERAL_USER_CONFIG_2 Bits Bit Name Settings Description Reset Access 7 RESERVED Reserved. 0x0 R/W 6 FILTER_MODE 0 = Sinc3. 1 = Sinc5. 0x0 R/W 5 SAR_DIAG_MODE_EN Sets SPI interface to read back SAR result on SDO. 0x0 R/W [4:3] SDO_DRIVE_STR SDO Drive Strength. 0x1 R/W 00 Nominal. 01 Strong. 10 Weak. 11 Extra Strong. [2:1] DOUT_DRIVE_STR DOUTx Drive Strength. 0x0 R/W 00 Nominal. 01 Strong. 10 Weak. 11 Extra Strong. 0 SPI_SYNC Sync pulse generated through SPI. 0x1 R/W 0 This signal is AND’ed with the value on START pin in the control module to
generate a pulse in SYNC_IN pin.
1 This bit is AND’ed with the value on START pin in the control module.
Data Sheet AD7771
Rev. 0 | Page 73 of 98
GENERAL USER CONFIGURATION 3 REGISTER Address: 0x013, Reset: 0x80, Name: GENERAL_USER_CONFIG_3
Disable deglitching of CONVST_SARpin
11: No deglitch circuit.10: CONVST_SAR Deglitch 1.5/ MCLK.01: Reserved.00: Reserved.
Disables the clock qualifier checkif the user requires to use an MCLKsignal < 265kHz.
Enable to SPI slave mode to readback ADC on SDO
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:6] CONVST_DEGLITCH_DIS (R/W) [0] CLK_QUAL_DIS (R/W)
[5] RESERVED
[3:1] RESERVED
[4] SPI_SLAVE_MODE_EN (R/W)
Table 63. Bit Descriptions for GENERAL_USER_CONFIG_3 Bits Bit Name Settings Description Reset Access [7:6] CONVST_DEGLITCH_DIS Disable deglitching of CONVST_SAR pin. 0x2 R/W 00 Reserved. 01 Reserved. 10 CONVST_SAR deglitch 1.5/MCLK. 11 No deglitch circuit. 5 RESERVED Reserved. 0x0 R/W 4 SPI_SLAVE_MODE_EN Enable to SPI slave mode to read back ADC on SDO. 0x0 R/W [3:2] RESERVED Reserved. 0x0 R/W 1 RESERVED Reserved. 0x0 R/W 0 CLK_QUAL_DIS Disables the clock qualifier check if the user requires to use an MCLK
signal <265 kHz. 0x0 R/W
DATA OUTPUT FORMAT REGISTER Address: 0x014, Reset: 0x20, Name: DOUT_FORMAT
Data out format
11: 1 DOUT Lines.10: 1 DOUT Lines.01: 2 DOUT Lines.00: 4 DOUT Lines.
Dout header format
1: CRC Header.0: Status Header.
Divide MCLK
111: Divide by 128.110: Divide by 64.101: Divide by 32.100: Divide by 16.011: Divide by 8.010: Divide by 4.001: Divide by 2.000: Divide by 1.
0
0
1
0
2
0
3
0
4
0
5
1
6
0
7
0
[7:6] DOUT_FORMAT (R/W) [0] RESERVED
[5] DOUT_HEADER_FORMAT (R/W)
[3:1] DCLK_CLK_DIV (R/W)
[4] RESERVED
Table 64. Bit Descriptions for DOUT_FORMAT Bits Bit Name Settings Description Reset Access [7:6] DOUT_FORMAT Data Out Format 0x0 R/W 00 4 DOUTx lines 01 2 DOUTx lines 10 1 DOUTx lines 11 1 DOUTx line 5 DOUT_HEADER_FORMAT DOUTx Header Format 0x1 R/W 0 Status header 1 CRC header 4 RESERVED Reserved 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 74 of 98
Bits Bit Name Settings Description Reset Access [3:1] DCLK_CLK_DIV Divide MCLK 0x0 R/W 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 0 RESERVED Reserved 0x0 R/W
MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER Address: 0x015, Reset: 0x00, Name: ADC_MUX_CONFIG
SD ADC Reference Mux
11: External Reference REFx-/REFx+.10: External Supply AVDD1x/AVSSx.01: Internal Reference.00: External Reference REFx+/REFx-
SD ADC Meter Mux
1001: External Reference REFx+/REFx+.1000: Internal Reference +/+.0111: Internal Reference -/+.0110: Internal Reference +/-0101: External Reference REFx-/REFx-0100: External Reference REFx-/REFx+.0011: External Reference REFx+/REFx-0010: 280mV.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] REF_MUX_CTRL (R/W) [1:0] RESERVED
[5:2] MTR_MUX_CTRL (R/W)
Table 65. Bit Descriptions for ADC_MUX_CONFIG Bits Bit Name Settings Description Reset Access [7:6] REF_MUX_CTRL Σ-Δ ADC Reference Mux. 0x0 R/W 00 External reference REFx+/REFx−. 01 Internal reference. 10 External supply AVDD1x/AVSSx. 11 External reference REFx−/REFx+. [5:2] MTR_MUX_CTRL Σ-Δ ADC Meter Mux. 0x0 R/W 0010 280 mV. 0011 External reference REFx+/REFx−. 0100 External reference REFx−/REFx+. 0101 External reference REFx−/REFx−. 0110 Internal reference +/−. 0111 Internal reference −/+. 1000 Internal reference +/+. 1001 External reference REFx+/REFx+. [1:0] RESERVED Reserved. 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 75 of 98
GLOBAL DIAGNOSTICS MUX REGISTER Address: 0x016, Reset: 0x00, Name: GLOBAL_MUX_CONFIG
Global SAR diagnostics mux control
10101: AVSSx AVDD4. Attenuated.10100: REF2+ AVSSx.10011: REF1+ AVSSx.
...00010: REF1P REF1N.00001: DVBE AVSSx.00000: AUXAin+ AUXAin-
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:3] GLOBAL_MUX_CTRL (R/W) [2:0] RESERVED
Table 66. Bit Descriptions for GLOBAL_MUX_CONFIG Bits Bit Name Settings Description Reset Access [7:3] GLOBAL_MUX_CTRL Global SAR Diagnostics Mux Control. 0x0 R/W 00000 AUXAIN+/AUXAIN−. 00001 DVBE/AVSSx. 00010 REF1+/REF1−. 10011 REF2+/REF2−. 10100 REF_OUT/AVSSx. 10101 VCM/AVSSx. 10110 AREG1CAP/AVSSx. 10111 AREG2CAP/AVSSx. 11000 DREGCAP/DGND. 11001 AVDD1A/AVSSx. 11010 AVDD1B/AVSSx. 11011 AVDD2A/AVSSx. 11100 AVDD2B/AVSSx. 11101 IOVDD/DGND. 11110 AVDD4/AVSSx. 11111 DGND/AVSSx. 10000 DGND/AVSSx. 10001 DGND/AVSSx. 10010 AVDD4/AVSSx. 10011 REF1+/AVSSx. 10100 REF2+/AVSSx. 10101 AVSSx/AVDD4. Attenuated. [2:0] RESERVED Reserved. 0x0 R/W
GPIO CONFIGURATION REGISTER Address: 0x017, Reset: 0x00, Name: GPIO_CONFIG
GPIO input/output
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:3] RESERVED [2:0] GPIO_OP_EN (R/W)
Table 67. Bit Descriptions for GPIO_CONFIG Bits Bit Name Settings Description Reset Access [7:3] RESERVED Reserved. 0x0 R/W [2:0] GPIO_OP_EN GPIO Input/Output 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 76 of 98
GPIO DATA REGISTER Address: 0x018, Reset: 0x00, Name: GPIO_DATA
Value sent to GPIO pins
Data read from GPIO pins
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [2:0] GPIO_WRITE_DATA (R/W)
[5:3] GPIO_READ_DATA (R)
Table 68. Bit Descriptions for GPIO_DATA Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved. 0x0 R/W [5:3] GPIO_READ_DATA Data Read from the GPIO Pins 0x0 R [2:0] GPIO_WRITE_DATA Value Sent to the GPIO Pins 0x0 R/W
BUFFER CONFIGURATION 1 REGISTER Address: 0x019, Reset: 0x38, Name: BUFFER_CONFIG_1
Reference buffer positive enable Reference buffer negative enable
0
0
1
0
2
0
3
1
4
1
5
0
6
0
7
0
[7] RESERVED [0] RESERVED
[6] RESERVED [1] RESERVED
[5] RESERVED [2] RESERVED
[4] REF_BUF_POS_EN (R/W) [3] REF_BUF_NEG_EN (R/W)
Table 69. Bit Descriptions for BUFFER_CONFIG_1 Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 REF_BUF_POS_EN Reference Buffer Positive Enable 0x1 R/W 3 REF_BUF_NEG_EN Reference Buffer Negative Enable 0x1 R/W [2:0] RESERVED Reserved 0x0 R/W
BUFFER CONFIGURATION 2 REGISTER Address: 0x01A, Reset: 0xC0, Name: BUFFER_CONFIG_2
Reference buffer positive prechargeenable
DRegCap Overdrive Enable.
Reference buffer negative prechargeenable
AReg2Cap Overdrive Enable
AReg1Cap Overdrive Enable
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
1
[7] REFBUFP_PREQ (R/W) [0] PDB_DLDO_OVRDRV (R/W)
[6] REFBUFN_PREQ (R/W)[1] PDB_ALDO2_OVRDRV (R/W)
[5:3] RESERVED
[2] PDB_ALDO1_OVRDRV (R/W)
Table 70. Bit Descriptions for BUFFER_CONFIG_2 Bits Bit Name Settings Description Reset Access 7 REFBUFP_PREQ Reference Buffer Positive Precharge Enable 0x1 R/W 6 REFBUFN_PREQ Reference Buffer Negative Precharge Enable 0x1 R/W [5:3] RESERVED Reserved 0x0 R/W 2 PDB_ALDO1_OVRDRV AREG1CAP Overdrive Enable 0x0 R/W 1 PDB_ALDO2_OVRDRV AREG2CAP Overdrive Enable 0x0 R/W 0 PDB_DLDO_OVRDRV DREGCAP Overdrive Enable 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 77 of 98
CHANNEL 0 OFFSET UPPER BYTE REGISTER Address: 0x01C, Reset: 0x00, Name: CH0_OFFSET_UPPER_BYTE
Combined Offset register Channel 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_OFFSET_ALL[23:16] (R/W)
Table 71. Bit Descriptions for CH0_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH0_OFFSET_ALL[23:16] Combined Offset Register Channel 0 0x0 R/W
CHANNEL 0 OFFSET MIDDLE BYTE REGISTER Address: 0x01D, Reset: 0x00, Name: CH0_OFFSET_MID_BYTE
Combined Offset register Channel 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_OFFSET_ALL[15:8] (R/W)
Table 72. Bit Descriptions for CH0_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH0_OFFSET_ALL[15:8] Combined Offset Register Channel 0 0x0 R/W
CHANNEL 0 OFFSET LOWER BYTE REGISTER Address: 0x01E, Reset: 0x00, Name: CH0_OFFSET_LOWER_BYTE
Combined Offset register Channel 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_OFFSET_ALL[7:0] (R/W)
Table 73. Bit Descriptions for CH0_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH0_OFFSET_ALL[7:0] Combined Offset Register Channel 0 0x0 R/W
CHANNEL 0 GAIN UPPER BYTE REGISTER Address: 0x01F, Reset: 0x00, Name: CH0_GAIN_UPPER_BYTE
Combined gain register Channel 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_GAIN_ALL[23:16] (R/W)
Table 74. Bit Descriptions for CH0_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH0_GAIN_ALL[23:16] Combined Gain Register Channel 0 0x0 R/W
CHANNEL 0 GAIN MIDDLE BYTE REGISTER Address: 0x020, Reset: 0x00, Name: CH0_GAIN_MID_BYTE
Combined gain register Channel 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_GAIN_ALL[15:8] (R/W)
Table 75. Bit Descriptions for CH0_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH0_GAIN_ALL[15:8] Combined Gain Register Channel 0 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 78 of 98
CHANNEL 0 GAIN LOWER BYTE REGISTER Address: 0x021, Reset: 0x00, Name: CH0_GAIN_LOWER_BYTE
Combined gain register Channel 0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH0_GAIN_ALL[7:0] (R/W)
Table 76. Bit Descriptions for CH0_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH0_GAIN_ALL[7:0] Combined Gain Register Channel 0 0x0 R/W
CHANNEL 1 OFFSET UPPER BYTE REGISTER Address: 0x022, Reset: 0x00, Name: CH1_OFFSET_UPPER_BYTE
Combined offset register Channel 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_OFFSET_ALL[23:16] (R/W)
Table 77. Bit Descriptions for CH1_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH1_OFFSET_ALL[23:16] Combined Offset Register Channel 1 0x0 R/W
CHANNEL 1 OFFSET MIDDLE BYTE REGISTER Address: 0x023, Reset: 0x00, Name: CH1_OFFSET_MID_BYTE
Combined offset register Channel 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_OFFSET_ALL[15:8] (R/W)
Table 78. Bit Descriptions for CH1_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH1_OFFSET_ALL[15:8] Combined Offset Register Channel 1 0x0 R/W
CHANNEL 1 OFFSET LOWER BYTE REGISTER Address: 0x024, Reset: 0x00, Name: CH1_OFFSET_LOWER_BYTE
Combined offset register Channel 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_OFFSET_ALL[7:0] (R/W)
Table 79. Bit Descriptions for CH1_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH1_OFFSET_ALL[7:0] Combined Offset Register Channel 1 0x0 R/W
CHANNEL 1 GAIN UPPER BYTE REGISTER Address: 0x025, Reset: 0x00, Name: CH1_GAIN_UPPER_BYTE
Combined gain register Channel 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_GAIN_ALL[23:16] (R/W)
Table 80. Bit Descriptions for CH1_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH1_GAIN_ALL[23:16] Combined Gain Register Channel 1 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 79 of 98
CHANNEL 1 GAIN MIDDLE BYTE REGISTER Address: 0x026, Reset: 0x00, Name: CH1_GAIN_MID_BYTE
Combined gain register Channel 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_GAIN_ALL[15:8] (R/W)
Table 81. Bit Descriptions for CH1_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH1_GAIN_ALL[15:8] Combined Gain Register Channel 1 0x0 R/W
CHANNEL 1 GAIN LOWER BYTE REGISTER Address: 0x027, Reset: 0x00, Name: CH1_GAIN_LOWER_BYTE
Combined gain register Channel 1
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH1_GAIN_ALL[7:0] (R/W)
Table 82. Bit Descriptions for CH1_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH1_GAIN_ALL[7:0] Combined Gain Register Channel 1 0x0 R/W
CHANNEL 2 OFFSET UPPER BYTE REGISTER Address: 0x028, Reset: 0x00, Name: CH2_OFFSET_UPPER_BYTE
Combined offset register Channel 2
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_OFFSET_ALL[23:16] (R/W)
Table 83. Bit Descriptions for CH2_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH2_OFFSET_ALL[23:16] Combined Offset Register Channel 2 0x0 R/W
CHANNEL 2 OFFSET MIDDLE BYTE REGISTER Address: 0x029, Reset: 0x00, Name: CH2_OFFSET_MID_BYTE
Combined offset register Channel 2
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_OFFSET_ALL[15:8] (R/W)
Table 84. Bit Descriptions for CH2_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH2_OFFSET_ALL[15:8] Combined Offset Register Channel 2 0x0 R/W
CHANNEL 2 OFFSET LOWER BYTE REGISTER Address: 0x02A, Reset: 0x00, Name: CH2_OFFSET_LOWER_BYTE
Combined offset register Channel 2
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_OFFSET_ALL[7:0] (R/W)
Table 85. Bit Descriptions for CH2_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH2_OFFSET_ALL[7:0] Combined Offset Register Channel 2 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 80 of 98
CHANNEL 2 GAIN UPPER BYTE REGISTER Address: 0x02B, Reset: 0x00, Name: CH2_GAIN_UPPER_BYTE
Combined gain register Channel 2
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_GAIN_ALL[23:16] (R/W)
Table 86. Bit Descriptions for CH2_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH2_GAIN_ALL[23:16] Combined Gain Register Channel 2 0x0 R/W
CHANNEL 2 GAIN MIDDLE BYTE REGISTER Address: 0x02C, Reset: 0x00, Name: CH2_GAIN_MID_BYTE
Combined gain register Channel 2
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_GAIN_ALL[15:8] (R/W)
Table 87. Bit Descriptions for CH2_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH2_GAIN_ALL[15:8] Combined Gain Register Channel 2 0x0 R/W
CHANNEL 2 GAIN LOWER BYTE REGISTER Address: 0x02D, Reset: 0x00, Name: CH2_GAIN_LOWER_BYTE
Combined gain register Channel 2
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH2_GAIN_ALL[7:0] (R/W)
Table 88. Bit Descriptions for CH2_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH2_GAIN_ALL[7:0] Combined Gain Register Channel 2 0x0 R/W
CHANNEL 3 OFFSET UPPER BYTE REGISTER Address: 0x02E, Reset: 0x00, Name: CH3_OFFSET_UPPER_BYTE
Combined offset register Channel 3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_OFFSET_ALL[23:16] (R/W)
Table 89. Bit descriptions for CH3_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH3_OFFSET_ALL[23:16] Combined Offset Register Channel 3 0x0 R/W
CHANNEL 3 OFFSET MIDDLE BYTE REGISTER Address: 0x02F, Reset: 0x00, Name: CH3_OFFSET_MID_BYTE
Combined offset register Channel 3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_OFFSET_ALL[15:8] (R/W)
Table 90. Bit Descriptions for CH3_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH3_OFFSET_ALL[15:8] Combined Offset Register Channel 3 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 81 of 98
CHANNEL 3 OFFSET LOWER BYTE REGISTER Address: 0x030, Reset: 0x00, Name: CH3_OFFSET_LOWER_BYTE
Combined offset register Channel 3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_OFFSET_ALL[7:0] (R/W)
Table 91. Bit Descriptions for CH3_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH3_OFFSET_ALL[7:0] Combined Offset Register Channel 3 0x0 R/W
CHANNEL 3 GAIN UPPER BYTE REGISTER Address: 0x031, Reset: 0x00, Name: CH3_GAIN_UPPER_BYTE
Combined gain register Channel 3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_GAIN_ALL[23:16] (R/W)
Table 92. Bit Descriptions for CH3_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH3_GAIN_ALL[23:16] Combined Gain Register Channel 3 0x0 R/W
CHANNEL 3 GAIN MIDDLE BYTE REGISTER Address: 0x032, Reset: 0x00, Name: CH3_GAIN_MID_BYTE
Combined gain register Channel 3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_GAIN_ALL[15:8] (R/W)
Table 93. Bit Descriptions for CH3_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH3_GAIN_ALL[15:8] Combined Gain Register Channel 3 0x0 R/W
CHANNEL 3 GAIN LOWER BYTE REGISTER Address: 0x033, Reset: 0x00, Name: CH3_GAIN_LOWER_BYTE
Combined gain register Channel 3
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH3_GAIN_ALL[7:0] (R/W)
Table 94. Bit Descriptions for CH3_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH3_GAIN_ALL[7:0] Combined Gain Register Channel 3 0x0 R/W
CHANNEL 4 OFFSET UPPER BYTE REGISTER Address: 0x034, Reset: 0x00, Name: CH4_OFFSET_UPPER_BYTE
Combined offset register Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_OFFSET_ALL[23:16] (R/W)
Table 95. Bit Descriptions for CH4_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH4_OFFSET_ALL[23:16] Combined Offset Register Channel 4 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 82 of 98
CHANNEL 4 OFFSET MIDDLE BYTE REGISTER Address: 0x035, Reset: 0x00, Name: CH4_OFFSET_MID_BYTE
Combined offset register Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_OFFSET_ALL[15:8] (R/W)
Table 96. Bit Descriptions for CH4_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH4_OFFSET_ALL[15:8] Combined Offset Register Channel 4 0x0 R/W
CHANNEL 4 OFFSET LOWER BYTE REGISTER Address: 0x036, Reset: 0x00, Name: CH4_OFFSET_LOWER_BYTE
Combined offset register Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_OFFSET_ALL[7:0] (R/W)
Table 97. Bit Descriptions for CH4_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH4_OFFSET_ALL[7:0] Combined Offset Register Channel 4 0x0 R/W
CHANNEL 4 GAIN UPPER BYTE REGISTER Address: 0x037, Reset: 0x00, Name: CH4_GAIN_UPPER_BYTE
Combined gain register Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_GAIN_ALL[23:16] (R/W)
Table 98. Bit Descriptions for CH4_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH4_GAIN_ALL[23:16] Combined Gain Register Channel 4 0x0 R/W
CHANNEL 4 GAIN MIDDLE BYTE REGISTER Address: 0x038, Reset: 0x00, Name: CH4_GAIN_MID_BYTE
Combined gain register Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_GAIN_ALL[15:8] (R/W)
Table 99. Bit Descriptions for CH4_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH4_GAIN_ALL[15:8] Combined Gain Register Channel 4 0x0 R/W
CHANNEL 4 GAIN LOWER BYTE REGISTER Address: 0x039, Reset: 0x00, Name: CH4_GAIN_LOWER_BYTE
Combined gain register Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH4_GAIN_ALL[7:0] (R/W)
Table 100. Bit Descriptions for CH4_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH4_GAIN_ALL[7:0] Combined Gain Register Channel 4 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 83 of 98
CHANNEL 5 OFFSET UPPER BYTE REGISTER Address: 0x03A, Reset: 0x00, Name: CH5_OFFSET_UPPER_BYTE
Combined offset register Channel 5
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_OFFSET_ALL[23:16] (R/W)
Table 101. Bit Descriptions for CH5_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH5_OFFSET_ALL[23:16] Combined Offset Register Channel 5 0x0 R/W
CHANNEL 5 OFFSET MIDDLE BYTE REGISTER Address: 0x03B, Reset: 0x00, Name: CH5_OFFSET_MID_BYTE
Combined offset register Channel 5
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_OFFSET_ALL[15:8] (R/W)
Table 102. Bit Descriptions for CH5_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH5_OFFSET_ALL[15:8] Combined Offset Register Channel 5 0x0 R/W
CHANNEL 5 OFFSET LOWER BYTE REGISTER Address: 0x03C, Reset: 0x00, Name: CH5_OFFSET_LOWER_BYTE
Combined offset register Channel 5
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_OFFSET_ALL[7:0] (R/W)
Table 103. Bit Descriptions for CH5_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH5_OFFSET_ALL[7:0] Combined Offset Register Channel 5 0x0 R/W
CHANNEL 5 GAIN UPPER BYTE REGISTER Address: 0x03D, Reset: 0x00, Name: CH5_GAIN_UPPER_BYTE
Combined gain register Channel 5
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_GAIN_ALL[23:16] (R/W)
Table 104. Bit Descriptions for CH5_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH5_GAIN_ALL[23:16] Combined Gain Register Channel 5 0x0 R/W
CHANNEL 5 GAIN MIDDLE BYTE REGISTER Address: 0x03E, Reset: 0x00, Name: CH5_GAIN_MID_BYTE
Combined gain register Channel 5
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_GAIN_ALL[15:8] (R/W)
Table 105. Bit Descriptions for CH5_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH5_GAIN_ALL[15:8] Combined Gain Register Channel 5 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 84 of 98
CHANNEL 5 GAIN LOWER BYTE REGISTER Address: 0x03F, Reset: 0x00, Name: CH5_GAIN_LOWER_BYTE
Combined gain register Channel 5
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH5_GAIN_ALL[7:0] (R/W)
Table 106. Bit Descriptions for CH5_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH5_GAIN_ALL[7:0] Combined Gain Register Channel 5 0x0 R/W
CHANNEL 6 OFFSET UPPER BYTE REGISTER Address: 0x040, Reset: 0x00, Name: CH6_OFFSET_UPPER_BYTE
Combined offset register Channel 6
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_OFFSET_ALL[23:16] (R/W)
Table 107. Bit Descriptions for CH6_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_OFFSET_ALL[23:16] Combined Offset Register Channel 6 0x0 R/W
CHANNEL 6 OFFSET MIDDLE BYTE REGISTER Address: 0x041, Reset: 0x00, Name: CH6_OFFSET_MID_BYTE
Combined offset register Channel 6
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_OFFSET_ALL[15:8] (R/W)
Table 108. Bit Descriptions for CH6_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_OFFSET_ALL[15:8] Combined Offset Register Channel 6 0x0 R/W
CHANNEL 6 OFFSET LOWER BYTE REGISTER Address: 0x042, Reset: 0x00, Name: CH6_OFFSET_LOWER_BYTE
Combined offset register Channel 6
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_OFFSET_ALL[7:0] (R/W)
Table 109. Bit Descriptions for CH6_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_OFFSET_ALL[7:0] Combined Offset Register Channel 6 0x0 R/W
CHANNEL 6 GAIN UPPER BYTE REGISTER Address: 0x043, Reset: 0x00, Name: CH6_GAIN_UPPER_BYTE
Combined gain register Channel 6
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_GAIN_ALL[23:16] (R/W)
Table 110. Bit Descriptions for CH6_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_GAIN_ALL[23:16] Combined Gain Register Channel 6 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 85 of 98
CHANNEL 6 GAIN MIDDLE BYTE REGISTER Address: 0x044, Reset: 0x00, Name: CH6_GAIN_MID_BYTE
Combined gain register Channel 6
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_GAIN_ALL[15:8] (R/W)
Table 111. Bit Descriptions for CH6_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_GAIN_ALL[15:8] Combined Gain Register Channel 6 0x0 R/W
CHANNEL 6 GAIN LOWER BYTE REGISTER Address: 0x045, Reset: 0x00, Name: CH6_GAIN_LOWER_BYTE
Combined gain register Channel 6
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH6_GAIN_ALL[7:0] (R/W)
Table 112. Bit Descriptions for CH6_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_GAIN_ALL[7:0] Combined Gain Register Channel 6 0x0 R/W
CHANNEL 7 OFFSET UPPER BYTE REGISTER Address: 0x046, Reset: 0x00, Name: CH7_OFFSET_UPPER_BYTE
Combined offset register Channel 7
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_OFFSET_ALL[23:16] (R/W)
Table 113. Bit Descriptions for CH7_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_OFFSET_ALL[23:16] Combined Offset Register Channel 7 0x0 R/W
CHANNEL 7 OFFSET MIDDLE BYTE REGISTER Address: 0x047, Reset: 0x00, Name: CH7_OFFSET_MID_BYTE
Combined offset register Channel 7
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_OFFSET_ALL[15:8] (R/W)
Table 114. Bit Descriptions for CH7_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_OFFSET_ALL[15:8] Combined Offset Register Channel 7 0x0 R/W
CHANNEL 7 OFFSET LOWER BYTE REGISTER Address: 0x048, Reset: 0x00, Name: CH7_OFFSET_LOWER_BYTE
Combined offset register Channel 7
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_OFFSET_ALL[7:0] (R/W)
Table 115. Bit Descriptions for CH7_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_OFFSET_ALL[7:0] Combined Offset Register Channel 7 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 86 of 98
CHANNEL 7 GAIN UPPER BYTE REGISTER Address: 0x049, Reset: 0x00, Name: CH7_GAIN_UPPER_BYTE
Combined gain register Channel 7
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_GAIN_ALL[23:16] (R/W)
Table 116. Bit Descriptions for CH7_GAIN_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_GAIN_ALL[23:16] Combined Gain Register Channel 7 0x0 R/W
CHANNEL 7 GAIN MIDDLE BYTE REGISTER Address: 0x04A, Reset: 0x00, Name: CH7_GAIN_MID_BYTE
Combined gain register Channel 7
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_GAIN_ALL[15:8] (R/W)
Table 117. Bit Descriptions for CH7_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_GAIN_ALL[15:8] Combined Gain Register Channel 7 0x0 R/W
CHANNEL 7 GAIN LOWER BYTE REGISTER Address: 0x04B, Reset: 0x00, Name: CH7_GAIN_LOWER_BYTE
Combined gain register Channel 7
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] CH7_GAIN_ALL[7:0] (R/W)
Table 118. Bit Descriptions for CH7_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_GAIN_ALL[7:0] Combined Gain Register Channel 7 0x0 R/W
CHANNEL 0 STATUS REGISTER Address: 0x04C, Reset: 0x00, Name: CH0_ERR_REG
Channel 0 - Reference detect error
AIN0- undervoltage errorAIN0+ overvoltage error
AIN0- overvoltage errorAIN0+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH0_ERR_REF_DET (R)
[4] CH0_ERR_AINM_UV (R)[1] CH0_ERR_AINP_OV (R)
[3] CH0_ERR_AINM_OV (R)[2] CH0_ERR_AINP_UV (R)
Table 119. Bit Descriptions for CH0_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH0_ERR_AINM_UV Channel 0—AIN0− Undervoltage Error 0x0 R 3 CH0_ERR_AINM_OV Channel 0—AIN0− Overvoltage Error 0x0 R 2 CH0_ERR_AINP_UV Channel 0—AIN0+ Undervoltage Error 0x0 R 1 CH0_ERR_AINP_OV Channel 0—AIN0+ Overvoltage Error 0x0 R 0 CH0_ERR_REF_DET Channel 0—Reference Detect Error 0x0 R
Data Sheet AD7771
Rev. 0 | Page 87 of 98
CHANNEL 1 STATUS REGISTER Address: 0x04D, Reset: 0x00, Name: CH1_ERR_REG
Channel 1 - Reference detect error
AIN1- undervoltage errorAIN1+ overvoltage error
AIN1- overvoltage errorAIN1+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH1_ERR_REF_DET (R)
[4] CH1_ERR_AINM_UV (R)[1] CH1_ERR_AINP_OV (R)
[3] CH1_ERR_AINM_OV (R)[2] CH1_ERR_AINP_UV (R)
Table 120. Bit Descriptions for CH1_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH1_ERR_AINM_UV Channel 1—AIN1− Undervoltage Error 0x0 R 3 CH1_ERR_AINM_OV Channel 1—AIN1− Overvoltage Error 0x0 R 2 CH1_ERR_AINP_UV Channel 1—AIN1+ Undervoltage Error 0x0 R 1 CH1_ERR_AINP_OV Channel 1—AIN1+ Overvoltage Error 0x0 R 0 CH1_ERR_REF_DET Channel 1—Reference Detect Error 0x0 R
CHANNEL 2 STATUS REGISTER Address: 0x04E, Reset: 0x00, Name: CH2_ERR_REG
Channel 2 - Reference detect error
AIN2- undervoltage errorAIN2+ overvoltage error
AIN2- overvoltage errorAIN2+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH2_ERR_REF_DET (R)
[4] CH2_ERR_AINM_UV (R)[1] CH2_ERR_AINP_OV (R)
[3] CH2_ERR_AINM_OV (R)[2] CH2_ERR_AINP_UV (R)
Table 121. Bit Descriptions for CH2_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH2_ERR_AINM_UV Channel 2—AIN2− Undervoltage Error 0x0 R 3 CH2_ERR_AINM_OV Channel 2—AIN2− Overvoltage Error 0x0 R 2 CH2_ERR_AINP_UV Channel 2—AIN2+ Undervoltage Error 0x0 R 1 CH2_ERR_AINP_OV Channel 2—AIN2+ Overvoltage Error 0x0 R 0 CH2_ERR_REF_DET Channel 2—Reference Detect Error 0x0 R
AD7771 Data Sheet
Rev. 0 | Page 88 of 98
CHANNEL 3 STATUS REGISTER Address: 0x04F, Reset: 0x00, Name: CH3_ERR_REG
Channel 3 - Reference detect error
AIN3- undervoltage errorAIN3+ overvoltage error
AIN3- overvoltage errorAIN3+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH3_ERR_REF_DET (R)
[4] CH3_ERR_AINM_UV (R)[1] CH3_ERR_AINP_OV (R)
[3] CH3_ERR_AINM_OV (R)[2] CH3_ERR_AINP_UV (R)
Table 122. Bit Descriptions for CH3_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH3_ERR_AINM_UV Channel 3—AIN3− Undervoltage Error 0x0 R 3 CH3_ERR_AINM_OV Channel 3—AIN3− Overvoltage Error 0x0 R 2 CH3_ERR_AINP_UV Channel 3—AIN3+ Undervoltage Error 0x0 R 1 CH3_ERR_AINP_OV Channel 3—AIN3+ Overvoltage Error 0x0 R 0 CH3_ERR_REF_DET Channel 3—Reference Detect Error 0x0 R
CHANNEL 4 STATUS REGISTER Address: 0x050, Reset: 0x00, Name: CH4_ERR_REG
Channel 4 - Reference detect error
AIN4- undervoltage errorAIN4+ overvoltage error
AIN4- overvoltage errorAIN4+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH4_ERR_REF_DET (R)
[4] CH4_ERR_AINM_UV (R)[1] CH4_ERR_AINP_OV (R)
[3] CH4_ERR_AINM_OV (R)[2] CH4_ERR_AINP_UV (R)
Table 123. Bit Descriptions for CH4_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH4_ERR_AINM_UV Channel 4—AIN4− Undervoltage Error 0x0 R 3 CH4_ERR_AINM_OV Channel 4—AIN4− Overvoltage Error 0x0 R 2 CH4_ERR_AINP_UV Channel 4—AIN4+ Undervoltage Error 0x0 R 1 CH4_ERR_AINP_OV Channel 4—AIN4+ Overvoltage Error 0x0 R 0 CH4_ERR_REF_DET Channel 4—Reference Detect Error 0x0 R
Data Sheet AD7771
Rev. 0 | Page 89 of 98
CHANNEL 5 STATUS REGISTER Address: 0x051, Reset: 0x00, Name: CH5_ERR_REG
Channel 5 - Reference detect error
AIN5- undervoltage errorAIN5+ overvoltage error
AIN5- overvoltage errorAIN5+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH5_ERR_REF_DET (R)
[4] CH5_ERR_AINM_UV (R)[1] CH5_ERR_AINP_OV (R)
[3] CH5_ERR_AINM_OV (R)[2] CH5_ERR_AINP_UV (R)
Table 124. Bit Descriptions for CH5_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH5_ERR_AINM_UV Channel 5—AIN5− Undervoltage Error 0x0 R 3 CH5_ERR_AINM_OV Channel 5—AIN5− Overvoltage Error 0x0 R 2 CH5_ERR_AINP_UV Channel 5—AIN5+ Undervoltage Error 0x0 R 1 CH5_ERR_AINP_OV Channel 5—AIN5+ Overvoltage Error 0x0 R 0 CH5_ERR_REF_DET Channel 5—Reference Detect Error 0x0 R
CHANNEL 6 STATUS REGISTER Address: 0x052, Reset: 0x00, Name: CH6_ERR_REG
Channel 6 - Reference detect error
AIN6- undervoltage errorAIN6+ overvoltage error
AIN6- overvoltage errorAIN6+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH6_ERR_REF_DET (R)
[4] CH6_ERR_AINM_UV (R)[1] CH6_ERR_AINP_OV (R)
[3] CH6_ERR_AINM_OV (R)[2] CH6_ERR_AINP_UV (R)
Table 125. Bit Descriptions for CH6_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R/W 4 CH6_ERR_AINM_UV Channel 6—AIN6− Undervoltage Error 0x0 R 3 CH6_ERR_AINM_OV Channel 6—AIN6− Overvoltage Error 0x0 R 2 CH6_ERR_AINP_UV Channel 6—AIN6+ Undervoltage Error 0x0 R 1 CH6_ERR_AINP_OV Channel 6—AIN6+ Overvoltage Error 0x0 R 0 CH6_ERR_REF_DET Channel 6—Reference Detect Error 0x0 R
AD7771 Data Sheet
Rev. 0 | Page 90 of 98
CHANNEL 7 STATUS REGISTER Address: 0x053, Reset: 0x00, Name: CH7_ERR_REG
Channel 7 - Reference detect error
AIN7- undervoltage errorAIN7+ overvoltage error
AIN7- overvoltage errorAIN7+ undervoltage error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [0] CH7_ERR_REF_DET (R)
[4] CH7_ERR_AINM_UV (R)[1] CH7_ERR_AINP_OV (R)
[3] CH7_ERR_AINM_OV (R)[2] CH7_ERR_AINP_UV (R)
Table 126. Bit Descriptions for CH7_ERR_REG Bits Bit Name Settings Description Reset Access [7:5] RESERVED Reserved 0x0 R 4 CH7_ERR_AINM_UV Channel 7—AIN7− Undervoltage Error 0x0 R 3 CH7_ERR_AINM_OV Channel 7—AIN7− Overvoltage Error 0x0 R 2 CH7_ERR_AINP_UV Channel 7—AIN7+ Undervoltage Error 0x0 R 1 CH7_ERR_AINP_OV Channel 7—AIN7+ Overvoltage Error 0x0 R 0 CH7_ERR_REF_DET Channel 7—Reference Detect Error 0x0 R
CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER Address: 0x054, Reset: 0x00, Name: CH0_1_SAT_ERR
Channel 0 - ADC conversion hasexceeded limits and has been clamped
Channel 1 - Modulator output saturationerror
Channel 0 - Filter result has exceededa reasonable level, before offset andgain calibration has been applied.Channel 1 - Filter result has exceeded
a reasonable level, before offset andgain calibration has been applied.
Channel 0 - Modulator output saturationerror
Channel 1 - ADC conversion hasexceeded limits and has been clamped
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] CH0_ERR_OUTPUT_SAT (R)
[5] CH1_ERR_MOD_SAT (R)
[1] CH0_ERR_FILTER_SAT (R)
[4] CH1_ERR_FILTER_SAT (R)
[2] CH0_ERR_MOD_SAT (R)
[3] CH1_ERR_OUTPUT_SAT (R)
Table 127. Bit Descriptions for CH0_1_SAT_ERR Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CH1_ERR_MOD_SAT Channel 1—Modulator output saturation error 0x0 R 4 CH1_ERR_FILTER_SAT Channel 1—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
3 CH1_ERR_OUTPUT_SAT Channel 1—ADC conversion has exceeded limits and is clamped 0x0 R 2 CH0_ERR_MOD_SAT Channel 0—Modulator output saturation error 0x0 R 1 CH0_ERR_FILTER_SAT Channel 0—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
0 CH0_ERR_OUTPUT_SAT Channel 0—ADC conversion has exceeded limits and is clamped 0x0 R
Data Sheet AD7771
Rev. 0 | Page 91 of 98
CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER Address: 0x055, Reset: 0x00, Name: CH2_3_SAT_ERR
Channel 2 - ADC conversion hasexceeded limits and has been clamped
Channel 3 - Modulator output saturationerror
Channel 2 - Filter result has exceededa reasonable level, before offset andgain calibration has been applied.Channel 3 - Filter result has exceeded
a reasonable level, before offset andgain calibration has been applied.
Channel 2 - Modulator output saturationerror
Channel 3 - ADC conversion hasexceeded limits and has been clamped
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] CH2_ERR_OUTPUT_SAT (R)
[5] CH3_ERR_MOD_SAT (R)
[1] CH2_ERR_FILTER_SAT (R)
[4] CH3_ERR_FILTER_SAT (R)
[2] CH2_ERR_MOD_SAT (R)
[3] CH3_ERR_OUTPUT_SAT (R)
Table 128. Bit Descriptions for CH2_3_SAT_ERR Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CH3_ERR_MOD_SAT Channel 3—Modulator output saturation error 0x0 R 4 CH3_ERR_FILTER_SAT Channel 3—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
3 CH3_ERR_OUTPUT_SAT Channel 3—ADC conversion has exceeded limits and is clamped 0x0 R 2 CH2_ERR_MOD_SAT Channel 2—Modulator output saturation error 0x0 R 1 CH2_ERR_FILTER_SAT Channel 2—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
0 CH2_ERR_OUTPUT_SAT Channel 2—ADC conversion has exceeded limits and has been clamped 0x0 R
CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER Address: 0x056, Reset: 0x00, Name: CH4_5_SAT_ERR
Channel 4 - ADC conversion hasexceeded limits and has been clamped
Channel 5 - Modulator output saturationerror
Channel 4 - Filter result has exceededa reasonable level, before offset andgain calibration has been applied.Channel 5 - Filter result has exceeded
a reasonable level, before offset andgain calibration has been applied.
Channel 4 - Modulator output saturationerror
Channel 5 - ADC conversion hasexceeded limits and has been clamped
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] CH4_ERR_OUTPUT_SAT (R)
[5] CH5_ERR_MOD_SAT (R)
[1] CH4_ERR_FILTER_SAT (R)
[4] CH5_ERR_FILTER_SAT (R)
[2] CH4_ERR_MOD_SAT (R)
[3] CH5_ERR_OUTPUT_SAT (R)
Table 129. Bit Descriptions for CH4_5_SAT_ERR Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CH5_ERR_MOD_SAT Channel 5—Modulator output saturation error 0x0 R 4 CH5_ERR_FILTER_SAT Channel 5—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
3 CH5_ERR_OUTPUT_SAT Channel 5—ADC conversion has exceeded limits and is clamped 0x0 R 2 CH4_ERR_MOD_SAT Channel 4—Modulator output saturation error 0x0 R 1 CH4_ERR_FILTER_SAT Channel 4—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
0 CH4_ERR_OUTPUT_SAT Channel 4—ADC conversion has exceeded limits and is clamped 0x0 R
AD7771 Data Sheet
Rev. 0 | Page 92 of 98
CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER Address: 0x057, Reset: 0x00, Name: CH6_7_SAT_ERR
Channel 6 - ADC conversion hasexceeded limits and has been clamped
Channel 7 - Modulator output saturationerror
Channel 6 - Filter result has exceededa reasonable level, before offset andgain calibration has been applied.Channel 7 - Filter result has exceeded
a reasonable level, before offset andgain calibration has been applied.
Channel 6 - Modulator output saturationerror
Channel 7 - ADC conversion hasexceeded limits and has been clamped
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] CH6_ERR_OUTPUT_SAT (R)
[5] CH7_ERR_MOD_SAT (R)
[1] CH6_ERR_FILTER_SAT (R)
[4] CH7_ERR_FILTER_SAT (R)
[2] CH6_ERR_MOD_SAT (R)
[3] CH7_ERR_OUTPUT_SAT (R)
Table 130. Bit descriptions for CH6_7_SAT_ERR Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CH7_ERR_MOD_SAT Channel 7—Modulator output saturation error 0x0 R 4 CH7_ERR_FILTER_SAT Channel 7—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
3 CH7_ERR_OUTPUT_SAT Channel 7—ADC conversion has exceeded limits and is clamped 0x0 R 2 CH6_ERR_MOD_SAT Channel 6—Modulator output saturation error 0x0 R 1 CH6_ERR_FILTER_SAT Channel 6—Filter result has exceeded a reasonable level, before offset and
gain calibration are applied 0x0 R
0 CH6_ERR_OUTPUT_SAT Channel 6—ADC conversion has exceeded limits and is clamped 0x0 R
CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER Address: 0x058, Reset: 0xFE, Name: CHX_ERR_REG_EN
ADC conversion error test enable Reference detect test enable
Filter saturation error test enable AINx+ overvoltage test enable
Enable error flag for Modulator saturation AINx+ undervoltage test enable
AINx- undervoltage test enable AINx- overvoltage test enable
0
0
1
1
2
1
3
1
4
1
5
1
6
1
7
1
[7] OUTPUT_SAT_TEST_EN (R/W) [0] REF_DET_TEST_EN (R/W)
[6] FILTER_SAT_TEST_EN (R/W) [1] AINP_OV_TEST_EN (R/W)
[5] MOD_SAT_TEST_EN (R/W) [2] AINP_UV_TEST_EN (R/W)
[4] AINM_UV_TEST_EN (R/W) [3] AINM_OV_TEST_EN (R/W)
Table 131. Bit Descriptions for CHX_ERR_REG_EN Bits Bit Name Settings Description Reset Access 7 OUTPUT_SAT_TEST_EN ADC Conversion Error Test Enable 0x1 R/W 6 FILTER_SAT_TEST_EN Filter Saturation Test Enable 0x1 R/W 5 MOD_SAT_TEST_EN Enable Error Flag for Modulator Saturation 0x1 R/W 4 AINM_UV_TEST_EN AINx− Undervoltage Test Enable 0x1 R/W 3 AINM_OV_TEST_EN AINx− Overvoltage Test Enable 0x1 R/W 2 AINP_UV_TEST_EN AINx+ Undervoltage Test Enable 0x1 R/W 1 AINP_OV_TEST_EN AINx+ Overvoltage Test Enable 0x1 R/W 0 REF_DET_TEST_EN Reference Detect Test Enable 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 93 of 98
GENERAL ERRORS REGISTER 1 Address: 0x059, Reset: 0x00, Name: GEN_ERR_REG_1
SPI CRC error
A CRC of the memory map contentsis run periodically to check for errors SPI invalid write address
A CRC of the fuse contents is runperiodically to check for errors inthe fuses
SPI invalid read address
SPI clock counter error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] SPI_CRC_ERR (R)
[5] MEMMAP_CRC_ERR (R)[1] SPI_INVALID_WRITE_ERR (R)
[4] ROM_CRC_ERR (R) [2] SPI_INVALID_READ_ERR (R)
[3] SPI_CLK_COUNT_ERR (R)
Table 132. Bit Descriptions for GEN_ERR_REG_1 Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 MEMMAP_CRC_ERR A CRC of the memory map contents is run periodically to check for errors 0x0 R 4 ROM_CRC_ERR A CRC of the fuse contents is run periodically to check for errors in the fuses 0x0 R 3 SPI_CLK_COUNT_ERR SPI clock counter error 0x0 R 2 SPI_INVALID_READ_ERR SPI invalid read address 0x0 R 1 SPI_INVALID_WRITE_ERR SPI invalid write address 0x0 R 0 SPI_CRC_ERR SPI CRC error 0x0 R
GENERAL ERRORS REGISTER 1 ENABLE Address: 0x05A, Reset: 0x3E, Name: GEN_ERR_REG_1_EN
Table 133. Bit Descriptions for GEN_ERR_REG_1_EN Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 MEMMAP_CRC_TEST_EN Memory Map CRC Test Error Enable 0x1 R/W 4 ROM_CRC_TEST_EN Fuse CRC Test Enable 0x1 R/W 3 SPI_CLK_COUNT_TEST_EN SPI Clock Counter Test Enable 0x1 R/W 2 SPI_INVALID_READ_TEST_EN SPI Invalid Read Address Test Enable 0x1 R/W 1 SPI_INVALID_WRITE_TEST_EN SPI Invalid Write Address Test Enable 0x1 R/W 0 SPI_CRC_TEST_EN SPI CRC Error Test Enable 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 94 of 98
GENERAL ERRORS REGISTER 2 Address: 0x05B, Reset: 0x00, Name: GEN_ERR_REG_2
DRegCap power supply error
Reset detectedAReg2Cap power supply error
Clock not switched overAReg1Cap power supply error
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] DLDO_PSM_ERR (R)
[5] RESET_DETECTED (R)[1] ALDO2_PSM_ERR (R)
[4] EXT_MCLK_SWITCH_ERR (R)[2] ALDO1_PSM_ERR (R)
[3] RESERVED
Table 134. Bit Descriptions for GEN_ERR_REG_2 Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 RESET_DETECTED Reset Detected 0x0 R 4 EXT_MCLK_SWITCH_ERR Clock Not Switched Over 0x0 R 3 RESERVED Reserved 0x0 R 2 ALDO1_PSM_ERR AREG1CAP Power Supply Error 0x0 R 1 ALDO2_PSM_ERR AREG2CAP Power Supply Error 0x0 R 0 DLDO_PSM_ERR DREGCAP Power Supply Error 0x0 R
GENERAL ERRORS REGISTER 2 ENABLE Address: 0x05C, Reset: 0x3C, Name: GEN_ERR_REG_2_EN
LDO PSM trip test enable
11: 11 - Run trip detect test on DRegCap.10: 10 - Run trip detect test on AReg2Cap.
1: 01 - Run trip detect test on AReg1Cap.0: 00 - No trip detect test enabled.
Reset detect enable
LDO PSM test EN
11:on all LDOs.11 - Run power supply monitor test
10:on DRegCap.10 - Run power supply monitor test
1:on ARegxCap.01 - Run power supply monitor test
0:enabled.00 - No power supply monitor test
0
0
1
0
2
1
3
1
4
0
5
1
6
0
7
0
[7:6] RESERVED [1:0] LDO_PSM_TRIP_TEST_EN (R/W)
[5] RESET_DETECT_EN (R/W)
[3:2] LDO_PSM_test_EN (R/W)
[4] RESERVED
Table 135. Bit Descriptions for GEN_ERR_REG_2_EN Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 RESET_DETECT_EN Reset Detect Enable 0x1 R/W 4 RESERVED Reserved 0x1 R/W [3:2] LDO_PSM_TEST_EN LDO PSM Test Enable 0x3 R/W 0 00—No power supply monitor test enabled 1 01—Run power supply monitor test on AREGxCAP 10 10—Run power supply monitor test on DREGCAP 11 11—Run power supply monitor test on all LDOs [1:0] LDO_PSM_TRIP_TEST_EN LDO PSM Trip Test Enable 0x0 R/W 0 00—No trip detect test enabled 1 01—Run trip detect test on AREG1CAP 10 10—Run trip detect test on AREG2CAP 11 11—Run trip detect test on DREGCAP
Data Sheet AD7771
Rev. 0 | Page 95 of 98
ERROR STATUS REGISTER 1 Address: 0x05D, Reset: 0x00, Name: STATUS_REG_1
An error specific to CH0_ERR_REGis active
Set high if any error bit is high
An error specific to CH1_ERR_REGis activeAn error specific to CH4_ERR_REG
is active
An error specific to CH2_ERR_REGis activeAn error specific to CH3_ERR_REG
is active
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] ERR_LOC_CH0 (R)
[5] CHIP_ERROR (R)
[1] ERR_LOC_CH1 (R)[4] ERR_LOC_CH4 (R)
[2] ERR_LOC_CH2 (R)[3] ERR_LOC_CH3 (R)
Table 136. Bit Descriptions for STATUS_REG_1 Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CHIP_ERROR Set this bit high if any error bit is high 0x0 R 4 ERR_LOC_CH4 An error specific to CH4_ERR_REG is active 0x0 R 3 ERR_LOC_CH3 An error specific to CH3_ERR_REG is active 0x0 R 2 ERR_LOC_CH2 An error specific to CH2_ERR_REG is active 0x0 R 1 ERR_LOC_CH1 An error specific to CH1_ERR_REG is active 0x0 R 0 ERR_LOC_CH0 An error specific to CH0_ERR_REG is active 0x0 R
ERROR STATUS REGISTER 2 Address: 0x05E, Reset: 0x00, Name: STATUS_REG_2
An error specific to CH5_ERR_REGis active
Set high if any error bit is high
An error specific to CH6_ERR_REGis activeAn error specific to GEN_ERR_REG_2
is active
An error specific to CH7_ERR_REGis activeAn error specific to GEN_ERR_REG_1
is active
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] ERR_LOC_CH5 (R)
[5] CHIP_ERROR (R)
[1] ERR_LOC_CH6 (R)[4] ERR_LOC_GEN2 (R)
[2] ERR_LOC_CH7 (R)[3] ERR_LOC_GEN1 (R)
Table 137. Bit Descriptions for STATUS_REG_2 Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CHIP_ERROR Set high if any error bit is high 0x0 R 4 ERR_LOC_GEN2 An error specific to GEN_ERR_REG_2 is active 0x0 R 3 ERR_LOC_GEN1 An error specific to GEN_ERR_REG_1 is active 0x0 R 2 ERR_LOC_CH7 An error specific to CH7_ERR_REG is active 0x0 R 1 ERR_LOC_CH6 An error specific to CH6_ERR_REG is active 0x0 R 0 ERR_LOC_CH5 An error specific to CH5_ERR_REG is active 0x0 R
AD7771 Data Sheet
Rev. 0 | Page 96 of 98
ERROR STATUS REGISTER 3 Address: 0x05F, Reset: 0x00, Name: STATUS_REG_3
An error specific to CH0_1_SAT_ERRreg is active
Set high if any error bit is high
An error specific to CH2_3_SAT_ERRreg is activeFuse initialization is complete. Device
is ready to receive commands
An error specific to CH4_5_SAT_ERRreg is activeAn error specific to CH6_7_SAT_ERR
reg is active
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] ERR_LOC_SAT_CH0_1 (R)
[5] CHIP_ERROR (R)
[1] ERR_LOC_SAT_CH2_3 (R)[4] INIT_COMPLETE (R)
[2] ERR_LOC_SAT_CH4_5 (R)[3] ERR_LOC_SAT_CH6_7 (R)
Table 138. Bit Descriptions for STATUS_REG_3 Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved 0x0 R 5 CHIP_ERROR Set high if any error bit is high. 0x0 R 4 INIT_COMPLETE Fuse initialization is complete. Device is ready to receive commands. 0x0 R 3 ERR_LOC_SAT_CH6_7 An error specific to CH6_7_SAT_ERR register is active. 0x0 R 2 ERR_LOC_SAT_CH4_5 An error specific to CH4_5_SAT_ERR register is active. 0x0 R 1 ERR_LOC_SAT_CH2_3 An error specific to CH2_3_SAT_ERR register is active. 0x0 R 0 ERR_LOC_SAT_CH0_1 An error specific to CH0_1_SAT_ERR register is active. 0x0 R
DECIMATION RATE (N) MSB REGISTER Address: 0x060, Reset: 0x00, Name: SRC_N_MSB
SRC N Combined
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:4] RESERVED [3:0] SRC_N_ALL[11:8] (R/W)
Table 139. Bit Descriptions for SRC_N_MSB Bits Bit Name Settings Description Reset Access [7:4] RESERVED Reserved 0x0 R [3:0] SRC_N_ALL[11:8] SRC N Combined 0x0 R/W
DECIMATION RATE (N) LSB REGISTER Address: 0x061, Reset: 0x80, Name: SRC_N_LSB
SRC N Combined
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] SRC_N_ALL[7:0] (R/W)
Table 140. Bit Descriptions for SRC_N_LSB Bits Bit Name Settings Description Reset Access [7:0] SRC_N_ALL[7:0] SRC N Combined 0x0 R/W
DECIMATION RATE (IF) MSB REGISTER Address: 0x062, Reset: 0x00, Name: SRC_IF_MSB
SRC IF ALL
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] SRC_IF_ALL[15:8] (R/W)
Table 141. Bit Descriptions for SRC_IF_MSB Bits Bit Name Settings Description Reset Access [7:0] SRC_IF_ALL[15:8] SRC IF All 0x0 R/W
Data Sheet AD7771
Rev. 0 | Page 97 of 98
DECIMATION RATE (IF) LSB REGISTER Address: 0x063, Reset: 0x00, Name: SRC_IF_LSB
SRC IF ALL
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:0] SRC_IF_ALL[7:0] (R/W)
Table 142. Bit Descriptions for SRC_IF_LSB Bits Bit Name Settings Description Reset Access [7:0] SRC_IF_ALL[7:0] SRC IF All 0x0 R/W
SRC LOAD SOURCE AND LOAD UPDATE REGISTER Address: 0x064, Reset: 0x00, Name: SRC_UPDATE
Select which option to load an SRCupdate
Assert bit to load SRC registers intoSRC
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] SRC_LOAD_SOURCE (R/W) [0] SRC_LOAD_UPDATE (R/W)
[6:1] RESERVED
Table 143. Bit Descriptions for SRC_UPDATE Bits Bit Name Settings Description Reset Access 7 SRC_LOAD_SOURCE Selects which option to load an SRC update 0x0 R/W [6:1] RESERVED Reserved 0x0 R 0 SRC_LOAD_UPDATE Asserts bit to load SRC registers into SRC 0x0 R/W
AD7771 Data Sheet
Rev. 0 | Page 98 of 98
OUTLINE DIMENSIONS
0.50BSC
BOTTOM VIEWTOP VIEW
PIN 1INDICATOR
EXPOSEDPAD
PIN 1INDICATOR
7.707.60 SQ7.50
0.450.400.35
SEATINGPLANE
0.800.750.70
0.05 MAX0.02 NOM
0.203 REF
COPLANARITY0.08
0.300.250.18
02-
12-2
014
-A
9.109.00 SQ8.90
0.20 MIN
7.50 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
164
16
17
49
48
32
33
PK
G-0
04
39
6
Figure 139. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm × 9 mm Body and 0.75 mm Package Height (CP-64-15)
Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD7771BCPZ −40°C to +125°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-15 AD7771BCPZ-RL −40°C to +125°C 64-Lead Lead Frame Chip Scale Package [LFCSP] CP-64-15 EVAL-AD7771FMCZ Evaluation Board 1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13802-0-6/17(0)