A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
J. Pallarès1, F. Vila1, S. Sutula1, K. Sabine2,
L. Terés1,3 and F. Serra-Graells1,3
1Institut de Microelectrònica de Barcelona, IMB-CNM(CSIC)
2Peardrop Design Systems Ltd
3Dept. of Microelectronics and Electronic Systems
Universitat Autònoma de Barcelona
Nov 2014
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
1 Introduction
2 Schematic Entry
3 Mixed-Mode HDL Simulation
4 Automatic Circuit Optimization
5 Full-Custom Layout Design and Verification
6 Conclusions
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Motivation and Objectives
Problems teaching VLSI design at lab: EDA environment proposal for
mixed-mode full-custom ASIC design:
Freeware, available for
PDK development
Intro Schem Mixed-Sim Optim Layout Conclusions
Professional EDA tools costs
(licenses, hardware, administration)
Technology confidentiality
Limited lab session time
gaf (gschem and friends) for schematic edition and netlisting
SpiceOpus (SPICE with integrated optimization utilities) for analog-digital & HDL-electrical simulation
Glade (GDS, LEF and DEF editor) for layout design and verification
XSpice
Scheme
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Case Study
14bit 8kHz 2Vdp A/D ΔΣM design
Intro Schem Mixed-Sim Optim Layout Conclusions
Mixed analog-digital signal domains
HDL modeling required due to oversampling Reduced DRC rule set
Simple device modeling
Easy PDK development
Students easily get familiar with
2P2M 2.5µm CMOS (CNM25) target technology
…but it can be extended to modern CMOS technologies as well.
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
1 Introduction
2 Schematic Entry
3 Mixed-Mode HDL Simulation
4 Automatic Circuit Optimization
5 Full-Custom Layout Design and Verification
6 Conclusions
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Schematic Entry
Intro Schem Mixed-Sim Optim Layout Conclusions
gnetlist allows programmable netlisting rules for both native SPICE devices and custom XSpice code models
e.g. ΔΣM differential architecture
gschem features customizable symbols, library browsing, net and pin labeling, hierarchical navigation, instance annotation and automatic rewiring...
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
1 Introduction
2 Schematic Entry
3 Mixed-Mode HDL Simulation
4 Automatic Circuit Optimization
5 Full-Custom Layout Design and Verification
6 Conclusions
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Architecture HDL Simulation
Intro Schem Mixed-Sim Optim Layout Conclusions
e.g. Z-domain integrator with built-in limiter XSpice code model (CM)
Students can code in C their own mixed-mode XSpice HDL models
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Architecture HDL Simulation
Students can code in C their own mixed-mode XSpice HDL models
SPICE3 Nutmeg scripting allows to manage several circuits and analysis at the same time
Auxiliary external programs may be also combined…
Intro Schem Mixed-Sim Optim Layout Conclusions
e.g. ΔΣM PSD
e.g. ΔΣM SNDR
e.g. ΔΣM coefficients mismatching study
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Block HDL Specification
XSpice modeling of circuit non-idealities and system re-simulation
Intro Schem Mixed-Sim Optim Layout Conclusions
G=80dB SR=20V/µs GBW=40MHz
G=60dB SR=8V/µs GBW=20MHz
e.g. OpAmp specification study
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
1 Introduction
2 Schematic Entry
3 Mixed-Mode HDL Simulation
4 Automatic Circuit Optimization
5 Full-Custom Layout Design and Verification
6 Conclusions
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Automatic Circuit Optimization
Routine scripting:
Intro Schem Mixed-Sim Optim Layout Conclusions
e.g. OpAmp optimization
Design parameters
Figures-of-merit (FOMs)
Implicit rules for discarding solutions
Cost function to score candidates
Optimization algorithm selection
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Automatic Circuit Optimization
Routine scripting:
Intro Schem Mixed-Sim Optim Layout Conclusions
Design parameters
Figures-of-merit (FOMs)
Implicit rules for discarding solutions
Cost function to score candidates
Optimization algorithm selection
Students can customize all steps and review results:
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
1 Introduction
2 Schematic Entry
3 Mixed-Mode HDL Simulation
4 Automatic Circuit Optimization
5 Full-Custom Layout Design and Verification
6 Conclusions
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
PCell-Based Layout Design
Fully featured full-custom layout editor
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
PCell-Based Layout Design
Fully featured full-custom layout editor
Parameterized cells (PCells) developed in Python
Intro Schem Mixed-Sim Optim Layout Conclusions
e.g. CNM25 NMOSFET PCell
e.g. CNM25 PiP capacitor PCell
Students can design analog layout faster while still preserving matching rules
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Design Rule Checker
User friendly interface for debugging DRC errors
Design rules set entirely scripted in Python
Students can learn how a DRC is programmed (boolean operations, derived
layers, geometrical concepts)
Intro Schem Mixed-Sim Optim Layout Conclusions
boolean operations
derived layers
e.g. CNM25 DRC script
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
LVS and Parasitics Extraction
User friendly interface for debugging ERC errors
Extraction rules set entirely scripted in Python
Intro Schem Mixed-Sim Optim Layout Conclusions
e.g. CNM25 extraction script
e.g. OpAmp layout extraction
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
LVS and Parasitics Extraction
User friendly interface for debugging ERC errors
Extraction rules set entirely scripted in Python
Gemini-based layout versus schematic (LVS)
Extraction of SPICE netlists with parasitic capacitors for post-layout simulation
Intro Schem Mixed-Sim Optim Layout Conclusions
e.g. OpAmp extracted netlist
e.g. OpAmp with LVS errors
Students can debug circuit connectivity or device size matching errors in the same environment
Students can evaluate losses in circuit performance due to layout parasitics
parasitic caps
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
1 Introduction
2 Schematic Entry
3 Mixed-Mode HDL Simulation
4 Automatic Circuit Optimization
5 Full-Custom Layout Design and Verification
6 Conclusions
Intro Schem Mixed-Sim Optim Layout Conclusions
A Freeware EDA Framework for Teaching Mixed-Mode Full-Custom VLSI Design
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Jofre Pallarès et al. DCIS 2014
Conclusions
EDA environment for practicing mixed-mode full-custom VLSI design not only at lab but also at home
Students can gain hands-on experience on:
Practical A/D ΔΣM circuit design case in simple CMOS technology
Intro Schem Mixed-Sim Optim Layout Conclusions
Schematic entry
HDL mixed system simulation
HDL block specification
Automatic circuit optimization
DRC and LVS
PCell-based layout
Parasitics extraction
Post-layout electrical simulation
102726: Design of Analog and Mixed Integrated Circuits and Systems http://www.cnm.es/~pserra/uab/damics
42838: Integrated Heterogeneous Systems Design http://www.cnm.es/~pserra/uab/ihsd
Thanks for your attention!