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Adder
Discussion D6.2
Example 17
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si = ci ^ (ai ^ bi)
ci+1 = ai * bi + ci * (ai ^ bi)
a
b
s
c
c i+1
i
i
i
i
Full Adder (Appendix I)
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Full Adder
a b
cc
s
i i
i+1 i
i
Full Adder
a b
0c
s
0 0
1
0
Full Adder
a b
c
s
1 1
2
1
Full Adder
a b
c
s
2 2
3
2
Full Adder
a b
c s
3 3
4 3
c0
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-- Example 17a: 4-bit adderlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity adder4a is
port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); cf : out STD_LOGIC; ovf : out STD_LOGIC; s : out STD_LOGIC_VECTOR(3 downto 0)
);end adder4a;
Full Adder
a b
0c
s
0 0
1
0
Full Adder
a b
c
s
1 1
2
1
Full Adder
a b
c
s
2 2
3
2
Full Adder
a b
c s
3 3
4 3
c0
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architecture adder4a of adder4a is -- intermediate carriessignal c: STD_LOGIC_VECTOR(4 downto 0);begin c(0) <= '0'; s <= a xor b xor c(3 downto 0); c(4 downto 1) <= (a and b) or (c(3 downto 0) and (a xor b)); cf <= c(4); ovf <= c(3) xor c(4);end adder4a;
a
b
s
c
c i+1
i
i
i
i
Full Adder
a b
0c
s
0 0
1
0
Full Adder
a b
c
s
1 1
2
1
Full Adder
a b
c
s
2 2
3
2
Full Adder
a b
c s
3 3
4 3
c0
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Aldec Active-HDL Simulation
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Full Adder
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Ci Ai Bi Si Ci+1
Truth table
Ci CombinationalLogic
CombinationalLogicAi
Bi
Si
Ci+1
Behavior
Ci+1:Si = Ci + Ai + Bi
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Full Adder
Block Diagram
Full Adder
a b
cc
s
i i
i+1 i
i
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4-Bit Adder
c 1 1 1 0 0:a 0 1 1 0 1 0:b 0 0 1 1 1c4:s 1 0 1 0 0
Full Adder
a b
0c
s
0 0
1
0
Full Adder
a b
c
s
1 1
2
1
Full Adder
a b
c
s
2 2
3
2
Full Adder
a b
c s
3 3
4 3
c0
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-- Example 17a: 4-bit adderlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity adder4b is
port( a : in STD_LOGIC_VECTOR(3 downto 0); b : in STD_LOGIC_VECTOR(3 downto 0); cf : out STD_LOGIC; ovf : out STD_LOGIC; s : out STD_LOGIC_VECTOR(3 downto 0)
);end adder4b;
Full Adder
a b
0c
s
0 0
1
0
Full Adder
a b
c
s
1 1
2
1
Full Adder
a b
c
s
2 2
3
2
Full Adder
a b
c s
3 3
4 3
c0
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architecture adder4b of adder4b is begin
process(a,b)variable temp: STD_LOGIC_VECTOR(4 downto 0);variable sv: STD_LOGIC_VECTOR(3 downto 0);variable cfv: STD_LOGIC;begin
temp := ('0' & a) + ('0' & b);sv := temp(3 downto 0);cfv := temp(4);ovf <= sv(3) xor a(3) xor b(3) xor cfv;cf <= cfv;s <= sv;
end process;end adder4b; c 1 1 1 0
0:a 0 1 1 0 1 0:b 0 0 1 1 1c4:s 1 0 1 0 0
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Aldec Active-HDL Simulation
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-- Example 17c: 4-bit adderlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_unsigned.all;entity adder is
generic(N:positive := 8); port(
a : in STD_LOGIC_VECTOR(N-1 downto 0); b : in STD_LOGIC_VECTOR(N-1 downto 0); s : out STD_LOGIC_VECTOR(N-1 downto 0)
);end adder;architecture adder of adder is begin
process(a,b)begin
s <= a + b;end process;
end adder;
N-Bit Adder
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Aldec Active-HDL Simulation