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Advanced Digital Logic Design – EECS 303
http://ziyang.eecs.northwestern.edu/eecs303/
Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298
![Page 2: Advanced Digital Logic Design – EECS 303ziyang.eecs.umich.edu/~dickrp//eecs303/lectures/adld-testing.pdf · Advanced Digital Logic Design – EECS 303 Teacher:Robert Dick Office:L477](https://reader031.vdocument.in/reader031/viewer/2022022006/5abd5b097f8b9a7e418b7f17/html5/thumbnails/2.jpg)
Combinational testingSequential testing
YieldFault modelsCombinational test generation
Outline
1. Combinational testing
2. Sequential testing
2 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Introduction to testing
After fabrication, some circuits don’t work correctly
Determining which circuits contain faults requires testing
Testing some types of circuits is easy, testing others is difficult
One can use automation to help solve this problem
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Introduction to testing
Determining the best way to test large circuits requiresautomation
Building large circuits that are easy to test also requiresautomation
Testing it spans all design, from system to physical level
Today, I’ll introduce some classical ideas at the logic level
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Section outline
1. Combinational testingYieldFault modelsCombinational test generation
5 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Yield
Yield, y , is the fraction of fault-free products
Test fault coverage, c , is the fraction of faults that the set ofapplied tests detects
Low-yield is expensive because fabrication capacity is wasted
Defect level, d , is the fraction of parts containing undetectedfaults
d = 1− y1−c
A high defect level is extremely expensive because it meanscircuits make their way into products, or worse, to consumers,before faults are discovered
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Defect level
Example acceptable defect level: ∼ 0.0002
Either yield must be very high or fault coverage must be very high
d × 10-6
0.5 0.6 0.7 0.8 0.9 1
y
99 99.2 99.4 99.6 99.8
100
c (%)
0 100 200 300 400
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Section outline
1. Combinational testingYieldFault modelsCombinational test generation
8 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Faults and failures
A fault is a physical defect in a circuit
A failure is the deviation of a circuit from its specified behavior
Faults can cause failures but they don’t always cause failures
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Functional testing
No assumptions about types of fault
No assumptions about structure or properties of Circuit UnderTest (CUT)
The CUT is a black box that is checked to determine whether itresponds to all (or most) input (sequences) as specified
However, ignoring structural information makes testingunnecessarily slow
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Structural testing
Use information about the specific CUT
Types of faults that are likely to occurStructure of circuit
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
zb
a
VDD
za
b
VDD
VSS
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
bridgingfault
zb
a
VDD
za
b
VDD
VSS
12 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
zb
a
VDD
za
b
VDD
VSS
12 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
stuck−openfault
zb
a
VDD
za
b
VDD
VSS
12 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
zb
a
VDD
za
b
VDD
VSS
12 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
stuck−at
fault
zb
a
VDD
za
b
VDD
VSS
12 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault models
zb
a
VDD
za
b
VDD
VSS
12 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Singe stuck-at faults
One of the simplest and most common fault models
S-a-0: Stuck-at 0S-a-1: Stuck-at 1
Relies on digital reinforcement
0.8 · VDD is 1 · VDD one logic stage laterS-a-0.8 ≈ s-a-1
For two-level logic, exhaustive test set for single stuck-at faultswill detect all multiple stuck-at faults, too
Doesn’t hold for multi-level logic
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Single stuck-at faults
Consider a NAND3 gate
Inputs faultz
A B C freea b c z
0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1
14 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Single stuck-at faults
Consider a NAND3 gate
Inputs faultz
A B C freea b c z
0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1
Too expensive to use 2n inputs (23 = 8 in this case)
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Single stuck-at faults
Consider a NAND3 gate
Inputs faultz
A B C freea b c z
0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1
Unate covering again
14 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault coverage
A test of all possible inputs for a NANDn gate will require 2n
tests
Applying all possible tests (or sequences of tests) for complexcircuits isn’t practical
However, for all NANDn gates, all single stuck-at faults (andimplicitly multiple stuck-at faults) can be tested using only n + 1tests
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault equivalence
The function of the circuit is identical in the presence of eitherfault
E.g., any input of a NAND gate being s-a-0 or the output beings-a-1 → output of 1
In general, identifying equivalent faults, or fault collapsing isdifficult
However, can use knowledge about gates, and connectivities, tofind most equivalent faults
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault equivalence
Consider a NAND3 gate
Inputs faultz
A B C freea b c z
0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1
Equivalent faults
17 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Fault equivalence
Consider a NAND3 gate
Inputs faultz
A B C freea b c z
0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1
Equivalent faults
17 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Other fault models
∼ 2/3 CMOS faults are not stuck-at faults
Luckily, stuck-at fault tests often detect them
More advanced faults models
Allow higher theoretical coverageAre more complicated
In this lecture, we only have time to cover stuck-at-faults
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Section outline
1. Combinational testingYieldFault modelsCombinational test generation
19 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Test generation
Can use algorithms to automatically generate a test for a specificfault
Problem: Identify some test, t, such that the output of thecircuit will deviate from its specified value if a particular fault, f ,is present
Excitation: Need to propagate a value to stuck-at fault that iscontrary to the fault value
Sensitization: Need to propagate the faulty value to an output ofthe circuit
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Excitation and sensitization
s−a−0
s−a−0
111
excitation
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
0
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Excitation and sensitization
s−a−0
s−a−0
111
excitation
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
0
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Excitation and sensitization
s−a−0s−a−0
111
excitation
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
0
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Excitation and sensitization
s−a−0s−a−0
111
excitation
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
0
21 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Excitation and sensitization
s−a−0s−a−0
111
excitation
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
s−a−0
0
1
0
111
sensitization
0
21 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Backtracking
111
s−a−0
not sensitized
0
1
0
1
1
1
s−a−0
111
s−a−0
01
0
sensitized
111
s−a−0
01
0
sensitized
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Backtracking
111
s−a−0
not sensitized
0
1
0
1
1
1
s−a−0
111
s−a−0
01
0
sensitized
111
s−a−0
01
0
sensitized
22 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Backtracking
111
s−a−0
not sensitized
0
1
0
1
1
1
s−a−0
111
s−a−0
01
0
sensitized
111
s−a−0
01
0
sensitized
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Backtracking
111
s−a−0
not sensitized
0
1
0
1
1
1
s−a−0
111
s−a−0
01
0
sensitized
111
s−a−0
01
0
sensitized
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Automatic Test Pattern Generation (ATPG)
Can automatically determine test for a particular fault
Boolean difference
Generally considered too slow for use on large circuitsEasy to understand
Excitation/sensitization based methods (D-algorithm)
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
i1i2
i3z
In the presence of the fault, function is i3XOR faulty and specified functions
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
s−a−0i1i2
i3z
In the presence of the fault, function is i3
XOR faulty and specified functions
24 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
δ
i1i2
i3
In the presence of the fault, function is i3
XOR faulty and specified functions
24 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
If the resulting function is 0, the fault can not be identified
If the resulting function is 1, the fault can be identified
Use a test that satisfies (sets to 1) the function
25 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
26 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
26 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
26 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Boolean difference
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
0
1
00 01 11 10
1
1
1
1
00
0 0
0
1
00 01 11 10
1
00
0
0
0
0
0
0
1
00 01 11 10
0 0
00 11
1 0
26 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm
We have seen that, in order to test for a particular fault, we must
Excite the faultSensitize a path from the fault to the output
The D-algorithm is an automated method of finding a test thatexcites a fault and sensitizes a path to the circuit output
J.P. Roth, IBM, 1966
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Roth’s extension to Boolean algebra
α/β
α is the fault-free valueβ is the value in the presence of the fault
0/0 = 0
1/1 = 1
1/0 = D0/1 = DX/X = X
28 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
(N)AND D-cubes of failure
detection D-cube of failuregate input z
a b a b z
AND 1 1 s-a-0 1 1 D0 X s-a-1 0 X DX 0 s-a-1 X 0 D
NAND 1 1 s-a-1 1 1 D0 X s-a-0 0 X DX 0 s-a-0 X 0 D
29 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
(N)OR D-cubes of failure
detection D-cube of failuregate input z
a b a b z
OR 0 0 s-a-1 0 0 D1 X s-a-0 1 X DX 1 s-a-0 X 1 D
NOR 0 0 s-a-0 0 0 D1 X s-a-1 1 X DX 1 s-a-1 X 1 D
30 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
(N)AND D-cubes of propagation
input AND NANDa b z z
1 D D D1 D D DD 1 D DD 1 D DD D D DD D D D
31 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
(N)OR D-cubes of propagation
input OR NORa b z z
0 D D D0 D D DD 0 D DD 0 D DD D D DD D D D
32 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm
1 Initially, all the lines in the circuit are X (Don’t Care)
Left blank in example
2 A gate with an input of D or D and an output of X belongs tothe frontier
3 An element whose assigned inputs do not imply the output isunjustified
4 We want to drive the frontier to a circuit output (sensitize). . .
5 . . . and justify the gate inputs (excite)
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm overview
no
done
yes
choose D-cubeof failure toexcite fault
sensitize pathto output
justify gates
conflicts? Backtrack
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D-algorithm
Select a D-cube of failure to excite the faultwhile frontier has not yet reached an output do
Perform the implications of the most recent assignmentif the frontier is empty then
Backtrackend ifChoose a signal, s, s.t. s can’t reached from the faultAssign s to a value in order to propagate the fault forward
end whilefor each unjustified line, l do
if l can be justified thenJustify l
elseBacktrack
end ifend forA test has been found
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm notes
There are a few details not explained in the pseudocode
Signals should be selected in order to drive the frontier forward
Backtracking is the action of backing up and taking the closestpreviously unexplored branch in the decision tree
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
i1i2i3
i4
i5
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
s−a−1
i1i2i3
i4
i5
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
i1i2i3
i4
i5 0/1 = D
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
i1i2i3
i4
i5
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
i1i2i3
i4
i5
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
i1i2i3
i4
i5
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
i1i2i3
i4
i5
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
i1i2i3
i4
i5
D
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
i1i2i3
i4
i5
D
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
Conflict!
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
0
i1i2i3
i4
i5
D
Dz
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
0
1
D
1
i1i2i3
i4
i5
D
z
37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
1
0
i1i2i3
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm example
D
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37 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
NOR D-cubes of failure
detection D-cube of failuregate input z
a b a b z
NOR 0 0 s-a-0 0 0 D0 1 s-a-1 0 1 D1 0 s-a-1 1 0 D1 1 s-a-1 1 1 D
38 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
NOR D-cubes of failure
detection D-cube of failuregate input z
a b a b z
NOR 0 0 s-a-0 0 0 D0 1 s-a-1 0 1 D1 0 s-a-1 1 0 D1 1 s-a-1 1 1 D
38 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
AND D-cubes of propagation
input ANDa b z
1 D D1 D DD 1 DD 1 DD D DD D D
39 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
AND D-cubes of propagation
input ANDa b z
1 D D1 D DD 1 DD 1 DD D DD D D
39 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
NOR D-cubes of propagation
input NORa b z
0 D D0 D DD 0 DD 0 DD D DD D D
40 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
NOR D-cubes of propagation
input NORa b z
0 D D0 D DD 0 DD 0 DD D DD D D
40 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
NOR D-cubes of failure
detection D-cube of failuregate input z
a b a b z
NOR 0 0 s-a-0 0 0 D0 1 s-a-1 0 1 D1 0 s-a-1 1 0 D1 1 s-a-1 1 1 D
41 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
NOR D-cubes of failure
detection D-cube of failuregate input z
a b a b z
NOR 0 0 s-a-0 0 0 D0 1 s-a-1 0 1 D1 0 s-a-1 1 0 D1 1 s-a-1 1 1 D
41 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm summary
If a test for a fault exists, guaranteed to generate it
Full backtracking
However, much faster than Boolean difference
42 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Caveats
This lecture has only introduced some topics in testing
If you intend to do research in this area, take a few courses ontesting
Single stuck-at fault model is becoming obsolete
43 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
Caveats
D-algorithm is actually more complicatedAvoiding backtracking is important for performance
ImplicationsHeuristics to make best decisions first
Should understand derivation of D-cubes for arbitrary fault models
44 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
D-algorithm reference
Stanley Hurst. VLSI Testing: Digital and Mixed Analogue/DigitalTechniques. Institution of Electrical Engineers, U.K., 1998
This is one of the better references in the library
Beware: The D-algorithm examples contain small errors
45 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
YieldFault modelsCombinational test generation
CAD survey reference
Melvin A. Breuer, Majid Sarrafzadeh, and Fabio Somenzi.Fundamental CAD algorithms. IEEE Trans. Computer-Aided Design ofIntegrated Circuits and Systems, 18(12):1449–1475, December 2000
Recommended by a student
Introduces a number of important logic-level and physical-levelCAD algorithms
A useful supplement to the material in Hachtel and Somenzi’s,and Sherwani’s books
Introduces the D-algorithm
46 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Outline
1. Combinational testing
2. Sequential testing
47 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Section outline
2. Sequential testingD-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
48 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
D-algorithm review
Given a fault, the D-algorithm will generate a test for that fault
Selects a D-cube of failure to excite the fault
Propagates a D value to the circuit outputs be selection D-cubesof propagation for gates
Justifies gate inputs
Uses full backtracking on D-cubes of failure and gate justification
49 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Fault simulator
Fault simulation is the process of determining which faults a testdetects
Test generation is complicated and time-consuming
Fault simulation is quick
50 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Test sequence generation
The D-algorithm gives us a way to generate a test for a given faultHowever, we need a sequence of tests for all (or most) faults
Determine all stuck-at faults for the circuitEliminate equivalent faultswhile untested faults remain do
Pick a fault and use an ATPG to generate a testAppend the test to a listUse a fault simulator to determine all faults the test detectsEliminate detected faults
end while
51 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Test sequence generation
However, this approach can still be too expensive
Recall
Fault simulation is fastATPG is slow
Take advantage of fault simulator
52 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Test sequence generation
while fault coverage is less than 90% doGenerate a random pattern – extremely fastUse a fault simulator to determine if new faults are detectedif so then
Append pattern to a listEliminate detected faults
end ifend whilewhile fault coverage is less than 99.5% do
Pick a fault and use an ATPG to generate a testAppend the test to a listUse a fault simulator to determine all faults the test detectsEliminate detected faults
end while
53 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Section outline
2. Sequential testingD-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
54 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancies
Sometimes a s-at-0 fault can’t be detected
Implication: Given any set of inputs to the circuit, that node canbe set to 0 and the output will match the specifications
Converse for s-a-1 faults
Even if a portion of the circuit is not able the switch, the samefunction is realized
The presence of an undetectable fault implies redundancy
How can the D-algorithm can be used to simplify logic?
55 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancies
Sometimes a s-at-0 fault can’t be detected
Implication: Given any set of inputs to the circuit, that node canbe set to 0 and the output will match the specifications
Converse for s-a-1 faults
Even if a portion of the circuit is not able the switch, the samefunction is realized
The presence of an undetectable fault implies redundancy
How can the D-algorithm can be used to simplify logic?
55 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancies
Logic terminating in the location of the stuck-at fault can be removedfrom the circuit and the same function will be realized
Conventional wisdom suggests removal
Simplify logicMake circuit more fully testable
56 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
a
b
z
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
s-a-0a
b
z
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
s-a-0
Excite: a 6= b
a
b
z
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
s-a-0
Excite: a 6= bSensitize: a = b = 0
a
b
z
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
s-a-0
Excite: a 6= bSensitize: a = b = 0
a
b
z
Can’t excite and propegate faulty value to z!
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
s-a-0
Excite: a 6= bSensitize: a = b = 0
Replace s-a-0 logic with 0
0
a
b
z
Can’t excite and propegate faulty value to z!
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
s-a-0
Excite: a 6= bSensitize: a = b = 0
Replace s-a-0 logic with 0
Eliminate unused logic
0
a
b
z
Can’t excite and propegate faulty value to z!
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy example
Excite: a 6= bSensitize: a = b = 0
Replace s-a-0 logic with 0
Simplify logic
Eliminate unused logic
a
b
z
Can’t excite and propegate faulty value to z!
57 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
ATPG for logic simplification
Can use ATPG algorithm to simplify logic
1 Find a fault that is untestable due to redundancy
2 Remove the redundant logic
3 Repeat
58 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Redundancy removal not always safe
Logical equivalence may not imply true equivalence
What happens if redundancy is intentional?
To reduce power consumptionTo ensure signal stability for use in asynchronous circuits
Removal can
Increase powerIntroduce races
59 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Section outline
2. Sequential testingD-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
60 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Sequential testing
Can convert to a version of combinational testing
Iterative array expansion
Simulation-based
61 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Iterative array expansion
Make a copy of the combinational logic for each time step
However, now the problem converts ATPG for multiple faults
Iterative array expansion increases the size of the combinationalproblem
More importantly, changes the required fault model
Requires ATPG for multiple faults
62 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Iterative array expansion
D Q
QC
i4
i1
i3
i2
z
c
63 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Iterative array expansion
s−a−0
D Q
QC
i4
i1
i3
i2
z
c
63 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Iterative array expansion
1
s−a−0
D Q
QC
i4
i1
i3
i2
z
c
i04
i01
i03
i02
z0
63 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Iterative array expansion
1
s−a−0
s−a−0
D Q
QC
i4
i1
i3
i2
z
c
i14
i11
i13
i12
z1
i04
i01
i03
i02
z0
63 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Iterative array expansion
1
s−a−0
s−a−0
D Q
QC
i4
i1
i3
i2
z
c
i14
i11
i13
i12
z1
i04
i01
i03
i02
z0
63 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Modified D-algorithm for iterative array
Propagate D-frontier forward
Generate new time frames as necessary
Propagate gate justification backward
Generate new time frames as necessary
However, this algorithm is not certain to find a test if one exists
Roth’s algebra not suited to sequential circuits
64 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Muth’s 9-valued logic
D-algorithm can’t adequately model the possible states insequential circuits
Repeated effect of fault can’t be modeled
Roth’s values
0/0, 0/1 (D ), 1/0 (D), 1/1, X/X
Muth’s values
0/0, 0/1, 0/X, 1/0, 1/1, 1/X, X/0, X/1, X/X
65 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
Generate a vector
Determine whether that vector brought the circuit state nearer toor farther from fault excitation and sensitization
If the state moved near to detection, append the pattern to a list
Many of the probabilistic optimization algorithms in the thirdlecture can be applied for simulation-based testing
66 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
abc
67 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
s−a−1
abc
67 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
s−a−1
abc
What if a, b, and c are state variables?
67 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
0
10
1
0
0
00
1
1
s−a−1
000 101
111001
110
abc
What if a, b, and c are state variables?
67 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
0
10
1
0
0
00
1
1
011?
s−a−1
000 101
111001
110
abc
What if a, b, and c are state variables?
67 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Simulation-based sequential testing
10
0
10
1
0
0
00
1
1
s−a−1
011000 101
111001
110
abc
What if a, b, and c are state variables?
67 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Sequential test generation problems
Sequential test generation intractable for large circuits
Some continue to work on improving test generation
Others modify circuit structure to make test generation easier. . .
68 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Section outline
2. Sequential testingD-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
69 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan-based design for test (DFT)
If testability is considered during design or synthesis, can bemade easy
Instead of forcing ATPG to deal with synchronous testing, inserta scan chain
Chain together (all) flip-flops and scan through an input if andonly if a testing input is activated
70 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan D flip-flop
C
Q
DQ
71 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan D flip-flop
TD
S
71 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan D flip-flop
C
Q
TD Q
S
71 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan D flip-flop
to next flip−flopfrom previous flip−flopC
Q
TD
71 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan D flip-flop
testing logic overhead
to next flip−flopfrom previous flip−flopC
Q
TD
71 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan D flip-flop
testing logic overhead
testing routing overhead
to next flip−flop
testing routing overhead
from previous flip−flopC
Q
TD
71 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Full scan
Greatly simplifies testing
Converts sequential testing to combinational testing
Testing can be slow if I/O pins limited
Significantly increases chip area and price
More complicated flip-flopsMore complicated routingI/O requirements, especially if speed required
72 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Scan chain
serial scan input
test mode
clock
combinational logic
serial scan outputQ
C
D
T
S
Q
C
D
T
S
Q
C
D
T
S
Q
C
D
T
S
73 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Level-sensitive scan design (LSSD)
Less delay than scan-path during normal operation
Used commercially, especially within IBM
Pre-processing step replaces all latches with LSSD latches
Other companies have related testing approaches
Scan path – NECScan/set – Sperry UnivacRandom access scan – Fujitsu
74 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
LSSD
TCtest1
Ctest2
D
Cnormal
L1
L1
L2
L2
75 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
LSSD
TCtest1
Ctest2
D
Cnormal
L1
L1
L2
L2
level sensitive D flip-flop
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
LSSD
TCtest1
Ctest2
D
Cnormal
L1
L1
L2
L2
level sensitive D flip-flop
level sensitive D flip-flop
75 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
LSSD
TCtest1
Ctest2
D
Cnormal
L1
L1
L2
L2
level sensitive D flip-flop
level sensitive D flip-flop
modecontrol
75 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
LSSD
Ctest1
Ctest2
D
Cnormal
L1
L1
L2
level sensitive D flip-flop
level sensitive D flip-flop
modecontrol
75 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Full scan disadvantages
Increased area
5%–15%
Increased delay
Depends on critical path average combinational logic depth
Slow when implemented serially
Need to serially clock through every register in IC
High pin requirements to speed up
76 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Partial scan
Instead of scanning all latches, scan a subset
Need to carefully select scanned latches based on
Test coverage effectsTesting speed
77 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Advanced DFT/SFT techniques
Testing core-based systems-on-chip (SoC)
Related to board-level boundary-scan
Fault injection
Reliability evaluationInsert fault into system and determine reaction
RTL synthesis for testability
Software fault modeling and testing
Extremely difficult problem
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Personal observations on testing
Despite continued research on advanced testing techniques,industry continues to use full-scan
In order for industry to accept a more complicated testingtechnique, the advantages must be tremendousCompanies don’t like complexity
Testing is a fairly mature field
Some people in academia have shifted their interest away fromtesting
It remains a huge practical problem for industry
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Personal observations on testing
Companies don’t want increased complexity
Researchers want to see their ideas used
Therefore, reduction in interest in testing among researchers
Therefore, reduction in interest in testing among companies
However, companies still have huge testing problems
Therefore, high demand for MS and Ph.D. graduates with testingexperience
One option: target a research problems involving testing and anotherarea, e.g., synthesis
80 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Testing summary
Low defect rate requires high test coverage
Functional testing requires too many patterns
Use structural testing based on a fault model, e.g., single stuck-at
Can use fault equivalence to reduce patterns
Can automatically generate a test for a specific fault
Combine ATPG with fault simulator to generate a set of testswith high coverage
81 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Testing summary
Can use ATPG for logic simplification – redundancy
Sequential testing difficult for large circuits
Use DFT to make testing easier
Use design automation to make DFT easier
82 Robert Dick Advanced Digital Logic Design
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Combinational testingSequential testing
D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability
Sequential testing references
Sujit Dey, Anand Raghunathan, and Rabindra K. Roy.Considering testability during high-level design. In Proc. Asia &South Pacific Design Automation Conf., February 1998
Survey on high-level design/synthesis for test techniques
Kwang-Ting Cheng. Gate-level test generation for sequentialcircuits. ACM Trans. Design Automation Electronic Systems,1(4):405–442, October 1996
Survey on sequential test generation
83 Robert Dick Advanced Digital Logic Design