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Advanced Packaging Technology
Server Forum 2014 Copyright © 2014 Amkor Technology
Paul Silvestri l Director, TSV Product DevelopmentAmkor Technology, Inc.
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What Is Driving Advanced Packaging…• Connected device
proliferation• Network expansion• Increased compute and
performance requirements
• Big Data Analytics• Unique hardware
configurations
Source: The Register, 5 May, 2014
Source: Intel
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Why Advanced Packaging Matters…
• Consistent Challenges and Opportunities– Reduce power consumption– Improve performance– Enable more functionality– Reduce footprint– Control system costs
• Advanced Packaging Influences– New architectures– Increased BW and efficiency– Increased integration
• Differentiates Products– Performance increase– Functionality & Features
Source: IDC 2013
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The Challenges
• Power consumption and hardware cost are nearly equal
• Memory increasing share of power• Decreasing memory per core• Technology scaling is slowing
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Server Memory Requirements
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Advanced Packaging Topics
• NAND– Wire bond die stacks
• DRAM– Wire bond die stacks– TSV die stacks
• MCMs– 2.5D interposers– 2.1D substrates
• Panel Level Packaging• Chip on Chip Stacks
Wire Bond Die Stacks
HBM Memory Cube
2.5D Heterogeneous Package
Panel Package Products
NAND Panel Die Stack
3DS DDR4
CoC Possum
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NAND PACKAGING ADVANCEMENTS FOR SSD
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Packaging for SSDs• SSDs improve data latency• Thin die stacks <50um/layer• Wire bond interconnect• Increased storage density per package• NAND process technology advancements
continue– Packaging remains wire bond stacked
die
24 Die NAND Stack
Source: Yuan Xie, PSU
SSD Card
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Roadmap for NAND WireBond Stacks• Wire bond stacked die satisfies near/mid term density
requirements• TSV and Panel Level Packaging Only If Best Performance and
Form-factor Required
Source: IBM, Flash Memory Summit
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DRAM PACKAGING ADVANCEMENTS
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DRAM Die Stacks & Segments
Notebook
Smart Phone
LPDDR3/4 DDR3 DDR4 HBM HMC
Wire Bond Die Stacks
NetworkingTablet
Desk Top
Server
HPC
TSV Die Stacks
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DRAM Trends
• DRAM cell unchanged for 40 years• DRAM scaling has Slowed• DRAM per core is decreasing
Source: IBM, Flash Memory Summit
Source: Cisco, ECTC ‘14
Source: Cisco, ECTC ‘14
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DRAM Product Roadmap for Large Systems
8
4
2
1
Die
Cou
nt
Logic
Memory
Memory
Memory
Organic Substrate
Memory
HBM HMC3DS
Wire Bond Die Stacks TSV Die Stacks EmergingTechnology
FlipChip + WB
DDR3 & DDR4 DDR4 Advanced DRAM
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Large System DRAM TSV Memory Types
HBMDDR4‐3DS Existing Memory Architecture Evolutionary Bottom Die DRAM + Control Low TSV Count Loose TSV Pitch FCCSP-BGA Packaging 2 and 4 High Die Stacks DIMM Application Production Now
New Memory Architecture Revolutionary Bottom Die Control Only High TSV Count Tight TSV Pitch WLCSP Packaging 5 and 9 High Die Stacks 2.5D Interposer Application for
GPU Low volume manufacturing now
HMC New Memory Architecture Revolutionary Bottom Die Logic Control High TSV Count Tight TSV Pitch FC-BGA Packaging 5 and 9 High Die Stacks MCM and Board Mount for
Networking LVM Now
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INTERPOSER PACKAGING TECHNOLOGY
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2.5D Interposer & Advance Packaging Product Roadmap
Logic + Memory EmergingSilicon Partition
PhotonicsAdvanced
MCM
3D Photonics Panel SIP
Image Source: Xilinx Image Source: Altera
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SOC to 2.5D TSV MCM SiP Migration• Focus Process Node Development on Specific Application Functionalities
– Reduces complexity and mask layer count of process node– Improves performance, power, and area of each application– Optimized process node for silicon function– Improves wafer yield – Reduces wafer cost
Logic 1
Logic 1
Cache
Logic 2Logic 1
Multi-Die Interposer
SiP
Monolithic 22nm SOC
Type 1
Multi-Die Interposer
SiP
Monolithic22nm SOC
Type 2
Logic SoC
Logic 1
Logic 3
Logic 2
Logic 4
Logic 1 <20nm
Logic 228nm
Cache
Analog
Logic 1
Logic 2
Logic 3
Logic 4
Analog SoC Logic 2
Image Source: Xilinx
Defect Density and Die Size
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2.5D Logic + Memory Integration
• Tightly couple logic & memory • Efficient BW per energy consumed• HBM Memory on TSV si interposer• Advanced packaging
Amkor CoW TSV TV
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ADVANCED PACKAGING COMMERCIAL STATUS
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TSV & Advanced Packaging Commercialization Status
HMC‐3DHMC‐3D
Development Status
Uni
t Vol
ume
& C
apab
ility
Panel FO/PLPPanel FO/PLP
DDR4‐3DSDDR4‐3DS
Advanced MCM
Advanced MCM
2.5D Interposers
2.5D Interposers
Pro
duct
ion
Feas
ibilit
y
HBM‐3DHBM‐3D
Photonics 2.5D
Photonics 2.5D
TSV Devices Are In Production!TSV Devices Are In Production!
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Thank You!
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