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1-Led 7 segment display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity led_display is
Port ( count : in STD_LOGIC;
t : in STD_LOGIC;
reset : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0);
nq : inout STD_LOGIC_VECTOR (3 downto 0);
hton : out STD_LOGIC_VECTOR (6 downto 0));
end led_display;
architecture Behavioral of led_display is
component tff2
port (t,clk,rst: in std_logic;
r: inout std_logic;
p: inout std_logic);
end component;
component LED_7_SEGMENT
port(data : in STD_LOGIC_VECTOR (3 downto 0);
AtoG : out STD_LOGIC_VECTOR (6 downto 0));
end component;
begin
u1:tff2 port map (t,count,reset,q(0),nq(0));
u2:tff2 port map (t,q(0),reset,q(1),nq(1));
u3:tff2 port map (t,q(1),reset,q(2),nq(2));
u4:tff2 port map (t,q(2),reset,q(3),nq(3));
L1:LED_7_SEGMENT port map(q,hton);
end Behavioral;
led display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity LED_7_SEGMENT is
Port ( data : in STD_LOGIC_VECTOR (3 downto 0);
AtoG : out STD_LOGIC_VECTOR (6 downto 0));
end LED_7_SEGMENT;
architecture Behavioral of LED_7_SEGMENT is
begin
process(data)
begin
case data is
when "0000" => AtoG <= "0000001";
when "0001" => AtoG <= "1001111";
when "0010" => AtoG <= "0010010";
when "0011" => AtoG <= "0000110";
when "0100" => AtoG <= "1001100";
when "0101" => AtoG <= "0100100";
when "0110" => AtoG <= "0100000";
when "0111" => AtoG <= "0001101";
when "1000" => AtoG <= "0000000";
when "1001" => AtoG <= "0000100";
when "1010" => AtoG <= "0001000";
when "1011" => AtoG <= "1100000";
when "1100" => AtoG <= "0110001";
when "1101" => AtoG <= "1000010";
when "1110" => AtoG <= "0110000";
when "1111" => AtoG <= "0111000";
when others => AtoG <= "ZZZZZZZ";
end case;
end process;
end Behavioral;
t filp flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity tff2 is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
p : inout STD_LOGIC;
r : out STD_LOGIC);
end tff2;
architecture Behavioral of tff2 is
begin
process(rst,clk)
begin
if rst='0' then
p<='1';
r<='0';
elsif clk'event and clk='0' then
if t='1' then
r<= p;
p<=not p;
else
r<=not p;
p<= p;
end if;
end if;
end process;
end Behavioral;
2- state machine
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity state_machine2 is
Port ( i : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end state_machine2;
architecture Behavioral of state_machine2 is
type state is(a,b);
signal ns,ps: state;
begin
process(rst,clk)
begin
if rst='1' then
q<='0';
elsif clk'event and clk='1' then
case ps is
when a=>
if i='0' then
q<='1';
ns<=a;
else
q<='0'; A B
1/0
0/1
1/0
ns<=b;
end if;
when b=>
if i='0' then
q<='1';
ns<=b;
else
q<='0';
ns<=a;
end if;
end case;
end if;
end process;
end Behavioral;
3-Priority encoder
library ieee;
use ieee.std_logic_1164.all;
entity priority is
port ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));
end priority;
architecture archi of priority is
begin
code <= "000" when sel(0) = '1' else
0/1
"001" when sel(1) = '1' else
"010" when sel(2) = '1' else
"011" when sel(3) = '1' else
"100" when sel(4) = '1' else
"101" when sel(5) = '1' else
"110" when sel(6) = '1' else
"111" when sel(7) = '1' else
"---";
end archi;
4- 3 to 8 line decoder . libraryieee;
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
architecture archi of dec is
begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";
end archi;
5- 4-to-1 1-bitMUX usingan If statement.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end mux;
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
if (s = "00") then o <= a;
elsif (s = "01") then o <= b;
elsif (s = "10") then o <= c;
else o <= d;
end if;
end process;
end archi
VIMPlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A,B : in std_logic_vector(7 downto 0);
SUM : out std_logic_vector(7 downto 0);
CO : out std_logic);
end adder;
architecture archi of adder is
signal tmp: std_logic_vector(8 downto 0);
begin
tmp <= conv_std_logic_vector(
(conv_integer(A) +
conv_integer(B)),9);
SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;
8-bit adder/subtractor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port(A,B : in std_logic_vector(7 downto 0);
OPER: in std_logic;
RES : out std_logic_vector(7 downto 0));
end addsub;
architecture archi of addsub is
begin
RES <= A + B when OPER='0'
else A - B;
end archi;
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behvarchitecture behv of shift_reg is
-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)
begin
-- everything happens upon the clock changing
if clock'event and clock='1' then
if shift = '1' then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S(0);
end behv;
----------------------------------------------------
----------------------------------------------------
-- VHDL code for n-bit counter (ESD figure 2.6)-- by Weijun Zhang, 04/2001
--
-- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0););
end reg;
----------------------------------------------------
architecture behv of reg is
signal Q_tmp: std_logic_vector(n-1 downto 0);
begin
process(I, clock, load, clear)
begin
if clear = '0' then
-- use 'range in signal assigment
Q_tmp <= (Q_tmp'range => '0');
elsif (clock='1' and clock'event) then
if load = '1' then
Q_tmp <= I;
end if;
end if;
end process;
-- concurrent statement
Q <= Q_tmp;
end behv;
---------------------------------------------------
---------------------------------------------------
-- 3-bit Shift-Register/Shifter
-- (ESD book figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- reset is ignored according to the figure
---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;
---------------------------------------------------begin
-- combine inputs into vector
input <= J & K;
p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table
case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
-- concurrent statements
Q <= state;
Qbar <= not state;
end behv;
-------------------------------------------------
---------------------------------------------------
-- n-bit Register (ESD book figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- KEY WORD: concurrent, generic and range
---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------
entity reg is
generic(n: natural :=2);
port( I: in std_logic_vector(n-1 downto 0);
clock: in std_logic;
load: in std_logic;
clear: in std_logic;
Q: out std_logic_vector(n-1 downto 0)data_out: out std_logic
);
end dff;
----------------------------------------------
architecture behv of dff is
begin
process(data_in, clock)
begin
-- clock rising edge
if (clock='1' and clock'event) then
data_out <= data_in;
end if;
end process;
end behv;
----------------------------------------------
----------------------------------------------
-- JK Flip-Flop with reset
-- (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- the description of JK Flip-Flop is based
-- on functional truth table
-- concurrent statement and signal assignment
-- are using in this example
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------
entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;
-----------------------------------------------
architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);BEGIN
sum <= (a XOR b) XOR cin ;
cout <= (a AND b) OR ((a OR b) AND cin) ;
END arch1 ;
--REGISTER
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY reg IS
PORT(clk: IN std_logic ;
input: IN std_logic_vector(15 DOWNTO 0) ;
output: OUT std_logic_vector(15 DOWNTO 0) ;
ld: IN std_logic
) ;
END reg ;
ARCHITECTURE behavioral OF reg IS
BEGIN
generic_register: PROCESS(clk, input, ld)
BEGIN
IF (rising_edge(clk)) THEN
IF (ld = '1') THEN
output <= input ;
END IF ;
END IF ;
END PROCESS ;
END behavioral ;
---------------------------------------------
-- D Flip-Flop (ESD book Chapter 2.3.1)
-- by Weijun Zhang, 04/2001
--
-- Flip-flop is the basic component in
-- sequential logic design
-- we assign input signal to the output
-- at the clock rising edge
---------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use work.all;
---------------------------------------------
entity dff is
port( data_in: in std_logic;
clock: in std_logic; END PROCESS ;
END arch1 ;
--
-- 8 to 3 priority encoder
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY enc8to3 IS
PORT(SIGNAL input: IN std_logic_vector(7 DOWNTO 0) ;
SIGNAL output: OUT std_logic_vector(2 DOWNTO 0)
) ;
END enc8to3 ;
--
-- Here is a case where we really need the WHEN - ELSE
-- I don't think the WITH select will work because
-- we want a priority encoder
--
ARCHITECTURE arch1 OF enc8to3 IS
BEGIN
output <= "111" WHEN (input(7) = '1') ELSE
"110" WHEN (input(6) = '1') ELSE
"101" WHEN (input(5) = '1') ELSE
"100" WHEN (input(4) = '1') ELSE
"011" WHEN (input(3) = '1') ELSE
"010" WHEN (input(2) = '1') ELSE
"001" WHEN (input(1) = '1') ELSE
"000" ;
END arch1 ;
-- fa.vhd
--
-- A 1-bit full-adder
--
-- George L. Engel, SIUE
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fa IS
PORT( a, b : in std_logic ;
cin : in std_logic ;
cout : out std_logic ;
sum : out std_logic
) ;
END fa ;
ARCHITECTURE arch1 OF fa IS ld: IN std_logic ;
inc: IN std_logic ;
clr: IN std_logic
) ;
END counter ;
ARCHITECTURE behavioral OF counter IS
BEGIN
generic_counter: PROCESS(clk, input, ld, inc, clr)
VARIABLE tmpvar: unsigned(11 DOWNTO 0) ;
BEGIN
IF (rising_edge(clk)) THEN
IF (clr = '1') THEN
tmpvar := (OTHERS => '0') ;
ELSIF (ld = '1') THEN
tmpvar := unsigned(input) ;
ELSIF (inc = '1') THEN
tmpvar := tmpvar + "000000000001" ;
END IF ;
output <= std_logic_vector(tmpvar) ;
END IF ;
END PROCESS ;
END behavioral ;
--
-- Design a 2-bit count-down counter
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_signed.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY down_counter IS
PORT(SIGNAL x: IN std_logic ;
SIGNAL count : OUT std_logic_vector(1 DOWNTO 0) ;
SIGNAL reset: IN std_logic ;
SIGNAL clk: IN std_logic
) ;
END down_counter ;
ARCHITECTURE arch1 OF down_counter IS
BEGIN
PROCESS(clk, x, reset)
VARIABLE tmp_cnt: unsigned(1 DOWNTO 0) ;
BEGIN
IF (reset = '1') THEN
tmp_cnt := "00" ;
ELSIF rising_edge(clk) THEN
IF (x = '1') THEN
tmp_cnt := tmp_cnt - "01" ;
END IF ;
END IF ;
count <= std_logic_vector(tmp_cnt) ;--counter
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY counter IS
PORT(clk: IN std_logic ;
input: IN std_logic_vector(11 DOWNTO 0) ;
output: OUT std_logic_vector(11 DOWNTO 0) ;
jk ffentity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;
-----------------------------------------------
architecture behv of JK_FF is
-- define the useful signals here
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);begin
-- combine inputs into vector
input <= J & K;
p: process(clock, reset) is
begin
if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then
-- compare to the truth table
case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;
end process;
-- concurrent statements
Q <= state;
Qbar <= not state;
end behv;
counter - -
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;