Download - AMS Verification Solution
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Cadence Analog/Mixed-Signal Verification Solution Overview Zhong Fan Engineering Director, Cadence Technology on Tour, Singapore July 25, 2013
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Verification is biggest overall challenge in mixed-signal design
Many of silicon re-spins could be prevented by better verification
MS Verification Challenge
Cause of Silicon Re-spins
Biggest Challenge in MS Verification
Main Design Challenges
Preventable by better Verification
Methodology
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Key Elements of MS Verification Solution
Assertion, Coverage and Metric-Driven Methodology
Behavioral Modeling Simulation
Continuous advancements in performance and features
Methodology, library and tools abstracting analog and mixed-signal functionality to higher level
New, Digital-like Methodology applied on analog and mixed-signal Integrated Environment
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Virtuoso AMS Designer Integration of Virtuoso MMSIM and IUS Simulators
VIRTUOSO MMSIM & IUS INSIDE Hierarchy Editor, Text File Configuration, Virtuoso ADE Integration
Virtuoso AMS Designer
Enabling Mixed Signal Technology
Virtuoso UltraSim
Virtuoso Spectre/APS
Digital Solver Verilog, VHDL, SDF
SystemC, e SystemVerilog
Analog Solver Spectre, SPICE
Verilog-A Parasitics
Shared Memory Space
Verilog-AMS VHDL-AMS
Verilog(Wreal) VHDL
SPICE Verilog-A
Or Incisive
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Integration of Analog & Digital Verification Flows
Behavioral models used for functional verification Real number models offer analog functionality at digital speeds Models are easily used in the Virtuoso and Incisive environments
Pin/Bus communication abstracted to the transaction-level
Validate Models to Circuit (amsDMV)
Analog Domain Digital Domain
D Create Behavioral
Model (RNM)
Transistor level Schematic
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Testbench
Mixed Signal Verification
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Schematic Model Generation
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Top-level Integrated Design
ABV enables a comprehensive verification approach
Improved documentation Improved observability
Identifies errors where they take place instead of at the outputs
Monitors behavior for all vectors
Improved controllability Improved coverage Verification starts sooner
Assertion-Based Verification Introduction
Spec
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Assertions in Digital, Analog, and Mixed Signal
Why Assertions?
Assume
Assert
Cover
Language Support
SVA
PSL
OVM, IAL, e
Not New for Analog
Device checks
Spectre MDL
$cds_get_analog_value
Assertion Browser vs. Waveforms
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Metric Driven Verification Methodology
Traditional, Direct Verification Methodology
Metric Driven Verification (MDV)
Test Direct, User
defined
DUT (Device Under
Test)
SPEC
Automatic Checking
Pass/Fail report
Random Test Within specified
constraints
DUT (Device Under
Test)
SPEC
Automatic Checking and
Coverage Analysis
Coverage and Pass/Fail Reports
Verifies that circuit works for specific tests
Verifies that circuit works in specified constrain space Drives Verification process to achieve desired goal /coverage Reduces risk of silicon re-spin or costly product recall
Verification Plan
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Low-power Verification for Mixed-signal Designs
Virtuoso AMS Simulation Special attention needed to connecting modules in
analog-digital co-simulation Converting corrupted digital values into electrical or real
number values
Virtuoso Power Intent Export Architect CPF macro model and CPF design generation from
schematic & inherited connection Structural netlist generation for use by CLP
Conformal Low Power LP structural and functional static checks Test bench independent Fast and comprehensive
Virtuoso Schematic Editor
Conformal Low Power
CPF Macro & Design
OA
Verilog Std cell Library
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iso iso
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Vdd1
Vdd2
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Virtuoso Incisive
Encounter
VSE CPF generation, static LP verification by CLP
CPF-aware AMS simulation
Metric-driven MS verification (RNM, assertions, UVM-MS)
MS behavioral model generation and validation
Constraint-driven mixed-signal design
Unified analog/MS simulation environment
Unified mixed-signal implementation
(OA-based flows)
Cadence low-power and mixed-signal solution Comprehensive, interoperable, and proven flow
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