Analog Computing for High Energy Efficiency
Aatmesh Shrivastava Assistant Professor
Electrical and Computer Engineering 416 ISEC
12/14/17 1
2
Source :BEATECH
Exponen2al growth in the number of connected devices
IoT infographic by i-‐scoop based on Cisco data
IoT Prospects
3
Todays Power Requirements
~100 WaEs
~3 WaEs
~10 milli WaEs
~100 milli WaEs
4
Powering with Ambient Energy
Solar: 10µ-‐100µ WaEs
Temp Gradients: 10µ-‐100µ WaEs
Piezoelectricity: 10µ-‐100µ
RF Energy: 100n-‐1u WaEs
1000X lower than the lowest power MSP430!
5
Flow of Energy in an EH System
V
Ambient Source
Energy Harvester unit
Power Management
System Processing and Communica2on
Harvest from low voltage, low power level
Efficient Harves2ng
Low Voltage operaJon/system start-‐up to enable system at lower stored energy
Efficient Power Management
Solar, ∆T, RF, etc.
Maximize the available energy for the system
Every bit of stored energy should be used for system opera2on
Minimize loss in voltage conversion
Operate the system at lowest power level • Ultra-‐low power radios and analog. • Sub-‐threshold digital. • Low power sensing circuits.
Low Idle mode power consumpJon
Lowest power clock reference, voltage reference etc.
12/14/17 6
SoC Design • The circuit techniques enable ultra-‐low power IoT nodes.
Accelerators
4-Channel, 16-tap FIR
16-pt, Complex
FFT
CORDIC
4-Channel AFE
8-bit SAR ADC
WuRx
4kB DMEM
2kB Tx Buffer
Multiplier/MAC
Histogram (1-3)
Heart rate (R-R) and
AFIB
ADPLL
Tx FSM
DC-DC Converter
Power Management
Radios
Sensing
Timer (1)
Clocking
Var. Voltage SPI Pads(0.4-3.3V)
TEG
SolarSPI
(master)
MSP430
LCU
2kB LCU Instr Mem
2kB MSP Instr Mem
Bus Abitration
64B SPI FIFO
DMA
Clk/Pwr. Gate Ctrl
Bus Controllers
SYS. INTERRUPT
4GHz
400MHz – 2.4GHz
31.25kHz
Timer (2)
Boost Converter w/
MPPT
UWBTx
XO
SYS. CLK
SYS. VDD
DPM
CTRLR
CTRLR
CTRLR
A. Klinefelter,.. A. Shrivastava et al “A 6.45µW self-powered IoT SoC with integrated energy-harvesting… ” IEEE International Solid State Circuits Conference, Feb. 2015.
• ULP wireless SoC with integrated power management, transceiver, AFE, DSP, and flexible clocking
• Autonomous power management for baDery-‐free operaGon
• Highest level of integraGon, including energy harvesGng and a full transceiver, for the lowest power
• Highest energy harvesGng / regulaGon efficiency
• Flexible sensing interfaces and on-‐chip processing for a diverse set of target applicaGons
12/14/17 7
SoC Design Technique
• 4X improvement over prior art for higher current operaJon • 70X improvement in lifeJme in lower current mode
(These benefits are without taking boost converter into account)
70X improvement in lifetime for low current modes
4X improvement in lifetime for high current modes
(µA)
Reference Sys
Lower duty cycling rate
Higher duty cycling rate
12/14/17 8
Compu2ng at the Edge
• IoT devices need to have significant compute ability to the edge.
• Needed to cut-‐down RF comm. data and power consumpJon.
• However exisJng digital system architecture is higher area and higher power for compuJng.
• Analog to digital conversion creates a highly inefficient use of hardware as only two extreme points of a transistor operaJon is used
• Analog compuJng on the other hand makes use of large voltage range of device operaJon. Lower area and Lower power.
12/14/17 9
Analog Compu2ng
• Makes use of enJre voltage range of transistor operaJon.
• ImplementaJon of adders, mulJpliers, etc. requires only few transistors for implementaJon.
• However analog compuJng has tradiJonally suffered from accuracy issues due to variaJon.
• We have eliminated this variaJon and realize high precision analog circuits for computaJon.
• Can achieve power efficiency of 10-‐100 Tera-‐FLOPs/W
12/14/17 10
Sub-‐threshold Analog Pla]orm
PTAT current referenceIO=Vtln(M)/fRC1
Sub-threshold diff-amp with PTAT bias and switched-cap loadgain, A=ln(M)/η*(C1/C3)
Temperature variation of diff-amp gain at 48ppm/oC
(a) Precise differential amplifier design with sub-threshold operation
Sub-threshold gm-C filter with PTAT bias
UGF=fR*ln(M)/η*(C1/C2)
(b) Precise low-pass filter implementation with sub-threshold operation
VDD
Q1Q2R1
M5
M7
M6
M8
M
C1φ1 φ2
IoVX
VY
A
B Cd
Cd1
VDD
IOVX
Vi+
C3C3
φ1 φ2
φ1 φ2 CdCd
Vi-
VDD
VX
VY
VCMFB
Vin1 Vin2
C2
Vo2Vo1
C2
Io gm gm
2C4
2C4
gmgm
2C4
2C4 VO-
VO+
Vi-
Vi+
A gm-C biquad
ω =fR*ln(M)/η*(C1/C2)
Process variation of the diff-amp gain with 3-σ variation of 2.3%
Temperature variation of biquad filter cut-off frequency 69ppm/oC
Process variation of the biquad filter with 3-σ variation of 4.2%
12/14/17 11
Example Logarithmic Circuit
A A A A A+
-
+
-
+
-
+
-
+
-
Current Rectifier
Current Rectifier
Current Rectifier
Current Rectifier
Current Rectifier
∑ RSSI
VDD
IOV2
V1
Vi+ Vi
-
RA RA
signal power level (dBm)
RSS
I (V)
Diff-amp as a limiting amplifier
Successive cascaded amplifier stages to form an RSSI
(a) RSSI amplifier circuit (b) Simulation of the RSSI circuit
Input signal • Dynamic range of
70dB. • Less than 20nW
power consumpJon. • Only few transistors
needed. • No clock! • Less than 1%
inaccuracy.
• High precision, lower area and ultra-‐low power arithmeJc circuit
12/14/17 12
Feature Extrac2on
• Segng up feature extracJon method
signal power level (dBm)
RSS
I (V)
Inter-ictal power level
Pre-ictal power Threshold
VPTH
VDD
RSC
1R
SC2
VPTH
A+
-RSSIS
ULP comparator for threshold detection
Voltage threshold set by switched cap
(a) PLT feature extraction method
signal power level (dBm)
RSS
I (V)
Inter-ictal power level
logW
SVM Classifier
Hyperplane
Normal
SeizurexB
xA
WT.X+β
=W1X1+W2X2+W3X3+W4X4+W5X5+β
Power spectral density is weighted at each frequency band
logWX To ADC
(b) SVM classification based feature extraction
12/14/17 13
Analog Compu2ng
• We will develop high accuracy, analog compuJng infrastructure for ultra-‐low power computaJon at the edge.
• This system/computer architecture can cater to a large variety of IoT sensing needs.
• In iniJal stage, the development will cater to specific applicaJon with a goal to develop a more general architecture.
• Can achieve power efficiency of 10-‐100 Tera-‐FLOPs/W
14
• The converter should operate TEG at its MPP • High Efficiency.
VO
MPP Tracking
MPPclk
TEGV M
PP
Clock Gen
Cm
p_ou
t
LS Control
EN ϕ1
HS Control
LS
HS
Boost
MLS
MHS
VI
RSTint
Boost Control
Cold Start Osc
L
Clock Doubler
MSU
VX
Cold StartCircuit
C1
Low-‐Voltage Harves2ng
15
Thanks
16
MPPclk
TEG
VMPP
Clock Gen
Cmp_out
VIN
CTEGS1
S2
CM
CTRL
RST
Load / Boost Cnvtr
R
R
MPP Sampling
• Operates at MPP tracking point. Ø Periodically samples the maximum power point of the ambient
source ( TEG or Solar cell). Ø Operates the converter at its maximum power point through the
control loop.
MPP Tracking
17
• Operates in two phases ϕ1 and ϕ2. • ϕ1 is used for cancelling all the offset in the design. • ϕ2 is LS and HS control typical switching. • In LS, MLS is turned on and inductor starts charging • In HS, MHS is turned on and inductor transfers charge
ϕ1
LS
HS
ϕ2
EN
timeBoost control Timing Signals
VO
MPP Tracking
MPPclk
TEG
V MPP
Clock Gen
Cm
p_ou
t
LS Control
EN ϕ1
HS Control
LS
HS
Boost
MLS
MHS
VI
RSTint
Boost Control
Cold Start Osc
L
Clock Doubler
MSU
VX
Cold StartCircuit
C1
Boost Converter Architecture
0.05 0.15 0.25
1520
2530
35
VI
Efficiency
SimulationEquation(10)
I P,max
VI
(1)
10 20 30 40 50
6070
8090
IL
Efficiency
VI=50mVVI=100mVVI=200mVVI=300mV
Efficiency
Peak Ind. Current (IP)
18
MLSControl Circuit
VIIP
Ind.
Cur
rent
T
RL
Static and Switching Loss
Conduction Loss
a) Low Side switching
MHS
Control Circuit
VI
Static and Switching Loss
VO
RHConduction Loss
b) High Side switching
L L
• Efficiency varies greatly with peak inductor current
• Maximum efficiency point peak inductor current for a given VI is given by
𝑰↓𝑷,𝒎𝒂𝒙 = [6(𝑬↓𝑺𝑻 +𝑬↓𝑺𝑾 ) 𝑽↓𝑰 /𝑳𝑹↓𝑳 ]↑1/3 …. (1)
Peak Inductor Control
19
VO
ϕ1
ϕ1ϕ2
VO
VIN
VI
CLS
EN
MLS
LS
M1(2/0.2)
ILSctl
ILSctl
ϕ2
MP1(weak)
Cbias
Phase Node Node
VI VI+VTM1 -
- VI+VTM1 α (VI+VTM1-VTM1)2
α (VI)2
a
b
ϕ1
ϕ2
a b ILSctl
VCLS
crst
VON_LS
EN
VON_LS
LS TLS
VCLS
VIN
RSTint
VX
C1
Timing diagram
𝑰↓𝑳𝑺𝒄𝒕𝒍 = 𝑪↓𝑳𝑺 𝒅𝒗/𝒅𝒕 �→𝑻↓𝑳𝑺 = 𝑪↓𝑳𝑺 𝑽↓𝑰 /𝑰↓𝑳𝑺𝒄𝒕𝒍 = 𝑪↓𝑳𝑺 /𝒌𝑽↓𝑰
𝑰↓𝑷 = 𝑽↓𝑰 𝑻↓𝑳𝑺 /𝑳 = 𝑽↓𝑰 𝑪↓𝑳𝑺 /𝒌𝑳𝑽↓𝑰 = 𝑪↓𝑳𝑺 /𝒌𝑳
• Circuit provides peak inductor current independent of VI and VO. • In reality, the peak inductor current decreases with VI because of
voltage drop across LS switch.
Boost Converter Architecture
20
60 64 68
-50
515
25
4s
IL(mA)
60 64 68
-50
515
25
4s
IL(mA)
64 68 72 76
-50
515
25
4s
IL(mA)
70 75 80
-50
515
25
4s
IL(mA)
18 22 26
010
2030
4s
IL(mA)
18 22 26
010
2030
4s
IL(mA)
32 36 40
010
2030
4s
IL(mA)
32 36 400
1020
304s
IL(mA)
42 46 50
010
2030
4s
IL(mA)
Ind. Current (m
A)
VI=50mV VI=100mV VI=150mV VI=200mV VI=250mV
MeasuredEquation (1)
Ind. Current (m
A)
VO=0.6Va) Different measurements of peak inductor current (IP) with VI , VO=1.2V
VO=0.8V VO=1.0V VO=1.2V
b) Different measurements of peak inductor current (IP) with VO , VI=100mV
MeasuredEquation (1)
µs µs µs µs µs
µsµsµsµs
Within 15%
Within 1%
• measurement show that Ipeak is within 15% of 50mV VI and 1% for 150mV or above
Measurement Results
21
• Figure shows the zero detecJon control for controlling the high side switch. • Compares VX with VO. Once VX crosses VO, turns off HS switch. • Proposed comparator uses offset compensaJon in phase ϕ1 to realize near
ideal zero detecJon for max. efficiency
VO
HSMHS
VX
VREF
VX
rst
LS
RSTintϕ1
ENcmpLS
VX
ENcmpHS
ϕ1
VO
VI
C2
Timing Diagram
Zero Detec2on
22
Comparator (C2) Schematic
ENcm
p2
ENcmp ENcmp2
ENcmp
ϕ1
VX
COFFSET
ϕ1
VO
VREF
VREF
ENcmp
VO VO
d
ϕ1M2 M3
e
f
W
W/2 W/2
ϕ1
ϕ1
VREF
g
T1
T2
ENcmp2
VO
Common Gate Amp
ϕ1
VOFFSET
ENcmp
• A common gate amplifier gives high performance. • In phase ϕ1 output is fed back and offset is stored on COFFSET. • Zero detecJon is performed in LS in phase ϕ2. amplifier
achieves near ideal zero crossing
Zero Detec2on Comparator
23
• Cold-‐start is enabled for VO < 550mV which keeps POR low and enables the ring oscillator (RO).
• A clock doubler circuit runs from the output of RO and doubles the switng of the clock to 0 to 2VI.
• The measured cold-‐start voltage was 220mV
p1
p2
VI
PORLVT
Ring Oscillator
VI
VO
p1
p2
LS_SU
0 to VI
0 to 2VI
0 to VI
MSUClock
Doubler
LS_SU
Cold-‐Start Circuit
24
• Design was done in 130nm CMOS and the area is 0.12mm2. • The LS resistance is criJcal for low voltage operaJon,
designed value of 0.3Ω.
Die photograph of the boost converter.
Parameter ValueTechnology 130nm bulk CMOS
Total area 600 µm x 200 µmInductor value L=10 µH
VIN-‐to-‐VSS
LS resistance 300 mΩ (Target)
Inductor DCR 70 mΩ
Bondwire 50 mΩ(1mm,1mil,gold)
NMOS Res 120 mΩLayout parasitic 60 mΩ
VSSVX VO
MLS MHS
IP Ctrl ZDHS ControlLS ControlCold StartMPP
VI
Resistance breakdown of LS
Design Implementa2on
25
0 2 4 6
0.0
0.4
0.8
1.2
VI
Efficiency
-3 -1 1 2 3 4
0.0
0.4
0.8
1.2
VI
Efficiency
200mV/div
No overshoot or undershoot at Vx indicating ideal zero crossing
Inductor current
Vx
V
Vx200mV/div
Inductor current
b) Vx Waveform at VI=15mV for zero detection
a) Vx Waveform at VI=250mV at VO=1.1V for zero detection
Zero Detec2on
-0.06 -0.03 0.00-0.4
0.0
0.4
0.8
VI
Efficiency
c) Boost converter operation at VI=10mV
Vx 200mV/div
VO=0.9V
Inductor current
26
10mV opera2on
27
VOVI=250mV
50mV/div
Inductor Current
Cold Start from VI=250mV
VI
VI=20mV
20mV operation
Normal operationCold start
• Figure shows start-‐up from 250mV and harvest energy to 20mV input.
Start-‐up Opera2on
0.00 0.10 0.20 0.30
020
4060
80100
VI
Efficiency
Effi
cien
cy
VI
21% @ 10mV input, VO=0.6V
83% @ 300mV input, VO=1.1V
28
Efficiency of 21% at 10mV VI and 83% at 300mV VI.
Efficiency Measurement
29
This Work Carlson JSSC’10
Ramadass JSSC’11
Kadirvel ISSCC’12
Im JSSC’13
HarvesJng TEG TEG TEG Solar / TEG TEG Min. VI 10 mV 20 mV 25 mV -‐ 40 mV
Cold-‐Start VI Voltage
220 mV 600 mV 35 mV w/ mech. kick
330 mV / 5 µW 40 mV w/ X-‐former
IDDQ 300 nW ~ 1 µW -‐ ~330 nA -‐ IP Control ü û û -‐ û MPPT ü û ü ü ü
η (@ VI) 83% @ 0.3V 75% @ 0.1V 58% @ 0.1V 80% @ 0.5V, Solar 61% @ 0.3V
η at low VI 53 % @ 20 mV 22% @ 10 mV
46% @ 20 mV -‐ -‐
30% @ 50 mV 30% @ 100
mV
Technology 130 nm 130 nm 350 nm -‐ 130 nm
Comparison Table
30
Energy Harvester Roadmap
• Boost conversion involves charging the inductor L in low-‐side (LS) switching and storing the energy on capacitor on high-‐side (HS) switching
• More research is needed to improve both LS and HS efficiency.
MLSControl Circuit
VIIP
Ind.
Cur
rent
T
RL
Static and Switching Loss
Conduction Loss
a) Low Side switching
MHS
Control Circuit
VI
Static and Switching Loss
VO
RHConduction Loss
b) High Side switching
L L
31
Energy Harvester Roadmap
• A 5mV drop on LS switch can reduce efficiency by 50% at 10mV. • CMOS switches are not efficient for low-‐input voltages. • Need to explore external switches more efficient transistors. • Inductor: lower form factor and low power capability.
MLSControl Circuit
VIIP
Ind.
Cur
rent
T
RL
Static and Switching Loss
Conduction Loss
a) Low Side switching
MHS
Control Circuit
VI
Static and Switching Loss
VO
RHConduction Loss
b) High Side switching
L L
LS switching requires opJmizaJon on inductor and low-‐side switch
32
Energy Harvester Roadmap
• Our analysis show that device mismatch in controller can impact the efficiency from 15% to 45%.
• The controller design needs to improve to realize max efficiency
MLSControl Circuit
VIIP
Ind.
Cur
rent
T
RL
Static and Switching Loss
Conduction Loss
a) Low Side switching
MHS
Control Circuit
VI
Static and Switching Loss
VO
RHConduction Loss
b) High Side switching
L L
Histogram of y3
y3
Frequency
10 20 30 40 500
510
15Efficiency (%)
Freq
uenc
y
Histogram of Efficiency
µ=32.5% σ=4.67%
a) Efficiency without offset compensation
12/14/17 33
Bandgap Reference
• It uses 2x charge pump cells to bias the BJTs, reducing the operaJng voltage to a 400 mV, lowest voltage Bandgap circuit.
• Add PTAT and CTAT voltages to generate Bandgap reference. • It can reduce the VSU to ~400 mV. • Consumes 32 nW or lower power.
VEB1
Q1
1Vin
ϕ1
ϕ1 ϕ2
ϕ2 2x charge pump cell
CL1
Vin
ϕ2
ϕ1 ϕ2
ϕ1
Switched cap. netw.aVEB+ bΔVBE
VREF
Cf1 Cf2
+_
+_
VEB2
Q2
MCL2
ΔVBE+ _ 2x charge pump cell
VEB1 generation circuit VEB2 generation circuit
CΔ1 2
A. Shrivastava, et al “A 32nW Bandgap reference ….” IEEE International Solid State Circuits Conference, Feb. 2015
12/14/17 34
SIMO Energy Harvester
PV
1.5V
3.3V
1.2V
5VStorage
BoostBuck
+_
Buck
Boost
• Energy harvesJng and power management can also be combined into a single soluJon, which can save system cost.
• Single inductor can mulJplex to work for harvester and regulator.
A. Shrivastava, et al “A 1.2µW SIMO energy harvesting and power management unit….” IEEE Symposium on VLSI Circuits, June 2014.
12/14/17 35
1nW Crystal Oscillator
XTAL
CL
CL
X C RC VDD/GND
ENP
ENNMNC
XO
XI
NCAL
PCAL
SARD
igita
l C
ontr
olle
r
ENP
ENN
XO
XI
XI
XI
VREF
VREFH
VREF
VREFL
+_
+_
+_
+_
VDDC
XI CLK
Clock Buffer
Calibration circuit
Time constant generation circuit
AmplifierDCCLK
XO
CLK
Output of clock buffer operating at 32.768 KHz with duty-‐cycling,
A. Shrivastava, et al “A 1.5nW, 32.768 KHz XTAL Oscillator Operational from a 0.3V Supply” IEEE Journal of Solid State Circuits, 2016.
Measured waveform at 32 kHz
• Lowest power crystal oscillator.
12/14/17 36
• Started at Northeastern in August-‐16. q 2 Ph.D. students, 2 M.S.
• Experience q Over 11 years of experience in integrated circuits research and development q Several IC tapeout experience including TI’s OMAP which went into Google-‐glass q Part of the IoT start-‐up, PsiKick that has raised over $32M in funding.
• Lab q State of the art IC prototyping facility.
• ContribuJons q >25 conference and journals. q TPC Member ISCAS, MWSCAS, ISLPED, Editorial Review Board-‐SSCL.
• Awards q Selected for Airforce Young Inves2gator Award-‐2018. q 13 granted US Patents, over 20 pending patents q Louis T Radar Graduate Research Fellowship. q Charles Brown fellowship for excellence
Capabili2es