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DescriptionParts Bits Architecture
Mode 4:0 all processor mode
T 5 ARMv4T Thumb stateI & F 7:6 all interrupt masksJ 24 ARMv5TEJ Jazelle stateQ 27 ARMv5TE condition flag
V 28 all condition flagC 29 all condition flagZ 30 all condition flagN 31 all condition flag
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(+ cache)
ARM11
eight-stage3350.4 mW/MHz
1.2Harvard16 x 32
ARM7
three-stage800.06 mW/MHz
0.97Von Neumann8 x 32
ARM10
six-stage2600. 5 mW/MHz
1.3Harvard16 x 32
(+ cache)
ARM9
five-stage1500.19 mW/MHz
1.1Harvard8 x 32
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Pipeline depthTypical MHz
MIPS/MHz
MultiplierArchitecture
mW/MHz
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Revision Example coreImplementation
ISA enhancement
ARMv1 ARM1 First ARM Processor26 bit addressingARMv2 ARM2 32 bit multiplier
32 bit coprocessor supportARMv2a ARM3 On chip cache
Atomic swap instruction
ARMv3 ARM6 & ARM7DI 32 bit addressingSeparate cpsr & spsrNew modes UNDEF, ABORTMMU support virtual memory
ARMv3M ARM7MARMv4 StrongARM Signed & unsigned long multiplyLoad store instructionNew Mode - System
A
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Revision Example coreImplementation
ISA enhancement
ARMv4T ARM7TDMI & ARM9T ThumbARMv5TE ARM9E & ARM10E Superset of the ARMv4TExtra inst. added for changing statebetween ARM & ThumbEnhanced multiply instructions
Extra DSP type instructionsFaster multiply accumulate
ARMv5TEJ ARM7EJ & ARM926EJ Java acceleration
ARMv6 ARM11 New multimedia instructions
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