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ASIC, FPGAs and programmable processors
CMPE 641
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The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
FPGAs
ASICs
CPLDs
SPLDs
Microprocessors
SRAMs & DRAMs
ICs (General)
Transistors
Technology Timeline
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The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043Copyright © 2004 Mentor Graphics Corp.
PLDs
SPLDs CPLDs
PLAsPROMs PALs GALs etc.
Figure 3-02
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The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043Copyright © 2004 Mentor Graphics Corp.
a b c
l l l
Address 0 &
Address 1 &
Address 2 &
Address 3 &
Address 4 &
Address 5 &
Address 6 &
Address 7 &
a !a b !b c !c
!a !c!b& &
!a c!b& &
!a !cb& &
!a cb& &
a !c!b& &
a c!b& &
a !cb& &
a cb& &
Predefined AND array
Pro
gra
mm
ab
le O
R a
rra
y
w x y
Predefined link
Programmable link
Figure 3-03
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The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043Copyright © 2004 Mentor Graphics Corp.
PLDs ASICs
Standard Cell
Full Custom
Gate Arrays
Structured ASICs*
SPLDs
CPLDs
*Not available circa early 1980s
The
GAP
Figure 3-17
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FPGAs Large array of configurable logic blocks (CLB)
connected via programmable interconnects
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Features and Specifications of FPGAs
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Basic Programmable Devices
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Features and Specifications of FPGAs
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Features and Specifications of FPGAs
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Features and Specifications of FPGAs
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Generic Xilinx FPGA Architecture
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Clock Tree in FPGAs• Everything is preplaced and routed (there is no
space for improvement)
• There is no gate sizing to enhance performance
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FPGA vs ASIC
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Standard cell based IC
vs. Custom design IC
Standard cell based IC:
Design using standard cells
Standard cells come from library provider
Many different choices for cell size, delay, leakage power
Many EDA tools to automate this flow
Shorter design time
Custom design IC:
Design all by yourself
Higher performance
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Standard cell based VLSI
design flow
Front end
System specification and architecture
HDL coding & behavioral simulation
Synthesis & gate level simulation
Back end
Placement and routing
DRC (Design Rule Check), LVS (Layout vs Schematic)
dynamic simulation and static analysis
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Simple diagram of the front-end design flow
System
Specification
RTL
CodingSynthesis Gate level code
INV (.in (a), .out (a_inv));
AND (.in1 (a_inv), .in2 (b), .out (c));Ex: c = !a & b
Cab
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Simple diagram of the back-end design flow
gate level Verilog
from synthesisPlace
&
Route
Final layout
(go for fabrication)
DRC
Gate level VerilogLVS
Timing information
Gate level dynamic and/or static analysis
Design rule
check
Layout vs.
schematic
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Flow of placement and routing
• Floorplan (place macros, do power planning)
• Placement and in-place optimization
• Clock tree generation
• Routing
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Import needed files
• Gate level verilog (.v)
• Geometry information (.lef)
• Timing information (.lib)
INV (.in (a), .out (a_inv));
AND (.in1 (a_inv), .in2 (b), .out (c));
INV: 1um width AND: 2 um width
INV: 1ns delay; AND: 2 ns delay
INV ANDa
b
C
Delay (a->c): 1ns + 2ns = 3ns
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Floorplan• Size of chip
• Location of Pins
• Location of main blocks
• Power supply: give enough power for each gate
• Note: the height of standard cell gates are the same so thGND/VDD lines can connect them all in rows.
VDD (Metal)
Power supply (1.8V)
current
Gate 1 Gate 2 Gate 3 Gate 4
1.75v
Voltage drop equation: V2 = V1 – I * R
1.7v(need another power)
1.65v
VSS
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Floorplan of a single processor
Inst
Mem
ALU
MAC
Control
Data
Mem
Clock
In-
FIFO0
In-
FIFO1
Output
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Placement & in-placement optimization
• Placement: place the gates
• In-placement optimization
– Why: timing information difference between synthesis and layout (wire delay)
– How: change gate size, insert buffers
– Should not change the circuit function!!
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Placement of a single processor
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Clock tree
• Main parameters: skew, delay, transition time
Q
QSET
CLR
S
R Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Original Clock
Clock Delay = y
Clock Skew= x -yClock Delay= x
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Clock tree of single processor
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Routing
• Connect the gates using wires
• Two steps
– Connect the global signals (power)
– Connect other signals
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Metal Layer Topology
Routing
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Layout of a single processor
Area:
0.8mm x 0.8mm
Estimated speed:
450 MHz
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384 Check &
2048 Variable
processors
Logic UtilizationChip 1: low logic
utilization 30%Application 1 gates
Application 2 gates
50 μm 50 μm
30
Chip 2: high logic
utilization 96%
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Single Tile
Transistors 325,000
Area 0.17 mm2
CMOS Tech. 65 nm ST
Microelectronics
low-leakage
Max.
frequency1.19 GHz @
1.3 V
Power
(100%
active)
59 mW @
1.19 GHz, 1.3 V
47 mW @
1.06 GHz, 1.2 V
608 μW @
66 MHz, 0.675 V
App. power
(802.11a rx)16 mW @
590 MHz, 1.3 V
55 million transistors, 39.4 mm2
5.9
39 m
m
410 μm
410 μ
m
FFTVit
Mot.
Est. MemMem
5.516 mm
Mem
Summary of the 167 Many-core Chip
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FPGA vs ASIC summary
• Front-end design flow is almost the same for both
• Back-end design flow optimization is different
– ASIC design: freedom in routing, gate sizing, power gating and clock tree optimization.
– FPGA design: everything is preplaced, clock tree is pre-routed, no power gating
– Designs implemented in FPGAs are slower and consume more power than ASIC
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ASIC and FPGA vs DSP
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FPGA vs DSP• DSP:
– Easy to program (usually standard C)
– Very efficient for complex sequential math-intensive tasks
– Fixed datapath-width. Ex: 24-bit adder, is not efficient for 5-bit addition
– Limited resources
• FPGA
– Requires HDL language programming
– Efficient for highly parallel applications
– Efficient for bit-level operations
– Large number of gates and resources
– Does not support floating point, must construct your own.
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Current trend
• Programming flexibility
• High performance
– Throughput
– Latency
• High energy efficiency
• Suitable for future
fabrication technologiesP
erf
orm
an
ce
&
En
erg
y e
ffic
ien
cy
Programming flexibility
ASIC
FPGA
Prog.
DSP
Many
-core
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Target Many-core Architecture
• High performance• Exploit task-level parallelism in
digital signal processing and multimedia
– Large number of processors per chip to support multiple applications
• High energy efficiency
– Voltage and frequency scaling capability per processor
High F, V
Low F, V
Halt
36
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• 164 programmable procs.
• Three dedicated-purpose procs.
• Per processor Dynamic Voltage and Frequency Scaling (DVFS)
– Selects between two voltages (VDD High and VDD Low)
– Programmable local oscillator
167-processor Multi-voltage Computational Chip
Viterbi
Decoder
FFT
16 KB Shared
Memories
Motion
Estimation
D. Truong, W. Cheng, T. Mohsenin, Z. Yu, A. Jacobson, G. Landge, M. Meeuwsen,
C. Watnik, A. Tran, Z. Xiao, E. Work, J. Webb, P. Mejia, B. Baas, VLSI Symp. 2008, JSSC 2009 37
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Single Tile
Transistors 325,000
Area 0.17 mm2
CMOS Tech. 65 nm ST
Microelectronics
low-leakage
Max.
frequency1.19 GHz @
1.3 V
Power
(100%
active)
59 mW @
1.19 GHz, 1.3 V
47 mW @
1.06 GHz, 1.2 V
608 μW @
66 MHz, 0.675 V
App. power
(802.11a rx)16 mW @
590 MHz, 1.3 V
55 million transistors, 39.4 mm2
5.9
39 m
m
410 μm
410 μ
m
FFTVit
Mot.
Est. MemMem
5.516 mm
Mem
Summary of the 167 Many-core Chip