August 2018
Programmable Solutions Group 2
TOPICS• FPGAs at Intel
• Fundamentals of Digital Electronics
• FPGA Architecture
• Intel® Quartus® Prime Design Software
• FPGA Design Flow
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Companion Lab1. Obtain an FPGA development kit
2. Download the attached lab manual
3. Download Quartus Prime Lite
4. Run installation while viewing training
To improve download time, only select the device support that matches the device you are using.
Search for “DE10-Lite”
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
FIELD PROGRAMMABLE GATE ARRAY (FPGA)
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• Flexible, multi-functional reprogrammable silicon
• Custom hardware functionality
• Bare-metal speed and reliability
• Truly parallel in nature
• Flexible, multi-functional reprogrammable silicon
• Custom hardware functionality
• Bare-metal speed and reliability
• Truly parallel in nature
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
Benefits of FPGA Technology
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• Cost
• Time to market
• Performance
• Reliability
• Long-Term Maintenance
• Cost
• Time to market
• Performance
• Reliability
• Long-Term Maintenance
Source: http://www.ni.com/white-paper/6984/en/
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
The BIRTH OF FPGAS
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First PROM; programmable, but permanent
1970
First EPROM; erased using
UV light
1971
1975
First PLA; limited to sum
of products
1983
Altera founded
1983
EEPROM
First EPLD; re-programmable
CMOS
1984
1985
First FPGA;64 logic blocks w/ two three-
input LUTs
High-density CPLD; full
subsystems
1988
1989
Altera launches first Integrated graphic design environment
SOURCE: https://www.altera.com/about/company/history.html
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
Intel’s deep history with fpgas
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1994
Altera purchases Intel’s PLD business
First PLD
1984
1984
Intel and Altera establish a joint
marketing agreement
World’s first microprocessor
1971
Intel and Altera start foundry
relationship for 14nm FPGAs
and SoCs
2013 2015
Intel acquires
Altera
Intel is founded by Robert Noyce and
Gordon Moore
1968
2002
First embedded
DSP
1983
Founded
2012
SoC FPGAFirst
embedded RAM
1995 2000
First soft micro-
processor
2016
System-in-Package
(SIP)
// //
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
THE RISE OF NEW MARKETS
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PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
Back to the BASICS
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A Z
0 1
1 0
A B Z
0 0 0
0 1 1
1 0 1
1 1 1
A B Z
0 0 0
0 1 0
1 0 0
1 1 1
S A B Z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
2:1 MUXZ = (~S & A) | (S & B)
ANDZ = A & B
ORZ = A | B
InverterZ = ~A
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
Look-Up Table (LUT): THE FOUNDATION
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PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
LOGIC ARRAY (Building) BLOCKS
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x 10
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
Building the Array
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LABs
Row
interconnect
Column
interconnectSegmented
interconnects
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
How its Programmed
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Row/Column Interconnect Junction
Programming info stored in a external non-volatile device
• Active: programmed automatically at power-on
• Passive: Intelligent host (CPU) controls programming
PROGRAMMABLE SOLUTIONS GROUP | Intel® ConfidentialProgrammable Solutions Group
Modern FPGAs
14Source: https://www.altera.com/products/fpga/cyclone-series/cyclone-v/features.html
Programmable Solutions Group
Describing Electronics
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Schematics
Hardware Description Languages (HDLs)
–Verilog, VHDL are most popular
Other high level languages
–“C”
–OpenCL
A
B
C
Y
Z
Y = ~(~(~A | (A&B&C)));Z = (~(~A | (A&B&C))) & ((A&B&C) | ~C) & ~C);
Programmable Solutions Group
What is IP?
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• Complex functions that Intel designs for our customers so they don’t have to design it themselves• Sometimes IP is free
• The more complex stuff costs since its expensive to develop and make sure it works
• Examples: Ethernet Controller, PCIe Controller, soft processor, multiplier functions, etc.
Programmable Solutions Group
Intro to Quartus
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• Intel® Quartus® Prime Design Software is a tool for FPGA, SOC and CPLD design
• Includes synthesis, debug, optimization, verification and simulation
• Takes a description of an FPGA (schematic or HDL) and determines how the lookup tables are programmed
• Many formats to program an FPGA
–In this class we will use a “.sof” file (SRAM object file)
–The .sof file is “volatile” and needs to be reprogrammed every time the board is restarted
Programmable Solutions Group
Quartus User InterfaceQuartus Prime Software Main Window
Project Navigator shows your project hierarchy, source files, design units, IP and design revisions in your project.
Tasks window shows the status of the design and can be used to run or re-run parts of the design flow
Messages window outputs messages from each process of the run.
Files window has tabs for the report browser, open design files and any other file opened by the user.
IP Catalog window is open by default and is used to generate IP functions that are to be used in your design.
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Project NavigatorProject Navigator
Messages WindowMessages Window
Tasks WindowTasks Window
Files WindowFiles Window
IP CatalogIP Catalog
Programmable Solutions Group
Tools Overview
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Design Files
Analysis & Elaboration
Synthesis
Fitter
Constraints & settings
Functional Simulation
Gate-Level SimulationEDA Netlist Writer
Functional Netlist
Post-Fit Simulation Files
Programming & Configuration files
Assembler
TimeQuest Timing Analysis
EDA Libraries
HW Debug tools- Programmer- SignalTap™ II
logic analyzer- SignalProbe
MA
P
Programmable Solutions Group
New Project Wizard
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1. Name project
2. Set Working Directory & Top-Level Entity
3. Add source files
4. Select Device
5. EDA tool settings
All settings can be modified later. Some steps can be skipped.The top level entity must match the top level module in your design exactly (case sensitive) in order to avoid a compile error.
Programmable Solutions Group
HINT: Family & Device Settings
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Expand the window so you can see all the fields
Get the part number for your specific device by looking on the chip on your board or the side of the box.
Programmable Solutions Group
Pin Planner
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Compile YOUR DESIGN
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Warnings shown in blue won’t prevent your design from compiling or being programmed, but they could indicate possible bugs. This lab does not have any design constraints, so the .sdc file is not needed. You will learn how to create one in the timing analysis workshop.
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PROGRAM YOUR FPGA
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TEST YOUR DESIGN
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Next Step: Multiplexer
Circuit Truth table
Symbol
The multiplexer can be described by the following Verilog statement:
Programmable Solutions Group
KNIGHTRIDER
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• When Quartus Prime Lite first starts for the very first time it might ask you about purchasing a license, select Run Quartus, all licenses are free for this lab.
• Note that there are two development kits described in the Lab Manual. Be careful to refer to the appropriate development kit.
• If things fail to compile, check your Top Level Entity Setting Setting Top Level Entity and make sure that the module <design> matches your top level entity, including case.
• Programmer – Hit Start Twice if it fails to program the first time
• If the Knight Rider LEDR[0] is the only one that turns on, you have not assigned the CLOCK_50 pin properly in your assignments.
• Check the LEDR[0] and LEDR[9] pins carefully in the Knight Rider lab and see if they sequence properly. If not, study the code carefully!
• Sometimes copy and paste from files into Quartus has carriage return formatting errors. If you see run on lines with no carriage return, you need to copy things over line by line, or add the appropriate file to your project.
FINAL TIPS