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Automated Bias Voltage Design Exploration to Achieve Optimal Power, Performance and Area (PPA) for GLOBALFOUNDRIES 22FDX Technology
Presenter: Pratik Rajput Authors : Pratik Rajput, Ramya Srinivasan, Haritez Narisetty, Richard Trihy (GLOBALFOUNDRIES) : Prabuddh Kumar Nahta (Synopsys)
March 22-23, 2017 SNUG Silicon Valley
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Agenda
What is GLOBALFOUNDRIES 22FDX Technology?
Body-Biasing: A New Dimension in Design Closure
Automation of Design Planning
Body Bias Voltage Exploration Flow Details
Results
Conclusion
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22FDX Technology
What is 22FDX technology? 22nm Fully Depleted
Silicon-on-Insulator (FDSOI) technology from GLOBALFOUNDRIES
Advantages: Lower leakage due to
insulator layer Enables Body Bias (BB) with
minimal leakage impact FDSOI variability is smaller
across die due to lower doping effort
Bulk versus FDSOI
Planar Bulk Transistor Planar FDSOI Transistor with green insulator layer
Effects of Body Biasing in Bulk Transistor and FDSOI Transistor
Buried Oxide Layer
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22FDX Technology
Bias voltage is applied to P-well and N-well
Reverse Body Bias (RBB)
nMOS neg. substrate voltage, pMOS pos. substrate voltage
raising VT of these devices
Forward Body Bias (FBB)
nMOS pos. substrate voltage, pMOS neg. substrate voltage
lowering VT of these devices
RBB versus FBB
flipped well
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IoT/Sensor Market Example: Remote Security Camera Application
22FDX Delivers: Optimization for Max performance and Minimal power FBB for max performance RBB for minimal power (low leakage and dynamic power)
RF integration for reduced BOM cost
22FDX die
Wireless Comms
High Performance Application Processor
Watchdog Processor
FBB
RBB
Wakes up Image Processor to zoom
in and analyze potential threat
Detects motion
Wakes up comms to transmit message
Integrated RF
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22FDX Example: ARM Cortex-A7 Implementation
1200
800
125 240
Total Power (mW)
Freq. (MHz)
180 210 152
520
47% Less Power
22FDX is the first technology to demonstrate 0.4v operation at >500Mhz on an ARM A7 Processor
Source: Verisilicon
50% Faster +
18% Less Power
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22FDX: The Simple Solution for Advanced Node Performance
FinFET performance & power Superior Analog/RF
Performance on demand
Relative # of Masks
40% fewer masks Lower mask cost
Reduced cycle time Source: Based on GF internal assessments
w/ BB
w/ BB
Performance Relative # of Masks
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Agenda
What is GLOBALFOUNDRIES 22FDX Technology?
Body-Biasing: A New Dimension in Design Closure
Automation of Design Planning
Body Bias Voltage Exploration Flow Details
Results
Conclusion
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22FDX Body-Biasing Power/Performance Trade-off
Max Frequency
Leakage Power
Reverse Body-bias (RBB)
Forward Body-bias (FBB)
Maximum Performance Operating Mode
Minimum Leakage in Standby Mode
FBB and RBB are different devices
-2V to +2V Body-Biasing
FDSOI: Fully Depleted Silicon-on-Insulator
SLVT/LVT Lowest VT Optimized for FBB Highest Performance
RVT/HVT Mid-Range VT Optimized for RBB Balance of low leakage
and high performance
Leak
age
Pow
er
Relative Fmax
` RVT (RBB)
SLVT (FBB)
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22FDX Body-Biasing
Body-Biasing (BB) offers an additional option to tune for cell performance or power: Same implementation can be timed with different bias voltages, resulting
in different performance results Different body-biasing domains on one chip are enabling new design
architectures and design styles
PVT + BIAS PVTB
A New Dimension in Design Closure
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22FDX Body-Biasing
RTL can be dissected into modules for better BB optimization: Optimize modules rather than the whole design with module-specific BB Does NOT require level shifters or isolation cells (same VDD) Just spacing rule Proper design planning along with Body Biasing will give optimal PPA
Multi-Bias Domain - Example
Module VNW bias VPW bias VDD
OR1200_TOP 0V 0V VDD(+/-10%)
OR1200_CPU 0V -1V VDD(+/-10%)
OR1200_DU 1V -2V VDD(+/-10%)
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22FDX Body-Biasing Multi-Bias Domain - Floorplan
NET_BIAS0_VPW
NET_BIAS0_VNW
NET_BIAS1_VPW
NET_BIAS1_VNW
NET_BIAS2_VPW
NET_BIAS2_VNW
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For more information on 22FDX Reference SNUG SV 2016 paper on GF22FDX Technology and Enablement
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Agenda
What is GLOBALFOUNDRIES 22FDX Technology?
Body-Biasing: A New Dimension in Design Closure
Automation of Design Planning
Body Bias Voltage Exploration Flow Details
Results
Conclusion
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Hierarchical blocks of SoC designs Varying range of functional operating frequencies Benefit from optimal choice of BB and library modes
(RBB/FBB)
Automated solution for determining BB voltages and library mode selection is essential Provides best possible PPA while reducing design
turnaround time
Cockpit solution allows user to quickly make choice on critical design parameters Power, Performance and Area
22FDX Automated Bias Voltage Exploration
Block 1 RBB/FBB?
BB=?
Block 3
RBB/FBB? BB=?
Block 2
Top
RBB/ FBB? BB=?
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Agenda
What is GLOBALFOUNDRIES 22FDX Technology?
Body-Biasing: A New Dimension in Design Closure
Automation of Design Planning
Body Bias Voltage Exploration Flow Details
Results
Conclusion
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Architecture
Bias Voltage Exploration Utility (Standalone/Lynx)
Design RTL
Bias Type (FBB/RBB)
Bias Voltage nwell/pwell
CSV Reports
Lynx Plots/ DT reports Constraints
UPF
Two Modes of Operation: 1) Expeditious Mode
2) Comprehensive Mode (increased run time and license usage)
22FDX Automated Bias Voltage Exploration
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Architecture Expeditious Mode (Minimizes Run Time and License Usage)
Block 1
Block 3
Block 2
Top
Block 1 Block 2 Block 3 Bias Voltage
RBB RBB RBB 0,0
RBB RBB RBB 0,-1
RBB RBB RBB 1,-2
FBB FBB FBB 0,0
FBB FBB FBB 0,-1
FBB FBB FBB 1,-2
1 2 3 4 5 6
Start
End
6 synthesis runs, for the number of blocks in design with same Bias Mode & Bias Voltage 3 Forward Bias and 3 Reverse Bias netlists are generated, regardless of number of blocks in design Each netlist is analyzed for FBB/RBB mode, with one of the possible body bias voltages on bias power
nets, while other constraints remain constant
22FDX: Bias Voltage Exploration
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Expeditious Mode: Introduction to Example Design Step 1 Create Six (6) different design netlists by compiling design with each of the body biases (FBB/RBB)
1
6
Block Level Power Domain
(pd_bias_1)
Block Level Power Domain
(pd_bias_2)
Top Power Domain (pd_bias_0)
22FDX: Bias Voltage Exploration
Block 1 Block 2 Block 3 Bias Voltage
RBB RBB RBB 0,0
RBB RBB RBB 0,-1
RBB RBB RBB 1,-2
FBB FBB FBB 0,0
FBB FBB FBB 0,-1
FBB FBB FBB 1,-2
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Block 1 Block 2 Block 3 Bias Voltage
RBB RBB RBB 0,0
RBB RBB RBB 0,-1
RBB RBB RBB 1,-2
FBB FBB FBB 0,0
FBB FBB 0,-1
FBB FBB FBB 1,-2
Expeditious Mode: Introduction to Example Design Step 2 Analyze design with each individual body biases and Extract data for each Power domain
22FDX: Bias Voltage Exploration
Analyze each netlist for the specific body
bias
Extract power/performance
data for analysis
At Power domain level, Compare QOR of all 6 Runs and pick best Bias Mode/Voltage combination
1
6
Block Level Power Domain
(pd_bias_1)
Block Level Power Domain
(pd_bias_2)
Top Power Domain (pd_bias_0)
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Expeditious Mode: Analysis Process Terminology (Configuration)
FRR-00-0M1-1M2
F 00 1M2 0M1 R R
Block Level Power Domain
(pd_bias_1)
Block Level Power Domain
(pd_bias_2)
Top Power Domain (pd_bias_0)
F 00
R 0M1 R 1M2
Bias Mode
F Forward Back Bias (FBB)
R Reverse Back Bias (RBB)
Bias Voltage
VNW VPW
00 0 volts 0 volts 0M1 0 volts -1 volts
1M2 1 volts -2 volts
22FDX: Bias Voltage Exploration
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After synthesis finishes, flow generates CSV reports and Lynx Plots for each power domain for data analysis Provides optimum configuration based on different QOR parameters
Reports recommendation for each power domain based on user controllable Worst Negative Slack (WNS) range. Algorithm gives priority to timing, over area and power, for each power domain
Optimum configuration recommendation based on Total Power Cell Area / Design Area Area Relaxation Factor (Area Tuning to get better Area/Power Trade-offs) Power Relaxation Factor (Power Tuning to get better Power/Area Trade-offs) Power Delay Product (PDP)
Expeditious Mode Analysis 22FDX: Bias Voltage Exploration
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All the reports control are in Project setup file User can adjust relaxation factor and WNS range to explore results
o No need to run the utility again, Single task will generate these reports o Reports generation takes very minimal time
Default WNS range of (-50 50) ps and Area and Power Relaxation Factor of 15% are chosen for the QOR selection criteria for each Power Domain.
Expeditious Mode Reporting Structure Additional features 22FDX: Bias Voltage Exploration
########################################################################################### ## Variables to report optimum configurations based on different parameters ########################################################################################### ## Provide the list which represents the minimum and maximum ranges set GFVAR_WNS_MINIMUM_RANGE "-50" set GFVAR_WNS_MAXIMUM_RANGE "50" ## Provide the area relaxation factor in % to find the % change in power ## Please provide only positive values, for example 15 denotes 15% degradation from least area value set GFVAR_AREA_RELAXATION_PERCENTAGE "15" ## Provide the power relaxation factor in % to find the % change in area ## Please provide only positive values, for example 15 denotes 15% degradation from least power value set GFVAR_POWER_RELAXATION_PERCENTAGE "15"
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Example report from Power Domain Analysis
Bias_0 Power Domain (TOP)
Netlist Scenario_name
Bias_type-Bias_voltage(VNW-VPW) Path_Delay(pS)
Leakage_Power(mW)
Total_power(mW)
Power_delay_product (mW*pS) WNS(pS)
Cell_Area (um*um)
FBB_FBB_FBB_0P00V-0P00V FFF-00-00-00 F-00 304.68239 0.035062 0.707551 215.57833 9.43512 1202.34 FBB_FBB_FBB_0P00V-M1P00V FFF-0M1-0M1-0M1 F-0M1 264.58804 0.077056 0.76144 201.467914 64.9789 1152.819 FBB_FBB_FBB_1P00V-M2P00V FFF-1M2-1M2-1M2 F-1M2 218.53572 0.282 0.992565 216.910905 20.7421 1117.875 RBB_RBB_RBB_0P00V-0P00V RRR-00-00-00 R-00 356.69224 0.021242 0.685507 244.515025 0.247803 1223.839 RBB_RBB_RBB_0P00V-M1P00V RRR-0M1-0M1-0M1 R-0M1 374.76509 0.022149 0.699383 262.104335 -0.07495 1182.571 RBB_RBB_RBB_1P00V-M2P00V RRR-1M2-1M2-1M2 R-1M2 403.68593 0.009115 0.67793 273.670805 -203.946 1227.699
Control on WNS Range (min >= WNS = WNS
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Example report from Power Domain Analysis
Control on WNS Range (min >= WNS = WNS
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Example report from Power Domain Analysis
Bias_0 Power Domain (TOP)
Netlist Scenario_name
Bias_type-Bias_voltage(VNW-VPW) Path_Delay(pS)
Leakage_Power(mW)
Total_power(mW)
Power_delay_product (mW*pS) WNS(pS)
Cell_Area (um*um)
FBB_FBB_FBB_0P00V-0P00V FFF-00-00-00 F-00 304.68239 0.035062 0.707551 215.57833 9.43512 1202.34 FBB_FBB_FBB_0P00V-M1P00V FFF-0M1-0M1-0M1 F-0M1 264.58804 0.077056 0.76144 201.467914 64.9789 1152.819 FBB_FBB_FBB_1P00V-M2P00V FFF-1M2-1M2-1M2 F-1M2 218.53572 0.282 0.992565 216.910905 20.7421 1117.875 RBB_RBB_RBB_0P00V-0P00V RRR-00-00-00 R-00 356.69224 0.021242 0.685507 244.515025 0.247803 1223.839 RBB_RBB_RBB_0P00V-M1P00V RRR-0M1-0M1-0M1 R-0M1 374.76509 0.022149 0.699383 262.104335 -0.07495 1182.571 RBB_RBB_RBB_1P00V-M2P00V RRR-1M2-1M2-1M2 R-1M2 403.68593 0.009115 0.67793 273.670805 -203.946 1227.699
Control on WNS Range (min >= WNS = WNS
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Example report from Power Domain Analysis
Bias_0 Power Domain (TOP)
Netlist Scenario_name
Bias_type-Bias_voltage(VNW-VPW) Path_Delay(pS)
Leakage_Power(mW)
Total_power(mW)
Power_delay_product (mW*pS) WNS(pS)
Cell_Area (um*um)
FBB_FBB_FBB_0P00V-0P00V FFF-00-00-00 F-00 304.68239 0.035062 0.707551 215.57833 9.43512 1202.34 FBB_FBB_FBB_0P00V-M1P00V FFF-0M1-0M1-0M1 F-0M1 264.58804 0.077056 0.76144 201.467914 64.9789 1152.819 FBB_FBB_FBB_1P00V-M2P00V FFF-1M2-1M2-1M2 F-1M2 218.53572 0.282 0.992565 216.910905 20.7421 1117.875 RBB_RBB_RBB_0P00V-0P00V RRR-00-00-00 R-00 356.69224 0.021242 0.685507 244.515025 0.247803 1223.839 RBB_RBB_RBB_0P00V-M1P00V RRR-0M1-0M1-0M1 R-0M1 374.76509 0.022149 0.699383 262.104335 -0.07495 1182.571 RBB_RBB_RBB_1P00V-M2P00V RRR-1M2-1M2-1M2 R-1M2 403.68593 0.009115 0.67793 273.670805 -203.946 1227.699
Control on WNS Range (min >= WNS = WNS
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Control on WNS Range (min >= WNS = WNS
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Agenda
What is GLOBALFOUNDRIES 22FDX Technology?
Body-Biasing: A New Dimension in Design Closure
Automation of Design Planning
Body Bias Voltage Exploration Flow Details
Results
Conclusion
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Output CSV report provides optimum configuration for each power domain in the design, based on extracted data for all parameters
User chooses desired configuration per requirement for final synthesis run Example: Based on Cell Area
Power Domain Level Analysis Reports
Analysis Parameters Optimum configuration Recommendation for All Blocks
Summary
Based on Total Power RRR-00-00-00 Minimum Total Power within specified WNS range "-50 50"
Based on Cell Area FFF-1M2-1M2-00 Minimum Cell Area within specified WNS range "-50 50"
Based on Area Relaxation Factor RFR-00-0M1-00 Best Configuration within specified WNS range "-50 50, with 15% Area Relaxation Factor
Based on Power Relaxation Factor RFF-0M1-0M1-00 Best Configuration within specified WNS range "-50 50, with 15% Power Relaxation Factor
Based on PDP FRR-00-00-0M1 Minimum PDP within specified WNS range "-50 50"
22FDX: Results Expeditious Mode Results
FFF-1M2-1M2-00
Pd_Bias_0 :F-1M2 Pd_Bias_1 :F-1M2 Pd_Bias_2 :F-00
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Block 1
Block 3
Block 2
Top
Block 1
Block 2
Block 3
Comments
RBB RBB RBB All Blocks RBB
RBB RBB FBB 2 Blocks RBB
RBB FBB RBB 2 Blocks RBB
RBB FBB FBB 1 Blocks RBB
FBB RBB RBB 1 Blocks FBB
FBB RBB FBB 2 Blocks FBB
FBB FBB RBB 2 Blocks FBB
FBB FBB FBB All Blocks FBB
8 1 2 3 4 5 6 7
Start
End
Synthesis uses any one of the possible bias voltage values for each of the blocks (single scenario SYN) Synthesis result creates 8 (2N) different netlists Each netlist is analyzed in MCMM Mode for 27 (3N) scenarios
8 netlists * 27 scenarios = 216 total combinations
22FDX: Bias Voltage Exploration Architecture Comprehensive Mode (Increased Run Time and License Usage) MCMM Analysis
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To determine optimum configuration, two levels of analysis are performed Power Domain level Analysis
Power/Performance analyzed at sub-block level Top Design level Analysis
Power/Performance analyzed at top design level
22FDX: Bias Voltage Exploration Comprehensive Mode Analysis
Path Delay
Top Power Domain (pd_bias_0)
Block Level Power Domain (pd_bias_2)
Block Level Power Domain (pd_bias_1)
Path Delay indicative of speed of a particular power domain in a given Bias configuration
Power Domain Analysis
For each domain average of arrival time for each Reg to Reg path
Top Design Level analysis Average of all Reg to Reg paths in
design
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Provides Power Domain level analysis reports Optimum configuration for all blocks (power domains) in the design Based on calculated QOR data for different parameters
Also generates Top Design level analysis report:
Top Level Analysis Report Analysis Parameters Optimum configurations
Recommendation for All Blocks
Summary
Based on Total Power RFF-1M2-00-00 Minimum Total Power within specified WNS range "-50 50"
Based on Cell Area FFF-1M2-00-00 Minimum Cell Area within specified WNS range "-50 50"
Based on Area Relaxation Factor RFF-1M2-00-00 Best Configuration within specified WNS range "-50 50, with 15% Area Relaxation Factor
Based on Power Relaxation Factor FFF-0M1-0M1-1M2 Best Configuration within specified WNS range "-50 50, with 15% Power Relaxation Factor
Based on PDP RFR-1M2-00-00 Minimum PDP within specified WNS range "-50 50"
22FDX: Results Comprehensive Mode Results
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Agenda
What is GLOBALFOUNDRIES 22FDX Technology?
Body-Biasing: A New Dimension in Design Closure
Automation of Design Planning
Body Bias Voltage Exploration Flow Details
Results
Conclusion
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GF 22 FDX Digital Design Reference Flow
Std cell lib PDK
Color-Aware DFM-Aware Variability-Aware
Path Depth
Varia
bilit
y
Includes sample block tested at all RTL-to-GDS
steps with Sign-off
Tape-out proven Flow
FDSOI-Aware Implant-Aware
Conclusion Bias Voltage design with GLOBALFOUNDRIES 22FDX technology is a new dimension
in Power, Performance and Area tuning Optimum Configuration Recommendations help designers meet their design targets and
reduce turnaround time Bias Voltage Exploration utility enables automated design exploration for optimal PPA
Available as Makefile based standalone utility, as well within Synopsys Lynx Environment Included with GLOBALFOUNDRIES Digital Implementation Reference Flow Design for 22FDX
Design example is ready for download @GLOBALFOUNDRIES FoundryView
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Acknowledgement
GLOBALFOUNDRIES Santa Clara:
Synopsys: Prabuddh Kumar / Josefina Hobbs / Gary Rudolph
Richard Trihy
Haritez Narisetty
Pratik Rajput
Ramya Srinivasan
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Thank You
Automated Bias Voltage Design Exploration to Achieve Optimal Power, Performance and Area (PPA) for GLOBALFOUNDRIES 22FDX TechnologyAgenda22FDX Technology22FDX TechnologyIoT/Sensor Market22FDX Example:22FDX:Agenda22FDX Body-Biasing22FDX Body-Biasing22FDX Body-Biasing22FDX Body-BiasingFor more information on 22FDXAgendaSlide Number 15AgendaSlide Number 1722FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: Bias Voltage ExplorationAgenda22FDX: Results22FDX: Bias Voltage Exploration22FDX: Bias Voltage Exploration22FDX: ResultsAgendaConclusionAcknowledgementSlide Number 37