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BackSpace: Formal Analysis for Post-Silicon Debug
Flavio M. de Paula*
Marcel Gort *, Alan J. Hu *, Steve Wilton *, Jin Yang+
* University of British Columbia+ Intel Corporation
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Outline
Motivation Current Practices BackSpace – The Intuition Proof-of-Concept Experimental Results (Recent Experiments) Conclusions and Future Work
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Motivation
Chip is back from fab! Screened out chips w/ manufacturing defects
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Motivation
Chip is back from fab! Screened out chips w/ manufacturing defects
A bring-up procedure follows: Run diagnostics w/o problems, everything looks fine!
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Motivation
Chip is back from fab! Screened out chips w/ manufacturing defects
A bring-up procedure follows: Run diagnostics w/o problems, everything looks fine! But, the system becomes irresponsive while running
the real application…
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Motivation
Chip is back from fab! Screened out chips w/ manufacturing defects
A bring-up procedure follows: Run diagnostics w/o problems, everything looks fine! But, the system becomes irresponsive while running
the real application… Every single chip fails in the same way (1M DPM: Func. bugs)
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Motivation
Chip is back from fab! Screened out chips w/ manufacturing defects
A bring-up procedure follows: Run diagnostics w/o problems, everything looks fine! But, the system becomes irresponsive while running
the real application… Every single chip fails in the same way (1M DPM: Func. bugs)
What do we do now?
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Current Practices
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Scan-out buggy state
Inputs
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Current Practices
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Scan-out buggy state
But, cause is not obvious!!!
Inputs
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Current Practices
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Guess when to stop and single step
?? ?
Scan-out
Inputs
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Current Practices
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?
Non-buggy path
Problems: Single-stepping interference;Non-determinism;Too early/late to stop?
Inputs
Guess when to stop and single step
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Current Practices
Leveraging additional debugging support: Trace buffer of the internal state
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Current Practices
Leveraging additional debugging support: Trace buffer of the internal state
Provides only a narrow view of the design, e.g., program counter, address/data fetches
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Current Practices
Leveraging additional debugging support: Trace buffer of the internal state
Provides only a narrow view of the design, e.g., program counter, address/data fetches
Record all I/O and replay Solves the non-determinism problem, but… Requires highly specialized bring-up systems
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Current Practices
Leveraging additional debugging support: Trace buffer of the internal state
Provides only a narrow view of the design, e.g., program counter, address/data fetches
Record all I/O and replay Solves the non-determinism problem, but… Requires highly specialized bring-up systems
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Just having additional hardware does NOT solve the problemJust having additional hardware does NOT solve the problem
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A Better Solution: BackSpace
Goal: Avoid guess work Avoid interfering with the system Run at speed Portable debug support Compute an accurate trace to the bug
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Requires: Hardware:
Existing test infrastructure and scan-chains; Breakpoint circuit; Good signature scheme;
Software: Efficient SAT solver; BackSpace Manager
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A Better Solution: BackSpace
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Non-buggy path
Inputs
1. Run at-speed until hit the buggy state
A Better Solution: BackSpace
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Non-buggy path
Inputs
1. Run at-speed until hit the buggy state
A Better Solution: BackSpace
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Non-buggy path
Inputs
1. Run at-speed until hit the buggy state
A Better Solution: BackSpace
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Non-buggy path
Inputs
1. Run at-speed until hit the buggy state
A Better Solution: BackSpace
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Inputs
2. Scan-out buggy state and history of signatures
A Better Solution: BackSpace
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Inputs
A Better Solution: BackSpace
FormalEngine
3. Off-Chip Formal Analysis
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Inputs
4. Off-Chip Formal Analysis - Compute Pre-image
A Better Solution: BackSpace
FormalEngine
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Inputs
5. Pick candidate state and load breakpoint circuit
A Better Solution: BackSpace
FormalEngine
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Inputs
6. Run until hits the breakpoint
A Better Solution: BackSpace
FormalEngine
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Inputs
7. Pick another state
A Better Solution: BackSpace
FormalEngine
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Inputs
7. Run until hits the breakpoint
A Better Solution: BackSpace
FormalEngine
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Inputs
7. Run until hits the breakpoint
A Better Solution: BackSpace
FormalEngine
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Inputs
A Better Solution: BackSpace
Computed trace of length 2
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Inputs
A Better Solution: BackSpace
7. Iterate
FormalEngine
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Inputs
8. BackSpace trace
A Better Solution: BackSpace
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Outline
Motivation Current Practices BackSpace – The Intuition Proof-of-Concept Experimental Results Recent Experiments Future Work
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Proof-of-Concept Experimental Results
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SAT Solver
Chip on Silicon
BackSpace Manager
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Proof-of-Concept Experimental Results
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SAT Solver
Logic Simulator
BackSpace Manager
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Proof-of-Concept Experimental Results Setup:
OpenCores’ designs: 68HC05: 109 latches oc8051 : 702 latches
Run real applications
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Proof-of-Concept Experimental Results Can we find a signature that reduces the size
of the pre-image? Experiment:
Select 10 arbitrary ‘crash’ states on 68HC05; Try different signatures
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Signature Size vs.States in Pre-Image
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Proof-of-Concept Experimental Results How far can we go back? Experiment:
Select arbitrary ‘crash’ states: 10 for each 68HC05 and oc8051;
Set limit to 500 cycles of backspace; Set limit on size of pre-image to 300 states; Compare the best two types of signature;
Hand-picked Universal Hashing of entire state
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68HC05 w/ 38-Bit Manual Signature
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68HC05 w/ 38-Bit Manual Signature
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68HC05 w/ 38-Bit Universal Hashing
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8051 w/ 281-Bit Manual Signature
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8051 w/ 281-Bit Universal Hashing
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Proof-of-Concept Experimental Results Results
Signature: Universal Hashing Small size of pre-images All 20 cases successfully BackSpaced to limit
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Proof-of-Concept Experimental Results Breakpoint Circuitry
40-50% area overhead. Signature Computation
Universal Hashing naïve implementation results in 150% area overhead.
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Recent Experiments OpenRisc 1200:
32-bit RISC processor; Harvard micro-architecture; 5-stage integer pipeline; Virtual memory support; Total of 3k+ latches
BackSpace implemented in HW/SW AMIRIX AP1000 FPGA board (provided by CMC) Board mimics bring-up systems Host-PC: off-chip formal analysis
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Recent Experiments
BackSpacing OpenRisc 1200: Running simple software application Backspaced for hundreds of cycles Demonstrated robustness in the presence of
nondeterminism
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Conclusions & Future Work
Introduced BackSpace: a new paradigm for post-silicon debug
Demonstrated it works
Main challenges: Find hardware-friendly & SAT-friendly signatures Minimize breakpoint circuitry overhead
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Dfn. BackSpaceable Design
1) Augmented Machine Given , where is the set of states,
Define the signature generator as
where is the set of states, , Construct an augmented machine MA such that:
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Dfn. BackSpaceable Design
2) BackSpaceable State A state (s’,t’) of augment state machine MA is
backspaceable if its pre-image projected onto 2S is unique.
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Dfn. BackSpaceable Design
3) BackSpaceable Machine An augmented machine MA is backspaceable iff
all reachable states are backspaceable. A state machine M is backspaceable iff it can be augmented into a state machine MA for which all reachable states are reachable.
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Crash State History Algorithm
Given state (s0,t0) of a backspaceable augmented state machine MA, compute a finite sequence of states (s0,t0), (s1,t1),… as follows: Since MA is backspaceable, let si+1 be the unique
pre-image state (on the state bits) of (si,ti).
Run MA (possibly repeatedly) until it reaches a state (si+1,x). Let ti+1 = x.
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Theorem (Correctness)
If started at a reachable state, the sequence of states computed by the preceding algorithm is the (reversed) suffix of a valid execution of M.
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Theorem (Probabilistic Termination)
If the forward simulation is random, then with probability 1, the preceding algorithm will reach an initial state.