slide 1 of 30
© D.A. Johns, K. Martin, 1997
University of Toronto
Basic Opamp Designand Compensation
David Johns and Ken MartinUniversity of Toronto
slide 2 of 30
© D.A. Johns, K. Martin, 1997
pgn concepts
Vout
University of Toronto
Two-Stage CMOS Opam • Useful for describing many opamp desi • Still used for low voltage applications
A1 –A2 1
Differentialinput stage
Secondgain stage
Outputbuffer
Vin
Ccmp
slide 3 of 30
© D.A. Johns, K. Martin, 1997
p
Q9
Q8
Q6
Q7
300
300
Vout
500
500
source Outputtage buffer
University of Toronto
Two-Stage CMOS OpamQ11
Q12
Q13Q15
Q14
Q5
Q3 Q4
Q2Q1
Rb
CC
VDD
2525
25 25
25100
300
300300
150 150
Q16
Q10
Vin– Vin+
Bias circuitry Differential-input Common-
VSS
first stage second s
all transistor lengths = 1.6 um
Ibias
slide 4 of 30
© D.A. Johns, K. Martin, 1997
itive loadse 1 and 2
(1)
(2)
(3)
WL-----
1
I bias
2-----------
University of Toronto
Opamp Gain • 3rd stage NOT included if driving capac • Typical gains of 50-100 for each of stag
First Stage
• Differential to single-ended
Second Stage
• Common-source gain
Av1 g– m1 rds2 rds4||( )=
gm1 2µ pCoxWL-----
1I D1 2µ pCox
= =
Av2 g– m7 rds6 rds7||( )=
slide 5 of 30
© D.A. Johns, K. Martin, 1997
0.9)
(4)
als zero if
s9------
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Opamp GainThird Stage
• Source follower • Typical gain — slightly less than 1 (say
• Note — and
• is body-effect conductance and equsource tied to substrate
• is the load conductance at output
gds 1 rds⁄= GL 1 RL⁄=
Av 3
gm8
GL gm8 gs8 gds8 gd+ + + +---------------------------------------------------------------------≅
gs
GL
slide 6 of 30
© D.A. Johns, K. Martin, 1997
A3 vout
A2+ )
A3 1≅
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Frequency ResponseQ5
Q3 Q4
Q2Q1
300
300300
150
150
vin–
vin+
Vbias
–A2
CCv1
i = gm1 vin
v2
Ceq CC 1(=
slide 7 of 30
© D.A. Johns, K. Martin, 1997
ain freq
ensation)
(5)
(6)
(7)
(8)
University of Toronto
Frequency Response • dominates at all freq except unity-g
• Ignore for now (used for lead comp
• Miller effect results in
• At midband freq
• Overall gain (assuming )
resulting in a unity-gain frequency of
CC
Q16
Ceq CC 1 A2+( )=( ) CC A2≅
A1 gm1Zout gm1 sCC A2( )⁄= =
A3 1≅
Av s( ) A2A1 gm1 sCC( )⁄= =
ωta gm1 CC⁄=
slide 8 of 30
© D.A. Johns, K. Martin, 1997
Freqωta
ta gm1 CC⁄≅
e
Freqωta
(log)
(log)
University of Toronto
Freq Response • First-order model
20 A1A2( )logGain(dB)
0
ω
-20 dB/decad
Phase(degrees)
0
180–
90–
ωp1
ωp1
slide 9 of 30
© D.A. Johns, K. Martin, 1997
gnal large
(9)
sistors
2I D1
CC------------
oxWL-----
1I D1
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Slew Rate • Max rate output changes when input si • All Q5 bias current goes into Q1 or Q2
is nominal bias current of input tran
• Using and
SRd vout
d t------------
max
≡I CC max
CC-------------------
I D5
CC--------= = =
I D1
CC gm1 ωta⁄= gm1 2µ pC=
slide 10 of 30
© D.A. Johns, K. Martin, 1997
(10)
en power diss.
channel input
ff 1ωta
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Slew Rate
where
• Normally, little control over for a giv
• Increase slew-rate by increasing
• This is one of main reasons for using p-stage — higher slew-rate
SR2I D1
2µ pCox W L⁄( )1I D1
-----------------------------------------------------ωta V e= =
V eff 1
2I D1
µ pCox W L⁄( )1------------------------------------=
ωta
V eff 1
slide 11 of 30
© D.A. Johns, K. Martin, 1997
genot exist,
(11)
uals Q6
(12)
(13)
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Systematic Offset Volta • To ensure inherent offset voltage does
design should satisfy
• Ensures nominal current through Q7 eq • Found by noting
and
then setting
W L⁄( )7
W L⁄( )4-------------------- 2
W L⁄( )6
W L⁄( )5--------------------=
I D5 2I D3 2I D4= =
V GS7 V DS3 V GS4= =
I D7 I D6=
slide 12 of 30
© D.A. Johns, K. Martin, 1997
t Stagean n-channelnel stage
nt, isr max gain)nductance ofnity-gain freqe trapped —ise
n of chargeis lowered by
V eff
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N-Channel or P-Channel Inpu • Can also build complement opamp with
input diff pair and second-stage p-chan
P-channel Advantages
• Higher slew-rate — For fixed bias currelarger (assuming similar widths used fo
• Higher unity-gain freq — higher transcosecond stage which is proportional to u
• Lower 1/f noise — holes less likely to bp-channel transistors have lower 1/f no
N-channel Advantage
• Lower thermal noise — due to excitatiocarriers in the channel — thermal noisehigh transconductance of first stage
slide 13 of 30
© D.A. Johns, K. Martin, 1997
independent
Vout s( )
C2
VoutA s( )
βC2
C1 C2+-------------------=
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Opamp Compensation
• Feedback circuit assumed to be freq
A s( )
β
Vin s( )
β
R2
R1Vout
A s( )
C1
βR1
R1 R2+------------------=
slide 14 of 30
© D.A. Johns, K. Martin, 1997
tion
(14)
r-freq poles.
with –135°r –45° due to
(15)
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General Opamp Compensa • Model by
• — first dominant-pole frequency
• — pole frequency modelling highe
• found from simulation — frequencyphase shift (–90° due to and anothehigher-frequency poles and zeros)
• Closed loop gain given by
A s( )
A s( )A0
1 s ωp1⁄+( ) 1 s ωeq⁄+( )------------------------------------------------------------=
ωp1
ωeq
ωeqωp1
ACL s( ) A s( )1 βA s( )+------------------------=
slide 15 of 30
© D.A. Johns, K. Martin, 1997
tion
(16)
uation
(17)
(18)
s2
0) ωp1ωeq( )----------------------------
----------------------------
s2
ω02
---------+
--------------
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General Opamp Compensa
where
• Compare to a general second-order eq
ACL s( )ACL0
1s 1 ωp1⁄ 1 ωeq⁄+( )
1 βA0+----------------------------------------------
1 βA+(--------------------+ +
-----------------------------------------------------------------------------------=
ACL0 A0 1 βA0+( )⁄= 1 β⁄≅
H 2 s( )Kω0
2
s2 ω0
Q------
s ω02
+ +
---------------------------------------- K
1 sω0Q-----------+
----------------------= =
% overshoot 100e
π–
4Q2
1–-----------------------
=
slide 16 of 30
© D.A. Johns, K. Martin, 1997
tion
(19)
(20)
se-margin we
(21)
nity-gain freq
(22)
p1ωeq
p1------
ωeq⁄ )--------------
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General Opamp Compensa • Equating 2 equations above results in
• To find relationship between and phalook at the loop gain,
• To find a relationship for the loop-gain u
ω0 1 βA0+( ) ωp1ωeq( ) βA0ω≅=
Q1 βA0+( ) ωp1ωeq⁄1 ωp1⁄ 1 ωeq⁄+
---------------------------------------------------=βA0ω
ωeq--------------≅
QLG s( )
LG s( ) βA s( )βA0
1 s ωp1⁄+( ) 1 s+(----------------------------------------------= =
LG jωt( ) 1=
slide 17 of 30
© D.A. Johns, K. Martin, 1997
tion
(23)
(24)
with
ωp1
ωt ωeq⁄
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General Opamp Compensa • And rearrange and use approx that
so that
• Would also like to relate phase-marginand Q factor
ωt »
βA0ωp1
ωeq-------------------
ωt
ωeq--------
1ωt
ωeq--------
2+=
Qωt
ωeq--------
1ωt
ωeq--------
2+=
slide 18 of 30
© D.A. Johns, K. Martin, 1997
ta
Freqta
(log)
Freq(log)
GM(gain margin)
University of Toronto
Phase-Margin
20 LG jω( )( )log
Loop Gain(dB)
0 ω
-20 dB/decade
Phase
(degrees)
0ω
180–
90–
ωp1
ωp1
Loop Gain
PM(phase margin)
slide 19 of 30
© D.A. Johns, K. Martin, 1997
tion(25)
(26)
ed,ated circuit!
Percentagevershoot for a
step input
13.3%8.7%4.7%1.4%0.008%
1 ωt ωeq⁄( )
ωt
University of Toronto
General Opamp Compensa
where adds phase shift
• If non-dominant poles remains unchangindependent of for optimally compens
PM(Phase margin) Q factor
o
55° 0.700 0.92560° 0.580 0.81765° 0.470 0.71770° 0.360 0.62275° 0.270 0.527
PM L∠ G jωt( ) 180°–( )– 90° tan––= =
ωp1 90°
ωt ωeq⁄ tan 90° PM–( )=
β
ωt ωeq⁄
slide 20 of 30
© D.A. Johns, K. Martin, 1997
pamp
300
Vout2
University of Toronto
Compensating the 2-Stage OQ5
Q3 Q4
Q2Q1
Q6
Q7
VDD300
300300
150 150300
Vin- Vin+
Vbias1
CcQ16
Vbias2
slide 21 of 30
© D.A. Johns, K. Martin, 1997
pamp
iode region.
(27)
ent, right-halfmargin
vout
C2
6
--
University of Toronto
Compensating the 2-Stage O
• has and is hard in the tr
• Small signal analysis — without presplane zero occurs and worsens phase-
gm1vin
gm7v1
v1
R1 C1
RC CC
R2
Q16 V DS16 0=
RC rds161
µnCoxWL-----
16
V eff 1
---------------------------------------------= =
RC
slide 22 of 30
© D.A. Johns, K. Martin, 1997
pamp at
(28)
pensation
(29)
(30)
RC 1 gm7⁄»
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Compensating the 2-Stage O • Including (through Q16) places zero
• Zero moved to left-half plane to aid com • Good practical choice is
satisfied by letting
since and if
RC
ωz1–
CC 1 gm7⁄ RC–( )------------------------------------------=
ωz 1.2ωt=
RC1
1.2gm1-----------------≅
ωt gm1 CC⁄≅ ω z 1 RCCC( )⁄≅
slide 23 of 30
© D.A. Johns, K. Martin, 1997
argin
re a –125°
y-gain
a phase
of times
RC 0=
55°
University of Toronto
Design Procedure1) Find CC with Rc=0 for a 55o phase m
— Arbitrarily choose pF and set
— Using SPICE, find frequency whe
phase shift exists, define gain as
— Choose new so becomes unit
frequency of the loop gain — results inmargin.
— Achieved by setting
— Might need to iterate on a coupleusing SPICE
C ′C 5≅
ωt
A ′CC ωt
CC C ′C A ′=
CC
slide 24 of 30
© D.A. Johns, K. Martin, 1997
(31)
aving zero
se at
ase CC while
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Design Procedure2) Choose RC according to
— Increases by about 20 percent, le
near final
— Check that gain continues to decreafrequencies above the new
3) If phase margin not adequate, increleaving RC constant
RC1
1.2ωtCC---------------------=
ωt
ωt
ωt
slide 25 of 30
© D.A. Johns, K. Martin, 1997
(32)
e the device
6
--
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Design Procedure4) Replace RC by a transistor
— SPICE can be used again to fine-tundimensions to optimize phase margin
RC rds161
µnCoxWL-----
16
V eff 1
---------------------------------------------= =
slide 26 of 30
© D.A. Johns, K. Martin, 1997
endenceiven by
(33)
(34)
ll track
(35)
(36)
ωp2
16-----
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Process and Temperature Indep • Can show non-dominant pole roughly g
• Recall zero given by
• If tracks inverse of then zero wi
ωp2
gm7
C1 C2+--------------------≅
ωz1–
CC 1 gm7⁄ RC–( )------------------------------------------=
RC gm7
RC rds161
µnCox W L⁄( )16V eff------------------------------------------------= =
gm7 µnCox W L⁄( )7V eff 7=
slide 27 of 30
© D.A. Johns, K. Martin, 1997
endencent of process
300
Q7
a Vb=
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Process and Temperature Indep • Need to ensure independe
and temperature variations
• First set which makes
Veff16 Veff7⁄
Q11
Q12
Q13
Q6
CC
25
25
25
300
Q16Va
Vb
Vbias
Veff13 Veff7= V
slide 28 of 30
© D.A. Johns, K. Martin, 1997
endence
(37)
(38)
16 same
(39)
(40)
13-----
W L⁄( )12
W L⁄( )13----------------------
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Process and Temperature Indep
• Since and gates of Q12 and Q
2I D7
µnCox W L⁄( )7------------------------------------
2I D13
µnCox W L⁄( )---------------------------------=
I D7
I D13-----------
W L⁄( )7
W L⁄( )13----------------------=
Va Vb=
V eff12 V eff16=
V eff 7
V eff 16---------------
V eff 13
V eff 12---------------
2I D13
µnCox W L⁄( )13--------------------------------------
2I D12
µnCox W L⁄( )12--------------------------------------
------------------------------------------= = =
slide 29 of 30
© D.A. Johns, K. Martin, 1997
iasingo a resistor
(41)
(42)
earrange
(43)
(44)
I D15RB
5
L⁄ )15-------------- I D15RB+
L⁄ 13
L⁄ 15--------------- RB=
ox W L⁄( )13I D13
L)13
L)15----------- RB⁄
University of Toronto
Stable Transconductance B •Can bias on-chip gm t
•But and r
•Recall
Q11
Q12
Q13Q15
Q14
RB
2525
25 25
25100
Q10
V GS13 V GS15 +=
2I D13
µnCox W L⁄( )13------------------------------------
2I D1
µnCox W(----------------------=
I D13 I D15=
2
2µnCox W L⁄( )13ID13
---------------------------------------------------- 1WW--–
gm13 2µnC=
gm13 2 1W ⁄(W ⁄(
-----------–=
slide 30 of 30
© D.A. Johns, K. Martin, 1997
iasingy geometric
process
(45)
lity and hence
ncreaseall 0 currents)
University of Toronto
Stable Transconductance B • Transconductance of determined b
ratios only • Independent of power-supply voltages,
parameters, temperature, etc.
• For special case
• Note that high-temp will decrease mobiincrease effective gate-source voltages
• Roughly 25% increase for 100 degree i • Requires a start-up circuit (might have
Q13
W L⁄( )15 4 W L⁄( )13=
gm131
RB------=