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Block-level Designs of Die-to-Wafer Bonded 3D ICsand Their Design Quality Tradeoffs
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu LimSpeaker: Shreepad PanthSchool of ECE, Georgia Institute of Technology, Atlanta, GA
ASPDAC 2013 (Jan 25, 2013)
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• Wafer-to-wafer bonding is a low cost process, but it requires that all dies have the same size
• In several cases, die-to-wafer bonding is more practical than wafer-to-wafer bonding and still low-cost– Memory + logic stacking– Logic-to-logic stacking when two dies are from different companies– Designs with IP blocks that may enforce different size of dies in the stack
• In near future, block-level designs are likely to be early 3D ICs on the market because the methodology allows the reuse of optimizedIP blocks
Near Future 3D ICs
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• TSV position is an important design factor that limits the quality of 3D ICs in terms of:– Performance: area, wirelength, delay, and power– Reliability: temperature and mechanical stress
• No previous work has studied the quality trade-offs between different styles of block-level layout of die-to-wafer bonded 3D ICs in a holistic manner
Related Work
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• A 2-tier 3D IC is focused in this work
• Both dies are facing down– Compatibility with popular flip-chip packaging– Heat sink attached on back side of the top die for good cooling
• Bottom die has larger footprint than top die– Large area available for C4 bumps for good power delivery
Problem Statement (I)
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• Redistribution layer (RDL)– Necessary if some TSVs in bottom die are outside the footprint of top die– Not needed if all TSVs in bottom die are inside the footprint of the top die
Problem Statement (II)
MoldingMolding
RDLTop Die
Bottom Die
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• Layout of the top die is fixed
• Study three different design styles of the bottom die– TSV-farm: dense array of TSVs in the middle of bottom die (no need for RDL)– TSV-distributed: arrays of TSVs distributed across bottom die– TSV-whitespace: TSVs inserted in whitespace nearby connecting pins
Problem Statement (III)
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• Partitioning:– Use same partition in all design styles for fair comparison
• Floorplanning:– Preplace TSVs (TSV-farm and TSV-distributed)– Postplace TSVs (TSV-whitespace)
• Timing optimization:– Set timing constraints of each die according to [Y.-J. Lee, 3DIC 2010]– Insert buffers to meet the constraints of each die separately
• Routing– Routing on each die– RDL routing (TSV-distributed and TSV-whitespace)
Design Flow
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• Area and wirelength are directly obtained from the layout of both bottom and top dies
• Delay and power are analyzed using the following flow:
Evaluation – Traditional Metrics
Top-DieParasitic RC
Top-Die DEF/GDSII
SoC Encounter
PrimeTime PX
Bottom-Die DEF/GDSII
Top-LevelTSV RC
Bottom-DieParasitic RC
Top-Level VerilogTop-DieVerilogBottom-Die
Verilog
DesignSwitchingActivity
Timing and Power of 3D ICs
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• Temperature is analyzed using the following flow:
Evaluation – Reliability MetricsTemperature (I)
Ansys FLUENT
User Defined Functions
Layout Analyzer
ThermalConductivity
VolumetricHeat Source
BoundaryConditions
Meshed Structure
Top-Die DEF/GDSIIBottom-Die DEF/GDSII TSV Position Logic Cell Power
Temperature
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Evaluation – Reliability MetricsTemperature (II)
M5
M1Poly
Bulk Si(30μm)
AdhesiveThermal Cell Width
TSV (5μm)
STIActive
TSV Liner (0.25μm)
TSV M1 Landing Pad
TSV M5 Landing Pad
Device
Contact = 5.56%Poly = 8.33%TSV = 11.11%Dielectric = 75%
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• Baseline TSV stress model from FEA simulation– Model realistic TSV structures: TSV, liner, landing pad– Obtain stress tensor from simulation result– Convert to Cartesian coordinate
Evaluation – Reliability MetricsMechanical Stress [M. Jung, DAC 2011] (I)
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡−
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡
⎥⎥⎥
⎦
⎤
⎢⎢⎢
⎣
⎡ −=
1000cossin0sincos
1000cossin0sincos
θθθθ
σσσσσσσσσ
θθθθ
θ
θθθθ
θ
zzzzr
zr
rzrrr
xyzS
Stress tensor from FEA simulation
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• Full-chip stress and reliability analysis using linear superposition
Evaluation – Reliability MetricsMechanical Stress [M. Jung, DAC 2011] (II)
TSV1 TSV2
TSV3TSV4
stress influence zone (25um)
P: point under consideration
TSV4 doesn’t affect P TSV1, TSV2, and TSV3
affect P
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• A reconfigurable computing array obtained from OpenCores
The Test Circuit
Total #gates 1,363,536#Interblock nets 1,853#TSVs 312Total #blocks 95#Blocks on top die 26#Blocks on bottom die 69
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• Baseline designs– TSV size: 10 μm– TSV pitch: 30 μm
• Small TSV (Small TSV size)– TSV size: 5 μm– TSV pitch: 30 μm
• Dense TSV (Small TSV size + narrow TSV pitch)– TSV size: 5 μm– TSV pitch: 15 μm
Experiments
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15/29Baseline – Layout in TSV-farm Style
Top DieBottom Die
TSV Farm Bonding Pads (Top Metal)
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16/29Baseline – Layout in TSV-distributed Style
RDLBottom Die
A TSV Array (to top die)Bonding Pads (to bottom die)
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17/29Baseline – Layout in TSV-whitespace Style
RDLBottom Die
Most TSVs are in whitespace
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18/29Baseline – Wirelength, Delay, and Buffers
Distributed TSV arrays interfere floorplan
Extra buffers are needed
Still slow
RDL = extra wirelength
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19/29Baseline – Power, Temperature, and Stress
Slow=
Lowpower
Distributed TSV arrayshelp reduce max temp.
High stress in small area
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20/29Baseline – Temperature Map of Bottom Die
TSV-farm TSV-distributed TSV-whitespace
Hot spotfar from
TSV farm
Only fewTSVs nearby
hot spot
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21/29Baseline – Stress Map of Bottom Die
TSV-farm TSV-distributed TSV-whitespace
TSV stress impacts area nearby the TSV
Zoom up these areas
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22/29Baseline – Stress Map of Bottom Die (Zoom-up)
TSV-farm TSV-distributed TSV-whitespace
Stress from nearbyTSVs adds up
Areas impacted byTSV stress do not
overlap much
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23/29Small TSV – Wirelength, Delay, and Buffers
SameWL
About same # buffersLittle faster(smaller TSV RC)
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24/29Small TSV – Power, Temperature, and Stress
Little more power Same temp. Much lower stress
Smaller area understress impact
Possible to narrowTSV pitch & footprint
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25/29Dense TSV – Wirelength, Delay, and Buffers
Little shorter WL Lower # buffersLitter faster
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26/29Dense TSV – Power and Temperature
Little more power About same temp.
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27/29Dense TSV – Stress
Stress is back to original values
in even smallerarea understress impact
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• A circuit is manually designed in three different styles to study trade-offs of the quality of the layouts
• TSV-farm style– Shortest wirelength and best timing– Highest average stress, but smallest impacted area
• TSV-distributed style– Longest wirelength (TSVs interfere placement)– Lowest temperature (TSVs help reduce temperature)
Conclusions
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Thank you
Questions?