Download - BUET online catalog
MODELING AND PERFORMANCEANALYSIS OF SEMICONDUCTOR ON
INSULATOR FIELD EFFECTTRANSISTORS
by
A. T. M. Golam Sarwar
MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONIC ENGINEERING
Department of Electrical and Electronic Engineering
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY
July 2011
The thesis titled “MODELING AND PERFORMANCE ANALYSIS OF SEMI-
CONDUCTOR ON INSULATOR FIELD EFFECT TRANSISTORS” submitted by
A. T. M. Golam Sarwar, Student no: 0409062249 P, Session: April, 2009 has been
accepted satisfactory in partial fulfillment of the requirement for the degree of Master
of Science in Electrical and Electronic Engineering on July 27, 2011.
Board of Examiners
1.
Dr. Quazi Deen Mohd Khosru
Professor
Department of EEE, BUET, Dhaka - 1000
Chairperson
(Supervisor)
2.
Dr. Md. Saifur Rahman
Professor
Department of EEE, BUET, Dhaka - 1000
Member
(Ex - officio)
3.
Dr. Md. Shafiqul Islam
Professor
Department of EEE, BUET, Dhaka - 1000
Member
4.
Dr. M. Rezwan Khan
Professor and Vice - Chancellor
United International University, Dhaka - 1209
Member
(External)
i
DECLARATION
It is hereby declared that this thesis or any part of it has not been submitted
elsewhere for the award of any degree or diploma.
A. T. M. Golam Sarwar
Graduate Student
Department of Electrical and Electronic Engineering,
Bangladesh University of Engineering and Technology, Dhaka - 1000, Bangladesh.
ii
DEDICATION
To my parents
iii
ACKNOWLEDGMENTS
I would like to express my sincere gratitude to my supervisor, Dr. Quazi Deen
Mohd Khosru, Professor, Department of Electrical and Electronic Engineering, BUET,
for his generous help, warm encouragement and support throughout my graduate the-
sis. Throughout my life I will be benefited from the experience and knowledge I gained
working with him.
I also wish to thank Dr. Saifur Rahman, Head, Department of Electrical and
Electronic Engineering, BUET, for creating perfect ambience to carry on my thesis
work and for his inspiration throughout my graduate session.
I am also grateful to all other people who gave me numerous suggestions through-
out the course of this thesis.
iv
ABSTRACT
Due to aggressive scaling of Metal Oxide Semiconductor Field Effect Transistors
(MOSFET), Silicon (Si) technology is expected to reach its physical performance
limit within few years. Researchers are looking for alternative materials, and alter-
native architectures for future logic and information processing devices. Ultrathin
body (UTB) fully depleted (FD) Semiconductor on Insulator is one of the promis-
ing architecture for next generation devices due to its superior performance in terms
of junction capacitance and subthreshold swing. Si has been explored as a channel
material in Semiconductor on Insulator devices, known as Silicon on Insulator (SOI)
MOSFETs. Moreover, III-V materials and Ge are being studied extensively as good
candidates to replace Si as channel material due to their high electron and high hole
mobility respectively; light electron and light hole conduction effective mass respec-
tively. In this dissertation, we mainly have focused on two issues. First, A physically
based compact surface potential model is proposed to simulate gate C-V character-
istics of UTB FD SOI devices. Quantum mechanical (QM) effects, such as, energy
quantization of inversion layer carriers, wavefunction penetration into the front and
buried oxide layers are incorporated in this model. The power law for lowest (ground)
quantized energy level versus normal electric field at oxide (E1 ∝ Foxλ) is used with λ
= 0.64 for electrons and λ = 0.6 for holes in weak and strong inversion region. Surface
potentials at three interfaces (front oxide - silicon film interface, silicon film - buried
oxide interface and buried oxide - substrate interface) are calculated using the E1 val-
ues. Substrate region is incorporated in the calculation to simulate devices with low
substrate doping. Once surface potentials at the three surfaces are know, inversion
v
and depletion charges determined to calculate gate capacitance. Computed compact
C-V characteristics are compared with self-consistent Schrodinger - Poisson simula-
tion over a range of device parameters to verify the accuracy of the model. Second,
Ballistic performance of III-V on Insulator (III-V-OI) and Ge on Insulator (GeOI)
devices with high - κ gate dielectrics have been investigated as possible replacement
in future CMOS technology as n- and p-type MOSFETs respectively. InAs and GaAs
are investigated as possible replacement for Si in n-MOSFET due to high electron
mobility and light conduction effective mass of electron. Ge is investigated as possi-
ble replacement for Si in p-MOSFET due to high hole mobility and light conduction
effective mass of hole. Numerous experimental research have been conducted on III-
V-OI and GeOI, and huge performance improvement has been reported. However, all
these devices are semiclassical devices whose transport is drift - diffusion (DD) type.
In this dissertation, we investigated the performance of scaled III-V-OI and GeOI
devices whose transport mechanism will be ballistic. To determine the ballistic drain
current, electrostatics of the devices are determined using self-consistent Schrodinger
- Poisson simulation. Once the electrostatics is known for a specific gate bias ballistic
current is calculated using the over-the-barrier transport model. Significant perfor-
mance enhancement is found in both III-V-OI and GeOI devices compared to SOI
devices.
vi
TABLE OF CONTENTS
Chapter Page
1 INTRODUCTION 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 History of MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 MORE MOORE and MORE THAN MOORE . . . . . . . . . . . . . 3
1.4 Emerging logic devices for future technology . . . . . . . . . . . . . . 3
1.5 Objective of this work . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.6 Organization of the dissertation . . . . . . . . . . . . . . . . . . . . . 13
2 A PHYSICALLY BASED COMPACT GATE C-V MODEL FOR
FULLY DEPLETED (FD) SILICON ON INSULATOR (SOI) MOS-
FET 14
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 QM Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Modeling Subband Energies in FD SOI MOSFET . . . . . . . 16
2.2.2 Modeling Surface Potentials at Depletion and Weak Inversion
Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.3 Modeling Surface Potentials at Strong Inversion Region . . . . 27
2.2.4 Transition Between Weak and Strong Inversion . . . . . . . . 29
2.2.5 Gate Voltage, Charge and Capacitance . . . . . . . . . . . . . 30
2.3 Surface Potentials at Different Interfaces of FD SOI MOSFETs . . . 32
2.4 Gate C-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
vii
3 HIGH PERFORMANCE III-V ON INSULATOR FIELD EFFECT
TRANSISTOR 55
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2 Performance Analysis of III-V on Insulator (III-V-OI) Field Effect
Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3 Effect of Strain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4 HIGH PERFORMANCE GERMANIUM ON INSULATOR FIELD
EFFECT TRANSISTOR 72
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2 Performance Analysis of Ge on Insulator Field Effect Transistor . . . 73
4.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5 CONCLUSIONS 81
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Future directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BIBLIOGRAPHY 84
A IMPORTANT TABLES 95
viii
LIST OF TABLES
Table Page
3.1 Simulation parameters for performance analysis of UTB FD III-V-OI
devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2 Decrease of inversion carrier concentration, Ninv in III-V-OI devices
compared to SOI devices at VGS = VDS = 0.8 V . . . . . . . . . . . . 63
3.3 Increase of injection velocity, Vinj in III-V-OI devices compared to SOI
devices at VGS = VDS = 0.8 V . . . . . . . . . . . . . . . . . . . . . 63
3.4 Enhancement of on current, ION in III-V-OI devices compared to Si
devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1 Simulation parameters for performance analysis of Ge UTB MOSFETs 74
4.2 Decrease of inversion carrier concentration, Ninv in GeOI devices com-
pared to SOI devices at VGS = VDS = 0.8 V . . . . . . . . . . . . . . 78
4.3 Increase of injection velocity, Vinj in GeOI devices compared to SOI
devices at VGS = VDS = 0.8 V . . . . . . . . . . . . . . . . . . . . . 79
4.4 Enhancement of on current, ION in GeOI devices compared to SOI
devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
A.1 Simulation parameters for performance analysis of III-V-OI and GeOI
MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
A.2 Quantization and DOS effective masses of electrons in Si . . . . . . . 95
A.3 Quantization and DOS effective masses of holes in Si . . . . . . . . . 96
A.4 Quantization and DOS effective masses of electrons in InAs and GaAs 96
A.5 Quantization and DOS effective masses of holes in Ge . . . . . . . . . 96
ix
LIST OF FIGURES
Figure Page
1.1 Graphical representation of Moore’s law . . . . . . . . . . . . . . . . 2
1.2 Schematic representation of MORE MOORE and MORE THAN
MOORE approach. Courtesy: International Technology Roadmap
for Semiconductors (ITRS) [1]. . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Schematic diagram of Silicon on Insulator UTB FD MOSFET. . . . . 17
2.2 Enegry band diagram of conduction band of a typical n-type FD SOI
FET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Superposition of triangular and square wells to model eigen energies of
FD SOI FET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for
longitudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi
= 25 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. 19
2.5 Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for
longitudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi
= 20 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. 19
2.6 Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for
longitudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi
= 15 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. 20
2.7 Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for
longitudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi
= 10 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. 20
x
2.8 Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for
longitudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi
= 5 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . 21
2.9 Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for
longitudinal valley electrons in an nMOSFET. Here, tox = 1 nm, tsoi
= 5 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . 21
2.10 Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 3 nm, tsoi =
25 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . 22
2.11 Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 1 nm, tsoi =
25 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . 22
2.12 Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 1 nm, tsoi =
15 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . 23
2.13 Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 1 nm, tsoi =
5 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . 23
2.14 Relative position of E1 compared to conduction band minima (CBM)
for low gate bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.15 Relative position of E1 compared to conduction band minima (CBM)
for high gate bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.16 % Occupancy vs tsoi from simulation (symbols) and eqn. 2.13 (line). . 28
2.17 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 5 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 33
xi
2.18 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 10 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 34
2.19 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 15 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 35
2.20 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 20 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 36
2.21 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 37
2.22 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 38
2.23 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 1 nm, tsoi = 25 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 39
2.24 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 1 nm, tsoi = 15 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 40
2.25 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 41
2.26 Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 42
xii
2.27 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET.
Device parameters used are: tox = 3 nm, tsoi = 5 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 44
2.28 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET.
Device parameters used are: tox = 3 nm, tsoi = 10 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 45
2.29 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET.
Device parameters used are: tox = 3 nm, tsoi = 15 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 46
2.30 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET.
Device parameters used are: tox = 3 nm, tsoi = 20 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 47
2.31 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET.
Device parameters used are: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3. . . . . . . . . . . . . . . 48
2.32 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET.
Device parameters used are: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 49
xiii
2.33 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET.
Device parameters used are: tox = 1 nm, tsoi = 25 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 50
2.34 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET.
Device parameters used are: tox = 1 nm, tsoi = 15 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 51
2.35 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET.
Device parameters used are: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 52
2.36 (a) Gate capacitance (CG) vs gate voltage (VG−VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET.
Device parameters used are: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm,
Nch = 1017 cm−3, and Nsub = 1017 cm−3. . . . . . . . . . . . . . . . . 53
3.1 Schematic diagram of III-V on Insulator field effect transistor. . . . . 57
3.2 Confinement effective mass mz of the Γ valley as a function of the
thin-film body thickness for GaAs and InAs. For both semiconductor
materials, mz increases significantly as the body thickness decreases. . 58
3.3 Inversion carrier - Voltage (Ninv − VGS) characteristics of UTB FD
III-V-OI and SOI n-type field effect transistors. . . . . . . . . . . . . 59
3.4 Capacitance - Voltage (CG−VGS) characteristics of UTB FD III-V-OI
and SOI n-type field effect transistor. . . . . . . . . . . . . . . . . . . 60
3.5 Injection velocity - Voltage (Vinj − VGS) characteristics of UTB FD
III-V-OI and SOI n-type field effect transistor. . . . . . . . . . . . . . 61
xiv
3.6 Transfer characteristics (I − V ) of UTB FD III-V-OI and SOI n-type
field effect transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.7 Drain current - Voltage (ID−VDS) characteristics of UTB FD III-V-OI
and SOI n-type field effect transistor for VGS = 0.8 V. . . . . . . . . 62
3.8 Energy band diagrams are shown with (solid lines) and without (dotted
lines) incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2
/ 5.5 nm GaAs / 25 nm SiO2 / Si for VGS - VFB = 0.1 V (a) and VGS
- VFB = 2.0 V (b). Part of the band profile in the Si substrate is not
shown here. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.9 Energy band diagrams are shown with (solid lines) and without (dotted
lines) incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2
/ 5.5 nm InAs / 25 nm SiO2 / Si for VGS - VFB = 0.1 V (a) and VGS
- VFB = 2.0 V (b). Part of the band profile in the Si substrate is not
shown here. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.10 Eigen energies are shown with (solid lines) and without (dotted lines)
incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2 / 5.5
nm GaAs / 25 nm SiO2 / Si system. . . . . . . . . . . . . . . . . . . 67
3.11 Eigen energies are shown with (solid lines) and without (dotted lines)
incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2 / 5.5
nm InAs / 25 nm SiO2 / Si system. . . . . . . . . . . . . . . . . . . . 68
3.12 Gate capacitance (a) and on current (b) are shown with (solid lines)
and without (dotted lines) incorporating strain effect for a 3.85 nm (∼
0.6 nm EOT) ZrO2 / 5.5 nm GaAs / 25 nm SiO2 / Si system. . . . . 69
3.13 Gate capacitance (a) and on current (b) are shown with (solid lines)
and without (dotted lines) incorporating strain effect for a 3.85 nm (∼
0.6 nm EOT) ZrO2 / 5.5 nm InAs / 25 nm SiO2 / Si system. . . . . . 70
xv
4.1 Schematic diagram of Ge on Insulator field effect transistor. . . . . . 74
4.2 Inversion carrier - Voltage (Ninv − VGS) characteristics of GeOI and
SOI p-type field effect transistor. . . . . . . . . . . . . . . . . . . . . 75
4.3 Capacitance - Voltage (CG − VGS) characteristics of GeOI and SOI
p-type field effect transistor. . . . . . . . . . . . . . . . . . . . . . . . 76
4.4 Injection velocity - Voltage (Vinj − VGS) characteristics of GeOI and
SOI p-type field effect transistor. . . . . . . . . . . . . . . . . . . . . 77
4.5 Transfer characteristics (I − V ) of GeOI and SOI p-type field effect
transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.6 Drain current - Voltage (ID − VDS) characteristics of GeOI and SOI
p-type field effect transistor. . . . . . . . . . . . . . . . . . . . . . . . 78
xvi
CHAPTER 1
INTRODUCTION
1.1 Introduction
Si based CMOS technology has been one of the most successful innovations in the
history of engineering. It has been dominating the semiconductor industry for last
few decades. It has become possible due to the aggressive scaling of Metal Oxide
Semiconductor Field Effect Transistor (MOSFET), the building block of computer
chips. In 1965 Gordon Moore, a co-founder of INTEL corporation, gave a prediction
popularly known as Moore’s law from his observation: The number of transistors
on a chip would double about every two years [2]. Since then, INTEL has
exponentially increased the number of transistors in a chip to realize the prediction
of Moore. Fig. 1.1 is a graphical representation of Moore’s law with INTEL’s actual
transistor count in chips.
1.2 History of MOSFET
First MOSFET was demonstrated from Bell Labs in 1959 by Dawon Kahng and
Martin M. (John) Atalla [3]. Since then it went through many evolutions. In 1968,
Poly-Si gate was introduced. To match the work function of the gate n-poly silicon
was used in n-MOSFETs and p-poly silicon was used in p-MOSFETs. In 1971,
INTEL launched first ever microprocessor in the history of mankind which contained
2250 transistors [4]. In 2002, INTEL introduceed strain silicon for high performance
MOSFET in 90 nm technology [4]. In 2007, 1st generation high-κ dielectric (HfO2)/
1
1965 1970 1975 1980 1985 1990 1995 2000 2005 2010103
104
105
106
107
108
109
1010
INTEL Transistor Count Moore's Law
Dual Core Itanium II
Itanium IIItanium
Pentium IV
Pentium III
Pentium II
Pentium486
386
286
8086
80808008
4004
N
umbe
r of T
rans
isto
rs
Year
Figure 1.1: Graphical representation of Moore’s law
metal gate microprocessor was introduced by INTEL in 45 nm technology, which
dramatically increased processor energy efficiency [4]. INTEL launched 2nd generation
of high-κmetal gate MOSFETs in 2009 using 32 nm technology; the last generation of
bulk planar MOSFET [4]. So high-κ metal gate idea can only give a four year solution
for the semiconductor industry. In 2011, INTEL has introduced 22 nm technology
tri-gate transistor for the first time to give a dramatic change in the fundamental
structure of MOSFET [4]. This new technology has enable INTEL to pursue Moore’s
law and ensure that the pace of technology advancement can continue for years to
come. So, the microprocessor which started its journey with 2250 transistors now
have more than two billions of transistors in it [4].
2
1.3 MORE MOORE and MORE THAN MOORE
Si based technology served the semiconductor industry for a long and it has reached
its fundamental physical limits. So, time has come to switch to new technology be-
yond CMOS. It seems that accommodating a new technology would not be possible
in near future. But it is necessary to continue the advancement of technology. So,
to keep the pace of technological advancement engineers take approaches known as
MORE MOORE and MORE THAN MOORE . In MORE MOORE ap-
proach, device engineers are investigating emerging devices with new materials that
can enable aggressive scaling of dimension and operating voltage for energy efficient
computing application. In MORE THAN MOORE approach, efforts have been
given to introduce more and more functionality to the devices with state-of-the-art
technology. Fig. 1.2 is a schematic representation ofMORE MOORE andMORE
THAN MOORE approach.
1.4 Emerging logic devices for future technology
To continue the technological advancement The International Technology Roadmap
for Semiconductors (ITRS) sets two specific goals [1]. First goal is to explore tech-
nologies that can replace Si channel and source drain regions with new, high mobil-
ity, high velocity materials to sustain CMOS performance gains in future technology
generations [1]. These replacement materials includes Ge, III-V compound semicon-
ductors, graphene nanoribbons, carbon nanotubes, or nanowires. The second goal is
to explore new information processing devices as dimensional scaling will approach
to fundamental physical limits. These goals can be accomplished by addressing two
technology-defining domains: 1) extending the functionality of the CMOS platform
via heterogeneous integration of these new technologies onto this platform, and 2)
stimulating invention of a new information processing paradigm.
3
Moore’s Law & More
More than Moore: DiversificationM
ore
Mo
ore
: M
inia
turi
za
tio
nM
ore
Mo
ore
: M
inia
turi
za
tio
n
Combining SoC and SiP: Higher Value System
sBaseli
ne C
MO
S:
CP
U,
Mem
ory
, L
og
icBiochips
Sensors
Actuators
HV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm...V
130nm
90nm
65nm
45nm
32nm
22nm...V
Information
Processing
Digital content
System-on-chip
(SoC)
Interacting with people
and environment
Non-digital content
System-in-package
(SiP)
Beyond CMOS
Traditional
Models[G
eo
me
tric
al
& E
qu
iva
len
t s
ca
lin
g]
Scalin
g (
Mo
re M
oo
re)
Functional Diversification (More than Moore)
HV
PowerPassives
Continuing SoCand SiP: Higher Value System
s
2009 ITRS: Overview of scaling trends
Figure 1.2: Schematic representation of MORE MOORE and MORE THAN
MOORE approach. Courtesy: International Technology Roadmap for Semiconduc-
tors (ITRS) [1].
For logic and alternative information processing technology three types of emerg-
ing device concepts are mentioned in ITRS [1].
1. ”MOSFET: Extending the Channel of MOSFETs to the End of the Roadmap”;
It contains extensions and enhancements to current MOSFETs. They are charge
based and utilize basic field effect functionality.
2. ”Charge based Beyond CMOS: Non-Conventional FETs and other Charge-
based information carrier devices”; All devices involve electron transport but
4
the switching function is inherently different from the field effect transistor and
include such effects as quantum mechanical tunneling and Coulomb blockade.
3. ”Non-FET, Non Charge-based ’Beyond CMOS Devices”; All devices involve
information carriers other than electronic charge and effect such as spin wave
interference and magnetic exchange coupling. It is likely that these technology
entries will not be suitable for general purpose computing but might be suitable
for special purpose computing such as cryptography, image processing etc.
MOSFET: Extending the Channel of MOSFETs to the End of the
Roadmap
Carbon Nanotube FETs - The primary potential advantages of Carbon Nanotube
FETs are the high mobility of charge carriers and the potential to minimize the sub-
threshold slope (i.e., minimize the short channel effects) by a surround gate geometry.
On the other hand, there are multiple challenges to achieving this, including: 1) the
ability to control bandgap, 2) growth of the nanotubes in required locations and di-
rections, 3) control of charge carrier type and concentration, 4) deposition of a gate
dielectric, and 5) formation of a low resistance electrical contact.
Graphene Nanoribbon FETs - Graphene materials offer the potential of the ex-
tremely high carrier mobilities available to CNTs (without the need for controlling
CNT chirality), combined with the promise of patterning graphene nanoribbons using
conventional processes. Work on graphene field effect transistors (FETs), while still
at an early stage, is proceeding at a rapid pace. Beginning with the first descrip-
tion of the electric field effect in graphene in 2004 [5], graphene FETs using bottom
gating, top-gating, dual-gating, and side-gating have now been demonstrated using
various combinations of exfoliated, epitaxial, stamped exfoliated, organically-grown,
and chemically-derived graphene.
The predictions of high current densities, extraordinary mobilities, and superior
5
FET performance [6,7] all with the goal of compatibility with CMOS process and tem-
perature range continue to drive the rapid pace of innovation in graphene FETs. This
innovation, accompanied by evidence of tunable Ion/Ioff via bandgaps and increasing
intrinsic carrier mobilities in the range of 7 × 104 cm2/V-s at room temperature [8]
and 2-3 × 105 cm2/V-s, at 5 K [9] is likely to bring rapid advance in this area over
the next few years.
An important problem with graphene for digital applications is its zero bandgap
which in turn will result in a very small Ion/Ioff ratio. To open up the band gap
one either has to build devices with graphene nano ribbons (d < 5 nm) or find other
methods to locally open up the bandgap. Very little is known about the transport
properties of these narrow ribbons, although passivation of the ribbon edges is a
major challenge. An important application space for graphene may be RF with
discrete elements and high linearity requirements.
Nanowire Field-Effect Transistors (NWFETs) - Nanowire field-effect transistors
are FET structures in which the conventional planar MOSFET channel is replaced
with a semiconducting nanowire. Such nanowires have been demonstrated with diam-
eters as small as 0.5 nm [10]. They may be composed of a wide variety of materials,
including silicon, germanium, various III-V compound semiconductors (GaN, AlN,
InN, GaP, InP, GaAs, InAs), II-VI materials (CdSe, ZnSe, CdS, ZnS), as well as
semiconducting oxides (In2O3, ZnO, TiO2), etc. Importantly, at low diameters, these
nanowires exhibit quantum confinement behavior, i.e., 1-D conduction, that may
permit the reduction of short channel effects and other limitations to the scaling of
planar MOSFETs. To first order the 1-D effect observed in transport is related to a
1-D density of states and leads to somewhat modified charge carrier scattering.
III-V channel replacement devices - High mobility III-V compound semiconductor
materials are attractive candidates as channel replacement materials for nMOSFETs.
However, in general, there is a trade-off between mobility and bandgap; high mobility
6
materials such as InAs have narrower bandgap. There is also a tradeoff between low
bandgap enabling lower voltage operation (to address the power/performance bal-
ance) versus excess leakage current. In addition to the narrow bandgap, the energy
difference between the lowest and the second lowest conduction bands tends to be
small, which increases the population of electrons in the second lowest conduction
band making the mobility worse [11]. Therefore, ternary compound semiconductors
such as InGaAs have attracted much attention because of their moderate bandgap
and the acceptable energy difference between the lowest and the second lowest con-
duction band minima. However, challenges for III-V channels are not only channel
material selection but also gate stacks [12, 13], stress engineering [14], growth on
Si [15, 16], surface passivation [17], and low-resistance S/D formation. A number of
high-k gate dielectrics such as ZrO2 [12], Al2O3 [17], HfO2 [17], and HfAlO [17] for use
with III-V structures have been investigated but no clear winner has emerged. Al-
though III-V materials have small piezoreistance coefficient, stress engineering does
shows a performance enhancement [14] with applied stress. Attachment of III-V
structure on Si by direct bonding [15] has been demonstrated. Although surface pas-
sivation is another major concern, it is reported that In-rich InGaAs has no Fermi-
level pinning [13, 17]. Ga-rich Ga2O3(Gd2O3)/InGaAs has a free-moving Fermi-level
near the conduction and valence-band edges [18], and Silane-Ammonia surface pas-
sivation technology makes it possible to realize interface trap density (Dit) of 1011
eV−1cm−2 [14].
Buried, short-channel III-V HEMT structures have been fabricated which show
[19,20] clear performance advantages over conventional Si MOSFETs. However, sim-
ilar III-V MOSFETs incorporating a surface-channel do not show similar improve-
ments relative to Si MOSFETs and will require significant improvements to be com-
mercially feasible. The conventional HEMT design may not be suitable for digital
applications since it may not meet the density requirements for a competitive gate
7
conductor pitch. Therefore, a self-aligned HEMT solution is required. Furthermore
the HEMT operating voltage is restricted due to excessive gate leakage
Ge channel replacement devices - Germanium as a channel replacement material
has attracted great attention because of its excellent electron and hole mobilities. In
particular, the hole mobility of strained germanium is much better than that of silicon
[21, 22]. On the other hand, because of the small bandgap, band-to-band tunneling
leakage current, or GIDL (gate-induced drain leakage) can be large. Therefore, any
potential use of Ge as a channel replacement material requires an ultrathin Ge film
in order to control the leakage [23]. The gate stack is another difficult challenge
for Ge MOSFETs. A Si cap layer is frequently used to make a good interface as
well as to reduce the electric field inside the germanium to control BTBT leakage
reduction [23]. High quality GeO2/Ge interfaces have been studied by several research
groups [24–26]. High-κ gate dielectrics such as ZrO2 and HfO2 [24] have also been
investigated. Although high hole mobility in pFETs has been demonstrated by many
research groups, electron mobility in nFETs is not very good in spite of high electron
mobility in bulk Ge. Because currently available stressed Si PMOS technology out
performs unstressed Ge based PFETs, only stressed Ge channels may be competitive.
Also Ge may not have a scaling advantage over Si because the lower bandgap will
require more graded junctions and therefore an increase of Rext. Low resistance S/D
formation is relatively easy for Ge pFETs, because of Fermi-level pinning at the
valence band edge. On the other hand, low resistance S/D formation is very difficult
for Ge nFETs. Recently, operation of short-channel Ge MOSFETs with gate lengths
less than 80 nm have been reported [24,27]. Although the progress of EOT and gate-
length scaling will be required, Ge or Ge-rich pMOSFETs are good candidates for
future generation MOSFETs. The performance of the n-channel Ge MOSFET also
needs substantial improvement.
Unconventional Geometries for FET devices - Unconventional geometries for FET
8
devices are defined as FET structure other than the conventional planar MISFET
structure. The basic operation principles for these devices are, however, very similar
to the more conventional planar MISFET case. Most of them are three-dimensional
multi-gate FETs in different configurations including vertical channel devices (Sur-
round Gate Transistor (SGT), Vertical Replacement Gate (VRG) and horizontal chan-
nel devices). Most of these devices are fabricated as Fully-Depleted (FD) channel
FETs.
Threshold voltage, Vt in multi-gate FETs can be adjusted by work function en-
gineering of the gate material, not by the channel doping. The work function engi-
neering in the gate stack is mandatory for CMOS applications to achieve proper Vt
for both n/p type channels. Due to its excellent gate controlled electrostatics, FD
channel multi-gate FETs have smaller subthreshold swing and higher punch through
immunity in the short gate length region, compared to the conventional single gate
MOSFET case. One restriction for FD channel multi-gate FETs is the channel thick-
ness. For example, the channel thickness should be less than 1/2 ∼ 2/3 of the
minimum gate length for the double gate FET. Such FD devices with thin channels,
however, will challenge junction design for Rext engineering. Even though multi-gate
FETs were first conceived and developed several years ago, first successful tri-gate
FinFET has been demonstrated in 2010 [28].
Charge based Beyond CMOS: Non-Conventional FETs and other Charge-
based information carrier devices
Tunnel FETs - Tunnel FETs are gated reverse-biased p-i-n junctions that are
expected to have OFF-ON transitions much more abrupt than conventional MOS-
FETs, whose 60-mV/dec subthreshold swing (SS) limit is set by the thermal injec-
tion of carriers from the source to the channel [29]. Band-to-band tunneling (BTBT)
is a quantum-mechanical phenomenon, expected to provide a much more abrupt
transition between ON and OFF states of a three terminal switch compared to the
9
60mV/decade MOSFET limit. Recent reports suggest that Tunnel FETs could be
also considered as promising candidates for the high performance switch, by using
appropriate heterostructure architectures [30] and/or exploiting low band-gap mate-
rials such as III-V compound semiconductors, Ge, SiGe, or graphene. Tunnel FETs
are expected to match or even outperform the speed performance of CMOS (in terms
of equivalent CV/I metrics) at the same supply voltage.
Impact Ionization MOS (IMOS) - In addition to Tunnel FETs, impact ionization
based FETs, called IMOS [31, 32], have been proposed as candidates to meet the
requirements of fundamental limit of 60 mV/dec SS, short channel effect and DIBL
effcets. Generally, low bandgap materials are used to build IMOS devices. The I-
MOS is composed of a PIN diode, whose intrinsic area is partially covered by a gate.
The attractiveness of IMOS comes from its potential co-integration with CMOS.
Spin Transistor - Spin transistors can be classified into Non-Conventional Charge-
based Extended CMOS Devices. They exhibit the transistor behavior with functions
of magnetoresistive devices. The most important feature is the control of transistor
output via spin or magnetization. Spin transistors can be divided into two categories,
i.e., spin-FET and spin-MOSFET. Although the source and drain of both the devices
are composed of a ferromagnetic material, their operating principles are quite differ-
ent. In the spin-FET, the switching operation can be achieved by spin precession
or dephasing of spin-polarized carriers injected in the channel. On the other hand,
relative magnetization configurations of the source and drain are used to modify the
output current for the spin-MOSFET.
Single-electron Transistors (SETs) - SETs are three-terminal devices that switch
on/off tunnel currents conveying electrons that are being transported one by one
from source to drain through a small island. Potentially, SETs can be applied to
general purpose Boolean logic, but significant circuit and architecture changes will
be required. SETs can potentially deliver high device density and power efficiency at
10
good speed if the issues of the large threshold voltage variation and the low current
drivability can be solved.
Negative gate capacitance FET - Based on the energy landscapes of ferroelectric
capacitors [33], it has been suggested that by replacing the standard insulator of a
MOSFET gate stack with a ferroelectric insulator of appropriate thickness it should be
possible to implement a step-up voltage transformer that will amplify the gate voltage,
thus leading to values of SS lower than 60 mV/dec and enabling low voltage/low power
operation; this device is called a negative capacitance FET. The main advantage of
such a device [33] is that it involves no change in the basic physics of the FET and
thus does not affect its current drive or impose other restrictions; thus, high Ion levels,
similar to advanced CMOS would be achievable with lower voltages.
NON-FET, NON CHARGE-BASED BEYOND CMOS DEVICES
Collective Spin Device - Ferromagnetic collective spin logic devices are a class
of alternative logic devices that use the local magnetization orientation of a domain
of a ferromagnetic material to store the computational state. In the nomenclature
adopted here, FM devices are distinct from spin devices, which are based on the
individual dynamics of spin of one or a few charge carriers. FM devices have the
potential of being non-volatile and radiation hard, which is derived from the properties
of the ferromagnetic materials themselves. While many ferromagnetic metals have
Currie temperatures well above room temperature, the Currie temperatures of most
ferromagnetic semiconductors are still limited to well below room temperature.
Moving Domain Wall Devices - Domain Wall (DW) logic devices are formed by
ferromagnetic wires in which domain walls propagate in separate regions with different
directions of magnetization.
Atomic Switch - The atomic switch is an MIM electrochemical switch that uses a
local oxidation/reduction process to form metallic nanofilaments connecting two dis-
similar metallic electrodes thereby establishing a low-resistance state. Reversal of the
11
polarity of the applied voltage enables the redox process to dissolve the nanofilaments
thereby resetting the high resistance state.
Molecular Devices - Molecular devices have remained a very active research area
with significant activity in the three principle areas of Contacts, Density functional
theory and Molecular Switching. Research in Molecular Contacts has focused on the
length-dependent changes in molecular orbital alignment and coupling with contact
states. Experimental measurements of thermopower on a series of phenylenediamines,
phenylenedithiols, and alkanedithiols were made and found to agree well with corre-
sponding calculations. In a related study, the electronic transport properties were
found to depend strongly on the nature of the contact itself (chemical bond or phys-
ical contact).
Bilayer, Pseudospintronic devices and the BiSFET in particular - Pseudo-spins
are discrete degrees of freedom other than spin which can still be treated much like
spin. There are in principle many possible forms of pseudospin and many possible
device applications. As one example, collective pseudospin effects, much like those
for spin in a ferromagnet, may be particularly interesting.
Nanomagnetic logic devices (NML formerly known as MQCA) - Nanomagnetic
devices exploit magnetic phenomena for logic based on physically-coupled single-
domain nanomagnets. This scheme is based on the shape-dependent switching of
magnetic elements, and the use of an applied magnetic-field clock for switching. A
three-input majority-logic gate, functioning as a universal nanomagnetic logic element
has been experimentally demonstrated.
1.5 Objective of this work
Silicon on insulator (SOI) devices has been studied by numerous research groups for
its superior performance in terms of junction capacitance, threshold voltage, carrier
mobility and improved subthreshold swing [34]. However, despite of many modeling
12
efforts [35–41], a quantum mechanical (QM) compact modeling of Ultrathin body
(UTB) fully depleted (FD) SOI MOSFET has not been found in the literature. So,
as one goal, a surface potential based QM compact model has been proposed and
applied to simulate gate capacitance - voltage (C-V) of UTB FD SOI FETs.
To extend the channel of MOSFET to the end of roadmap, as discussed in the
previous section, it is necessary to replace the Si channel with alternative high mobility
and high velocity materials. III-V materials is one of the prospective material to
replace Si in n-channel MOSFET due to its higher electron mobility [11,42]. Similarly,
Ge is suitable for p-channel MOSFET for higher hole mobility [11]. Ultarthin body
(UTB) fully depleted (FD) devices are amongst the alternative structure devices
that can give superior performance compared to planar devices. Many theoretical
and experimental researches have been performed on FD silicon on insulator (SOI)
devices. Recently, researcher are taking interest in heterogeneous integration of high
mobility semiconductor with Si technology. III-V materials [16] and Ge [43] have been
investigated for n- and p-type high-mobility-semiconductor on insulator devices. As
a second goal, performance of III-V materials (e.g. GaAs and InAs) and Ge have
been investigated for future generation n- and p-MOSFETs respectively.
1.6 Organization of the dissertation
In chapter 2, surface potential based compact gate C − V model is proposed. Full
theoretical analysis with detail calculations and results are presented. C-V character-
istics generated from compact model has been compared with numerical simulations.
Error curves are shown to validate the accuracy of the proposed model. Chapter 3
consists of performance analysis of III-V on insulator devices. Performance of III-V
on insulator devices are compared with its Si counterpart at a future technology node.
Effect of biaxial strain on device performance is presented as well. Similarly, chapter
5 comprises the analysis of Ge on insulator devices.
13
CHAPTER 2
A PHYSICALLY BASED COMPACT GATE C-V MODEL FOR
FULLY DEPLETED (FD) SILICON ON INSULATOR (SOI) MOSFET
2.1 Introduction
Surface potential (φs) based MOSFET models have regained it’s popularity over
last few years because of it’s consistency and accuracy in determining terminal cur-
rents and charges valid in all regions of operation [44–50]. These models are suitable
for simulating low power devices and also show better performance in modeling sub-
threshold region over the threshold voltage based models [51–57]. Most of the recently
developed φs based models are semiclassical [44–50]. However, with the aggressive
scaling of the MOSFET, quantum mechanical (QM) effects, such as, energy quan-
tization of inversion layer carriers [58] and wavefunction penetration into the gate
dielectric [59,60] started to play an important role in determining the characteristics
of the nanoscale MOSFETs. It is well known that these QM effects increase φs for
a given gate bias and a number of models have been developed to incorporate QM
effects in φs of nanoscale MOSFETs [61–64].
The silicon-on-insulator (SOI)-MOSFET is one of the promising candidates for
future high speed integrated circuit technology due to it’s reduced junction capaci-
tance and improved subthreshold swing [34]. Many φs based models, developed for
bulk MOSFETs, have been extended to model partially depleted (PD) SOI MOS-
FETs [35,36]. However, modeling of fully depleted (FD) SOI MOSFET is inherently
complicated than it’s PD counterpart due to the presence of depletion charge in the
14
substrate region. In [37–39], FD SOI models have been reported without considering
substrate depletion region. Thus these models are not applicable to FD SOI devices
with low substrate doping. In [40], Sadachika et. al reported φs based FD SOI model
considering the substrate depletion region. This model is based on iterative method
thus makes it’s application in circuit simulators unattractive. Recently Agarwal et.
al reported closed form surface potential analytical solution for all three surfaces
(gate oxide - silicon film interface (φsf), silicon film - buried oxide interface (φsb), and
buried oxide - substrate interface (φsbulk)) considering the substrate depletion in FD
SOI MOSFETs [41].
However, all these FD SOI models are semiclassical. As QM effects are becoming
very important with the scaling of nanoscale FD SOI MOSFETs, a compete model
including QM effects has become necessary to study the characteristics of nanoscale
FD SOI MOSFETs. Gate capacitance - voltage (C-V) characteristics is an important
analysis technique for electrical characterization of MOS devices as it can provide
information, such as, effective oxide thickness (EOT) of gate dielectric, fixed oxide
charge, metal - gate work function, interface traps distribution. Though numerical
simulation technique [65–67] is very popular to study gate C-V characteristics of FD
SOI devices, computationally efficient compact C-V models are necessary for circuit
simulators.
In this chapter, we are proposing a compact model to study C-V characteristics
of nanoscale FD SOI MOSFETs considering substrate depletion. In our study, we
excluded the possibility of substrate inversion. To verify the accuracy of the model,
compact C-V characteristics are compared with the C-V characteristics resulted from
self-consistent Schrodinger-Poisson simulation [65].
15
2.2 QM Model Description
2.2.1 Modeling Subband Energies in FD SOI MOSFET
Li et al. [68] showed that the 2/3 power law (triangular-potential approximation) [58]
for estimating the ground state eigenenergy of bulk MOSFET becomes inaccurate due
to (i) linear approximation of the potential profile inside Si and (ii) the negligence
of wavefunction penetration into the gate dielectric layer. Li et al. proposed a new
exponent, with the same form of [58], to calculate the ground state eigenenergy taking
into account the effects of wavefunction penetration and non-triangular potential
profile
E1 − Ec,v∼= ±γ
(
| Fox | cm
MV
)λ
. (2.1)
Where, Ec is the conduction band edge and Ev is the valence band edge at silicon-
dielectric interface, Fox is the effective oxide field, E1 is the energy of first eigen state
and λ is the modified exponent. Li et al. proposed λ =0.61 and γ =77 meV for
electrons and λ =0.64 and γ =88 meV for holes in bulk MOSFETs at inversion. For
modeling E1 in nanoscale FD SOI MOSFETs, shown in Fig. 2.1, we used the same
approach reported by Li et al. with λ = 0.64 and γ = 73 meV for electron and λ =
0.60 and γ = 104 meV for holes at inversion. Energy band diagram of conduction
band of a typical n-type FD SOI FET is shown in Fig. 2.2.
16
2
Source Drainn/p-Si
SiO2 t ox
t so
i
t box
x
y
Figure 2.1: Schematic diagram of Silicon on Insulator UTB FD MOSFET.
0 5 10 15 20 25 30 350
1
2
3
4
y (nm)
Ene
rgy(
eV)
VGS
− VFB
= 1.6 Vtox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.2: Enegry band diagram of conduction band of a typical n-type FD SOI
FET.
Fig. 2.4 - 2.9 show the ground state eigen energy (E1 − Ec) vs Front oxide field
(Fox) for longitudinal valley electrons for different device parameters in nMOSFETs.
Fig. 2.10 - 2.13 show the ground state eigen energy (E1 − Ev) vs Front oxide field
17
(Fox) for heavy holes for different device parameters in pMOSFETs. It is evident
from the results that proposed model (model of Li et al. with modified values of γ
and λ) can not predict ground state eigen enegies very precisely at low Fox for very
thin tsoi (≤5 nm). The reason behind this can be understood through the relative
position of E1 with the conduction band minima (CBM) inside the Si channel. Fig.
2.14 and 2.15 show the relative position of E1 and CBM inside Si channel for different
gate bias with inversion carrier distribution (ρinv). It is observable that for low bias
point E1 is mainly dominated by the square characteristics of the quantum well. But
for high gate bias E1 is situated in a enegry where the conduction band profile is
parabolic. As the model prosed by Li et al. is for the parabolic band profile, our
proposed model(model of Li et al. with modified values of γ and λ) can perform good
at high bias, i.e. high oxide electric field. But it is found that ground state eigen
energies at low Fox are less important in estimating gate C-V characteristics of nano-
scale MOSFETs, which is the prime goal of this chapter. However, a more accurate
modeling of eigen energies is possible considering superposition of a triangular and a
square quantum well (fig. 2.3).
Figure 2.3: Superposition of triangular and square wells to model eigen energies of
FD SOI FET.
18
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
c (eV
)
SimulationCompact
tox
= 3 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5 × 1016 cm−3
Figure 2.4: Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for longi-
tudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi = 25 nm, tbox = 25
nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3.
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
c (eV
)
SimulationCompact
tox
= 3 nmtsoi
= 20 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5 × 1016 cm−3
Figure 2.5: Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for longi-
tudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi = 20 nm, tbox = 25
nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3.
19
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
c (eV
)
SimulationCompact
tox
= 3 nmtsoi
= 15 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
Figure 2.6: Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for longi-
tudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi = 15 nm, tbox = 25
nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3.
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
c (eV
)
SimulationCompact
tox
= 3 nmtsoi
= 10 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
Figure 2.7: Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for longi-
tudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi = 10 nm, tbox = 25
nm, Nch = 1017 cm−3, and Nsub = 5× 1016 cm−3.
20
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
c (eV
)
SimulationCompact
tox
= 3 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.8: Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for longi-
tudinal valley electrons in an nMOSFET. Here, tox = 3 nm, tsoi = 5 nm, tbox = 25
nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3.
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
c (eV
)
SimulationCompact
tox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.9: Ground state eigen energy (E1 − Ec) vs Front oxide field (Fox) for longi-
tudinal valley electrons in an nMOSFET. Here, tox = 1 nm, tsoi = 5 nm, tbox = 25
nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3.
21
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
v (eV
)
SimulationCompact
tox
= 3 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.10: Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 3 nm, tsoi = 25 nm, tbox =
25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3.
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
v (eV
)
SimulationCompact
tox
= 1 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.11: Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 1 nm, tsoi = 25 nm, tbox =
25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3.
22
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
v (eV
)
SimulationCompact
tox
= 1 nmtsoi
= 15 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.12: Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 1 nm, tsoi = 15 nm, tbox =
25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3.
104
105
106
107
10−2
10−1
100
Front oxide field (V/cm)
E1−E
v (eV
)
SimulationCompact
tox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
Figure 2.13: Ground state eigen energy (E1 − Ev) vs Front oxide field (Fox) for
longitudinal valley electrons in a pMOSFET. Here, tox = 1 nm, tsoi = 5 nm, tbox =
25 nm, Nch = 1017 cm−3, and Nsub = 1017 cm−3.
23
0 2 4 6 8 10 12
0
0.1
0.2
0.3
0.4
0.5
y (nm)
Ene
rgy(
eV)
Energy bandE
1
ρinv
VGS
− VFB
= 0.8 V
Figure 2.14: Relative position of E1 compared to conduction band minima (CBM)
for low gate bias.
0 2 4 6 8 10 12
0
0.1
0.2
0.3
0.4
0.5
y (nm)
Ene
rgy(
eV)
Energy bandE
1
ρinv
VGS
− VFB
= 1.6 V
Figure 2.15: Relative position of E1 compared to conduction band minima (CBM)
for high gate bias.
24
2.2.2 Modeling Surface Potentials at Depletion and Weak Inversion Re-
gions
The 1-D poisson’s equation for the FD SOI devices shown in Fig. 2.1 is given as [53]
∂F (y)
∂y=
1
εSi(p(y)− n(y)−NA(y) +ND(y)). (2.2)
Where, F (y) is the electric field, εSi is the dielectric constant of silicon, p(y) and n(y)
are hole and electron concentration respectively, and NA(y) and ND(y) are acceptor
and donor type doping concentration respectively.
For an FD SOI n-MOSFET with constant channel doping (Nch), (2.2) can be
modified in the channel region as
∂F (y)
∂y=
q
εSi(p(y)− n(y)−Nch). (2.3)
By integrating (2.3) for depletion and weak inversion (p(y) = n(y) ≈ 0) we have
Fbox(weak) = Fox −qNchtsoi
εox. (2.4)
Where, Fox and Fbox are electric field at front oxide and buried oxide respectively, q
is the electronic charge, tsoi is the channel thickness, and εox is the dielectric constant
of the gate dielectric.
In the substrate region, (2.2) can be written as
∂F (y)
∂y= −
qNsub
εSi. (2.5)
Integrating both side of (2.5), depletion width at the substrate (Zdep(sub)) can be
25
written as
Zdep(sub) =εboxFbox(weak)
qNsub
. (2.6)
Where, Nsub is the substrate doping density and εbox is the dielectric constant of the
buried oxide layer.
From the well known F = −dφ
dy, we can derive the expression for surface potential
at buried oxide - substrate interface (φsbulk).
φsbulk(weak) =εoxFbox(weak)Zdep(sub)
2εSi. (2.7)
Substituting (2.6) to (2.7) results
φsbulk(weak) =ε2oxF
2
box(weak)
2qεSiNsub
. (2.8)
Now surface potential at the silicon film - buried oxide interface (φsb) can be deter-
mined from
φsb(weak) = φsbulk(weak) + Fbox(weak)tbox. (2.9)
Where, tbox is thickness of the buried oxide layer. From F = −dφ
dy, the expression of
surface potential at the front oxide - silicon film interface (φsf) can be written as
φsf(weak) = φsb(weak) +εoxtsoi2εSi
(Fox + Fbox(weak)). (2.10)
26
2.2.3 Modeling Surface Potentials at Strong Inversion Region
In strong inversion operation, once the eigen energies are calculated, inversion charge
density (Qs) for a given Fox can be obtained from
Qs(Fox) = −εoxFox −Qdep(Fox). (2.11)
Where, Qdep is the total depletion charge density in combined channel and substrate
region. Calculation procedure of Qdep is described in section 2.2.5. Using Fermi-Dirac
statistics and effective mass approximation we can write [69]
∓Qs(Fox) =∑
i
ηimikBT
π~2ln
(
1 + exp±[EF −Ei(Fox)]
kBT
)
(2.12)
for electrons and holes respectively (all the energies are given for electrons in eqn.
2.12). Here, ηi is the degeneracy of the ith eigen level, mi is the density of states
effective mass. It is necessary to consider only one valley and one eigenenergy state
to solve (2.12) explicitly.
To use only one eigenenergy state and a single valley in solving (2.12) occupancy
of that eigen state of the particular valley needed to be known. The percent occu-
pancy (k) of the ground state of the longitudinal valley maintains a constant nature
at inversion region of operation for a specific device parameter (not shown). This
constant nature is explained in [68] as the consequence of two opposing effects: (i)
the increase in subband splitting and (ii) the increasing degenerate nature of the
carrier distribution.
However, k weakly depends on doping density of the channel region (Nch) and
moderately depends on channel thickness (tsoi). The dependency of k on tsoi can be
modeled with an empirical equation (tsoi in eqn. 2.13 is given in nm). Fig. 2.16
27
shows the fitting of eqn. 2.13 with the simulated results.
k = 49.7 exp(−0.23 tsoi) + 38.9 exp(0.003 tsoi). (2.13)
5 10 15 20 2540
45
50
55
60
Silicon film thickness, tsoi
(nm)
% O
ccup
ancy
simulationEqn. (2.13)
Figure 2.16: % Occupancy vs tsoi from simulation (symbols) and eqn. 2.13 (line).
So (2.12) can be modified as
∓kQs(Fox) =η1m1kBT
π~2ln
(
1 + exp±[EF − E1(Fox)]
kBT
)
(2.14)
Now, (2.14) can be solved explicitly for EF −Ec,v(Fox) in terms of E1(Fox)−Ec,v(Fox)
(from eqn. 2.1) and Qs(Fox) (from eqn. 2.11) using
EF −Ec,v(Fox) = E1(Fox)−Ec,v(Fox)±kBT ln
[
exp
(
k | Qs(Fox) | π~2
η1m1kBT
)
− 1
]
(2.15)
for electrons and holes respectively. Thus the total band bending at front oxide -
silicon film interface can be calculated by
28
qφsf(strong) = [EF − Ec,v]− [EF − Ec,v(0)]. (2.16)
Where, EF −Ec,v(0) is the relative position of fermi energy at the front oxide - silicon
film thickness at flatband.
To calculate Fbox at strong inversion condition we assume the potential drop at
the front oxide - silicon interface due to depletion charge alone (φd) as same as bulk
MOSFET [68] as
qφd(Fox) = ±2qφF + [E1(Fox)−Ec,v(Fox)]. (2.17)
Where, qφF is the magnitude of the energy difference between fermi level and intrin-
sic fermi level at flatband. Then Fbox at strong inversion can be found solving the
following quadratic equation
aF 2
box(strong) + bFbox(strong) + c = 0. (2.18)
Where,
a =ε2ox
2qεSiNsub
, b = tbox +εoxtsoiεSi
, and c =qNcht
2
soi
2εSi− φd. (2.19)
From Fbox(strong), φsbulk(strong) and φsb(strong) can be obtained readily using (2.8)
and (2.9) respectively.
2.2.4 Transition Between Weak and Strong Inversion
To have a smooth transition between weak and strong inversion we have selected a
well know smoothing function that can satisfy two important characteristics.
29
1. The smoothing function must be continuous and differentiable.
2. The smoothing function must be capable to ensure that each of the approxi-
mations for weak and strong inversions is reduced smoothly to insignificance
outside of its respective region of validity.
The smoothing function is given as
φs = φs(strong)− φt ln
(
1 + exp
[
φs(strong)− φs(weak)
φt
])
. (2.20)
Where, φt =kBTq.
2.2.5 Gate Voltage, Charge and Capacitance
Once the surface potential at the interface of front oxide and silicon film at weak
(φsf(weak)) and strong (φsf(strong)) inversion are determined, gate voltage can be
calculated from
VG(weak/strong) = φsf(weak/strong) + Foxtox + VFB. (2.21)
Where, VFB is the flatband voltage. To calculate the depletion charge (Qdep) of (2.11)
we first calculate depletion charge at substrate region (Qdep(sub)) from
Qdep(sub) = −Fboxεbox, (2.22)
and then total depletion charge (Qdep) from
Qdep = Qdep(sub)− qNchtsoi. (2.23)
30
Total charge (Qtot) in the gate is given by
Qtot = εoxFox, (2.24)
gate capacitance (CG) can be calculated from
CG =∂Qtot
∂VG
. (2.25)
A FD SOI pFET can be modeled in a similar fashion.
31
2.3 Surface Potentials at Different Interfaces of FD SOI MOSFETs
In this section, we presented surface potentials at three different surfaces a) front
oxide - silicon film interface (φsf), b) silicon film - buried oxide interface (φsb), and
c) buried oxide - substrate interface (φsbulk) as a function of gate voltage (VG − VFB)
calculated from the procedure described in section 2.2 and compared them with self-
consistent simulation results and semiclassical results for both n type and p type FD
SOI MOSFETs.
Fig. 2.17 - 2.22 show φsf vs. (VG − VFB), φsb vs. (VG − VFB) and φsbulk vs.
(VG−VFB) in n type FD SOI MOSFETs and Figs. 2.23 - 2.25 show φsf vs. (VG−VFB),
φsb vs. (VG−VFB) and φsbulk vs. (VG−VFB) in p type FD SOI MOSFETs respectively.
It can be clearly observed that proposed model of section 2.2 can predict φsf more
precisely than φsb and φsbulk. As prediction of φsf is the more critical than φsb and
φsbulk for gate C-V characterization, proposed model can be used to simulate gate
C-V characteristics of nano-scale MOSFETs (verified in section 2.4).
32
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
1.2
1.4
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) φsf vs. VG − VFB
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
0 0.5 1 1.5 20
0.1
0.2
0.3
0.4
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.17: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 5 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 1017 cm−3.
33
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
1.2
1.4
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 10 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
(a) φsf vs. VG − VFB
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
0 0.5 1 1.5 20
0.1
0.2
0.3
0.4
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.18: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 10 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 5× 1016 cm−3.
34
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
1.2
1.4
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 15 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
(a) φsf vs. VG − VFB
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
0 0.5 1 1.5 20
0.1
0.2
0.3
0.4
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.19: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 15 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 5× 1016 cm−3.
35
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
1.2
1.4
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 20 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
(a) φsf vs. VG − VFB
0 0.5 1 1.5 2−0.2
0
0.2
0.4
0.6
0.8
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
0 0.5 1 1.5 2−0.1
0
0.1
0.2
0.3
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.20: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 20 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 5× 1016 cm−3.
36
−0.5 0 0.5 1 1.5 2−0.2
0
0.2
0.4
0.6
0.8
1
1.2
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5 × 1016 cm−3
(a) φsf vs. VG − VFB
−0.5 0 0.5 1 1.5 2−0.2
0
0.2
0.4
0.6
0.8
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
−0.5 0 0.5 1 1.5 2−0.1
0
0.1
0.2
0.3
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.21: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 5× 1016 cm−3.
37
0 0.5 1 1.5 20
0.2
0.4
0.6
0.8
1
1.2
1.4
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) φsf vs. VG − VFB
0 0.5 1 1.5 20
0.5
1
1.5
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
0 0.5 1 1.5 20
0.1
0.2
0.3
0.4
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.22: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
nFET for device parameters: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 1017 cm−3.
38
−2 −1.5 −1 −0.5 0−1.5
−1
−0.5
0
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) φsf vs. VG − VFB
−2 −1.5 −1 −0.5 0−1
−0.5
0
0.5
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
−2 −1.5 −1 −0.5 0−0.3
−0.2
−0.1
0
0.1
0.2
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.23: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 1 nm, tsoi = 25 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 1017 cm−3.
39
−2 −1.5 −1 −0.5 0−1.5
−1
−0.5
0
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 15 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) φsf vs. VG − VFB
−2 −1.5 −1 −0.5 0−1
−0.8
−0.6
−0.4
−0.2
0
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
−2 −1.5 −1 −0.5 0−0.4
−0.3
−0.2
−0.1
0
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.24: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 1 nm, tsoi = 15 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 1017 cm−3.
40
−2 −1.5 −1 −0.5 0−1.5
−1
−0.5
0
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) φsf vs. VG − VFB
−2 −1.5 −1 −0.5 0−1.5
−1
−0.5
0
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
−2 −1.5 −1 −0.5 0−0.4
−0.3
−0.2
−0.1
0
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.25: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 1017 cm−3.
41
−2 −1.5 −1 −0.5 0−1.5
−1
−0.5
0
VGS
− VFB
(V)
φ sf (
V)
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) φsf vs. VG − VFB
−2 −1.5 −1 −0.5 0−0.8
−0.6
−0.4
−0.2
0
VGS
− VFB
(V)
φ sb (
V)
SimulationCompactSemiclassical
(b) φsb vs. VG − VFB
−2 −1.5 −1 −0.5 0−0.2
−0.15
−0.1
−0.05
0
VGS
− VFB
(V)
φ sbul
k (
V)
SimulationCompactSemiclassical
(c) φsbulk vs. VG − VFB
Figure 2.26: Surface potential at different interfaces (φsf , φsb and φsbulk) of FD SOI
pFET for device parameters: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm, Nch = 1017
cm−3, and Nsub = 1017 cm−3.
42
2.4 Gate C-V Characteristics
In this section, compact gate capacitance (CG) vs gate voltage (VG − VFB) charac-
teristics are presented and compared with the numerical self-consistent results [65].
Device parameters are varied to ensure the acceptance of the proposed model. It
is evident that proposed model can successfully simulate gate capacitance of both
n-type and p-type FD SOI MOSFTEs in depletion and inversion regions.
Fig. 2.27 - 2.32 show CG vs (VG − VFB) characteristics for n type FD SOI MOS-
FETs and Figs. 2.33 - 2.35 show CG vs (VG − VFB) characteristics for p type FD
SOI MOSFETs respectively using proposed compact model. Each curve is accom-
panied with the semiclassical and QM self-consistent results. Percent absolute error
between the self-consistent and compact gate capacitance are also presented in the
strong inversion region.
43
0 0.5 1 1.5 20
2
4
6
8
10
12
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) CG vs. VG − VFb
1.3 1.4 1.5 1.6 1.7 1.80
0.5
1
1.5
2
2.5
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.27: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET. Device param-
eters used are: tox = 3 nm, tsoi = 5 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub =
1017 cm−3.
44
0 0.5 1 1.5 20
2
4
6
8
10
12
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 10 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
(a) CG vs. VG − VFb
1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.650
0.2
0.4
0.6
0.8
1
1.2
1.4
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.28: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET. Device param-
eters used are: tox = 3 nm, tsoi = 10 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 5× 1016 cm−3.
45
0 0.5 1 1.5 20
2
4
6
8
10
12
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 15 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5×1016 cm−3
(a) CG vs. VG − VFb
1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.650
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.29: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET. Device param-
eters used are: tox = 3 nm, tsoi = 15 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 5× 1016 cm−3.
46
0 0.5 1 1.5 20
2
4
6
8
10
12
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 20 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5 × 1016 cm−3
(a) CG vs. VG − VFb
1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.650
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.30: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET. Device param-
eters used are: tox = 3 nm, tsoi = 20 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 5× 1016 cm−3.
47
−0.5 0 0.5 1 1.5 20
2
4
6
8
10
12
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 5 × 1016 cm−3
(a) CG vs. VG − VFb
1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.650
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.31: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET. Device param-
eters used are: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 5× 1016 cm−3.
48
0 0.5 1 1.5 20
5
10
15
20
25
30
35
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) CG vs. VG − VFb
1.3 1.4 1.5 1.6 1.7 1.80.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.32: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI nFET. Device param-
eters used are: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub =
1017 cm−3.
49
−2 −1.5 −1 −0.5 00
5
10
15
20
25
30
35
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) CG vs. VG − VFb
−2 −1.8 −1.6 −1.40
0.5
1
1.5
2
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.33: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET. Device param-
eters used are: tox = 1 nm, tsoi = 25 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 1017 cm−3.
50
−2 −1.5 −1 −0.5 00
5
10
15
20
25
30
35
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 15 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) CG vs. VG − VFb
−2 −1.8 −1.6 −1.40
1
2
3
4
5
6
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.34: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET. Device param-
eters used are: tox = 1 nm, tsoi = 15 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 1017 cm−3.
51
−2 −1.5 −1 −0.5 00
5
10
15
20
25
30
35
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 1 nmtsoi
= 5 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) CG vs. VG − VFb
−1.8 −1.7 −1.6 −1.5 −1.4 −1.31
1.2
1.4
1.6
1.8
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.35: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET. Device param-
eters used are: tox = 1 nm, tsoi = 5 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub =
1017 cm−3.
52
−2 −1.5 −1 −0.5 00
2
4
6
8
10
12
VGS
− VFB
(V)
CG
(m
F /
m2 )
SimulationCompactSemiclassical
tox
= 3 nmtsoi
= 25 nmtbox
= 25 nmN
ch = 1017 cm−3
Nsub
= 1017 cm−3
(a) CG vs. VG − VFb
−2 −1.9 −1.8 −1.7 −1.6 −1.5 −1.4 −1.30
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VGS
− VFB
(V)
Abs
olut
e er
ror
(%)
(b) % error vs. VG − VFb
Figure 2.36: (a) Gate capacitance (CG) vs gate voltage (VG − VFb) and (b) Absolute
error (%) vs gate voltage (VG − VFb) are presented for FD SOI pFET. Device param-
eters used are: tox = 3 nm, tsoi = 25 nm, tbox = 25 nm, Nch = 1017 cm−3, and Nsub
= 1017 cm−3.
53
2.5 Conclusion
A physically based compact model has been proposed in this chapter to correctly
simulate the gate capacitance of FD SOI MOSFETs considering the effects of energy
quantization of inversion layer carriers, wavefunction penetration and substrate de-
pletion. The proposed model is started with analytical modeling of ground state eigen
energy of inversion layer carriers. From the calculated eigen states surface potential
at three surfaces are modeled. Both n- and p-type MOSFETs, with ultrathin equiv-
alent oxide thickness (EOT) down to 1 nm, are modeled using the proposed model
and results are compared with self-consistent simulations. It is found that proposed
model can accurately model the gate capacitance while the calculation burden has
been reduced to a great extent.
54
CHAPTER 3
HIGH PERFORMANCE III-V ON INSULATOR FIELD EFFECT
TRANSISTOR
3.1 Introduction
The success of the semiconductor industry has been highly depending on the success of
increasing scaling of Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
for last few decades. Si based technology has served the industry for a long time and
expected to reach its performance limits due to basic physics rather that nuts and bolts
engineering [1]. Device engineers are searching for alternative semiconductor materi-
als, with higher carrier mobility, to continue the performance enhancement of MOS-
FETs [11]. III-V compound semiconductors are good candidate to replace Si in future
n-channel MOSFET because of their high electron mobility [42]. III-V materials have
been extensively studied for high performance n-channel MOSFETs [17, 70–72]. But
these approaches can not be integrated with present Si technology. Compound semi-
conductor heterogeneous integration with Si technology has been studied for lowering
the processing cost of alternative material high performance devices [73, 74]. Re-
cently, Ko et al. reported high performance compound semiconductor on insulator
MOSFETs by integration of ultrathin layers of III-V semiconductor on Si substrate
with reduced interface traps states [16]. In addition ultrathin body (UTB) semi-
conductor on insulator is one of the promising alternative structure to replace bulk
planner MOSFETs due to its superior performance in terms of parasitic capacitance,
enhanced mobility, and threshold voltage [1,22,75]. However, gate length (Lg) of the
55
reported devices by Ko et al. is 0.5 µm and thickness of the InAs layer is 15nm.
According to International Technology Roadmap for Semiconductors (ITRS) high
performance logic technology requirement UTB fully depleted (FD) devices will have
physical gate length, body thickness and oxide thickness of 17 nm, 5.5 nm and 0.6
nm (EOT) respectively at 2015. It is shown that ballistic ratio at such gate length
will be unity [76].
In this chapter, we have investigated the performance of III-V on insulator n-
channel MOSFET at ballistic regime. The effect of biaxial strain on the channel
material due to lattice mismatch has also been investigated. For our investigation we
have used GaAs and InAs as channel material.
3.2 Performance Analysis of III-V on Insulator (III-V-OI) Field Effect
Transistor
Intel launched 45 nm technology microprocessor with high-k metal gate in 2009 as the
last generation bulk planar MOSFET. Most promising devices for the next technol-
ogy generation are ultrathin body (UTB) fully depleted (FD) SOI FET and FinFET.
According to ITRS high performance logic technology requirement, UTB FD devices
should be in chips from 2013 to 2019 [1]. So we are presenting a comparative analysis
of silicon SOI and III-V-OI devices at 17 nm technology node to show the perfor-
mance enhancement that can be achieved through heterogeneous integration of III-V
material with Si technology in n-MOSFET. The device structure used for simulation
is shown in Fig. 3.1. For this study we have used the parameters from ITRS Process
Integration, Devices and Structures (PIDS): Table PIDS2. Parameters are listed in
table A.1.
56
17 -3
2
Source Drainp- InAs / GaAs (10
17cm
-3)
ZrO2
Figure 3.1: Schematic diagram of III-V on Insulator field effect transistor.
Table 3.1: Simulation parameters for performance analysis of UTB FD III-V-OI de-
vices
Parameter Value
Body thickness (tbody) 5.5 nm
Oxide thickness (tox) 0.6 nm (EOT)
Power supply voltage (Vdd) 0.81 V
Saturation threshold voltage (Vt,sat) 220 mV
1D coupled Schrodinger-Poison self-consistent simulator has been used to calculate
the electrostatics of III-V-OI field effect transistors. Effect of wavefunction penetra-
tion into the gate dielectric has been incorporated using open boundary conditions at
dielectric-semiconductor interfaces [59,60]. Effect of biaxial strain on channel material
has been incorporated using deformation potential model [77]. Once the electrostatics
57
of the given device is known, ballistic drain current is calculated using over-the-barrier
model [78, 79]. Metal gate work function is adjusted to fulfil the threshold voltage
(Vt) requirement of ITRS (Table A.1). Vt is defined as the gate voltage (VGS) at
which on current (ION) of the device is 1 µA/µm.
Recent study shows that band structure affects the performance of ultrathin body
(UTB) III-V nMOSFETs [80]. Liu et al. shows with the mean of tight binding (TB)
model that nonparabolicity in the Γ valley plays an important role in determining the
performance of III-V UTB nMOSFETs [80]. It is suggested that bulk effective masses
should not be used in the analysis of III-V UTB structures rather they proposed
thickness-dependent effective masses. Thickness dependent effective masses proposed
by Liu et al. is reproduced in Fig. 3.2 [80]. Thickness dependent effective masses are
used for this study to incorporate the effects of band structure on the performance of
III-V UTB FD nMOSFETs.
0 5 10 150
0.05
0.1
0.15
0.2
0.25
0.3
0.35
tbody
(nm)
mz (
× m
0)
InAs − UTBGaAs − UTB
Figure 3.2: Confinement effective mass mz of the Γ valley as a function of the thin-film
body thickness for GaAs and InAs. For both semiconductor materials, mz increases
significantly as the body thickness decreases.
58
Fig. 3.3 shows the inversion carrier density, Ninv as a function of gate voltage
(VGS). It is observable that Si device has higher Ninv compared to III-V devices.
This is due to the fact that III-V materials have lower density of state (DOS) effective
mass than that of Si.
0 0.2 0.4 0.6 0.80
2
4
6
8
VGS
(V)
Nin
v (
× 10
12 /c
m2 )
InAsGaAsSi
Figure 3.3: Inversion carrier - Voltage (Ninv −VGS) characteristics of UTB FD III-V-
OI and SOI n-type field effect transistors.
Fig. 3.4 shows the gate capacitance - voltage (CG − VGS) characteristics of GaAs,
InAs and Si UTB FD devices. It is evident from the figure that Si device has the
highest CG and InAs device has lowest CG in the range of operation. It can be
explained from Fig. 3.3. From fig 3.3, it can be understood that as Si device has
Ninv - VGS profile with highest slope it has the highest CG at inversion. It is also
observable that GaAs device shows very high increase in CG at higher VGS . It is due
to the occupancy of L-valley which has a higher DOS effective mass than Γ-valley.
Fig. 3.5 shows the injection velocity, Vinj as a function of VGS . The velocity at
which ballistic carriers are injected into the channel from source is known as injection
velocity. It is different from the drift and thermal velocity. To calculate Vinj we used
59
0 0.2 0.4 0.6 0.80
10
20
30
40
50
VGS
(V)
CG
(m
F /
m2 )
InAsGaAsSi
Figure 3.4: Capacitance - Voltage (CG − VGS) characteristics of UTB FD III-V-OI
and SOI n-type field effect transistor.
equation 3.1, where ION is the current at higher drain bias when injection from drain
side is seized. It can be seen from Fig. 3.5 that Vinj is higher in InAs device which
can be attributed to the light conduction effective mass in InAs. As the conduction
effective mass of GaAs is higher than InAs, it has lower Vinj.
ION = qVinjNinv (3.1)
ION depends on two factors i) Vinj ii) Ninv (equation 3.1). Fig. 3.3 shows a lower
Ninv whereas Fig. 3.5 shows a higher Vinj in III-V devices compared to Si device. So,
two contentious effects are present to determine ION in III-V on insulator nMOSFETs.
In InAs device, a 33% decrease (table 3.2) in Ninv and 281.7% increase (table 3.3) in
Vinj resulted a 156.18% increase (table 3.4) in ION compared to Si device. In GaAs
device, a 21.63% decrease (table 3.2) in Ninv and 175.2% increase (table 3.3) in Vinj
resulted a 116.24% increase (table 3.4) in ION compared to Si device. Fig. 3.6 and 3.7
60
1.00
1.05
1.10
1.15
1.20
1.25
1.30
0.0 0.2 0.4 0.6 0.8
2
4
6
V inj (
X 1
07 cm
/s)
InAs GaAs
V inj (
X 1
07 cm
/s)
VGS (V)
Si
Figure 3.5: Injection velocity - Voltage (Vinj − VGS) characteristics of UTB FD III-
V-OI and SOI n-type field effect transistor.
show the transfer characteristics (ION - VGS) and drain current - voltage (ID - VDS)
characteristics of different types of SOI devices. It is evident that III-V SOI devices
has higher on current (ION) compared to Si devices. Among the InAs and GaAs,
InAs shows better performance, i.e. higher ION compared to GaAs. Though InAs
has outperform GaAs in terms of ION , due to its narrow band gap its shows higher
off-state current. Besides ternary InGaAs has its advantages over binary materials
(GaAs, InAs etc.) as its larger inter-valley separation (0.5 eV for In0.53Ga0.47As)
ensures lower degradation of electron transport under high drain bias. So ternary
materials, such as, In0.53Ga0.47As can be used for the channel material to tradeoff
between on-state and off-state current.
61
0 0.2 0.4 0.6 0.80
1
2
3
4
5
VGS
(V)
I ON (
× 10
3 µA
/ µm
)
InAsGaAsSi
Figure 3.6: Transfer characteristics (I−V ) of UTB FD III-V-OI and SOI n-type field
effect transistor.
0 0.2 0.4 0.6 0.80
1
2
3
4
5
VDS
(V)
I D (
× 10
3 µA
/ µm
)
InAsGaAsSi
Figure 3.7: Drain current - Voltage (ID − VDS) characteristics of UTB FD III-V-OI
and SOI n-type field effect transistor for VGS = 0.8 V.
62
Table 3.2: Decrease of inversion carrier concentration, Ninv in III-V-OI devices com-
pared to SOI devices at VGS = VDS = 0.8 V
Si nMOSFET GaAs nMOSFET InAs nMOSFET
Ninv Ninv % decrease Ninv % decrease
(×1012/cm−2) (×1012/cm−2) (×1012/cm−2)
8.069 6.323 21.63 5.407 33
Table 3.3: Increase of injection velocity, Vinj in III-V-OI devices compared to SOI
devices at VGS = VDS = 0.8 V
Si nMOSFET GaAs nMOSFET InAs nMOSFET
Vinj Vinj % increase Vinj % increase
(×107cm/s) (×107cm/s) (×107cm/s)
1.258 3.462 175.2 4.802 281.7
Table 3.4: Enhancement of on current, ION in III-V-OI devices compared to Si devices
Si nMOSFET GaAs nMOSFET InAs nMOSFET
ION ION % increase ION % increase
(µA/µm) (µA/µm) (µA/µm)
1625 3514 116.24 4163 156.18
3.3 Effect of Strain
When compound semiconductors, like GaAs and InAs, are grown on Si/SiO2 system,
they experience biaxial strain due to lattice mismatch with the base layer. Incor-
63
poration of strain effects in the device simulator with accurate physics is important
because it can change the device performance to a great deal. For a GaAs and InAs
on a Si/SiO2 substrate, type of biaxial strain is compressive, which stimulate the edge
of the conduction band to shift at higher energy (for electron) [77].
Fig. 3.8 and 3.9 show the conduction band diagrams of GaAs and InAs devices
respectively. In both of the cases, bottom edge of conduction band (EC(channel)),
in the channel region, have been shifted to higher energy with the incorporation of
strain. Here, we can see that a quantum well has been formed due to thin channel
layer (5.5 nm) in between front and buried oxides . It is expected that as EC(channel)
has been changed, it will also affect the position of eigen energies of the quantum well.
Fig. 3.10 and 3.11 show the change in eigen energies (Ei) as a function of gate
voltage (flat band voltage, VFB is assumed to be zero) for GaAs and InAs devices
respectively. Only lowest two (E1 and E2) states are shown as higher states have very
little probability of occupancy. It is observable from Figs. 3.10(a) and 3.11(a) that
strain effect forces the eigen energies to come closer to the bottom edge of conduction
band, EC (at the front oxide-channel interface) for both GaAs and InAs system. This
is expected as the conduction band edge shifts upward due to compressive character-
istic of strain. Though energy difference between Ei and EC (Ei - EC) decreases due
to strain effect, energy difference between Ei and fermi energy, EF (Ei - EF ) increases
with the consideration of strain effect (Figs. 3.10(b) and 3.11(b)). So, it is expected
that the channel will invert at higher gate voltage (VG - VFB) and reasons higher
threshold voltage (Vt) with the consideration of strain effect.
Fig. 3.12 and 3.13 show gate capacitance - votage, CG-VGS (3.12(a) and 3.13(a))
and on current - voltage, ION -VGS (3.12(b) and 3.13(b)) characteristics for GaAs and
InAs devices respectively. From both C-V and I-V curves it can be readily understood
that stain effect causes a higher threshold voltage for both GaAs and InAs devices.
64
−5 0 5 10 150
0.5
1
1.5
2
2.5
3
3.5
Z (nm)
Ene
rgy
(eV
)
VG
− VFB
= 0.05 V
w/o strainw strain
(a) Energy band diagram for VGS - VFB = 0.1 V
−5 0 5 10 15−1.5
−1
−0.5
0
0.5
1
1.5
2
Z (nm)
Ene
rgy
(eV
)
VG
− VFB
= 2.0 V
w/o strainw strain
(b) Energy band diagram for VGS - VFB = 2.0 V
Figure 3.8: Energy band diagrams are shown with (solid lines) and without (dotted
lines) incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2 / 5.5 nm GaAs
/ 25 nm SiO2 / Si for VGS - VFB = 0.1 V (a) and VGS - VFB = 2.0 V (b). Part of
the band profile in the Si substrate is not shown here.
65
−5 0 5 10 15−0.5
0
0.5
1
1.5
2
2.5
3
3.5
Z (nm)
Ene
rgy
(eV
)
VG
− VFB
= 0.05 V
w/o strainw strain
(a) Energy band diagram for VGS - VFB = 0.1 V
−5 0 5 10 15−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
Z (nm)
Ene
rgy
(eV
)
VG
− VFB
= 2.0 V
w/o strainw strain
(b) Energy band diagram for VGS - VFB = 2.0 V
Figure 3.9: Energy band diagrams are shown with (solid lines) and without (dotted
lines) incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2 / 5.5 nm InAs
/ 25 nm SiO2 / Si for VGS - VFB = 0.1 V (a) and VGS - VFB = 2.0 V (b). Part of
the band profile in the Si substrate is not shown here.
66
0 0.5 1 1.5 2 2.50
0.1
0.2
0.3
0.4
Ei −
EC (
eV)
VGS
− VFB
(V)
w/o strainw strain E
2
E1
(a) 1st (E1) and 2nd (E2) eigen state respect to conduction band
edge (EC)
1 1.5 2 2.5−0.5
0
0.5
1
1.5
Ei −
EF (
eV)
VGS
− VFB
(V)
w/o strainw strain
E2
E1
(b) 1st (E1) and 2nd (E2) eigen state respect to fermi energy
(EF )
Figure 3.10: Eigen energies are shown with (solid lines) and without (dotted lines)
incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2 / 5.5 nm GaAs / 25
nm SiO2 / Si system.
67
1 1.5 2 2.50
0.2
0.4
0.6
0.8
1
Ei −
EC (
eV)
VGS
− VFB
(V)
w/o strainw strain
E2
E1
(a) 1st (E1) and 2nd (E2) eigen state respect to conduction band
edge (EC)
0.5 1 1.5 2 2.5−1
−0.5
0
0.5
1
1.5
Ei −
EF (
eV)
VGS
− VFB
(V)
w/o strainw strain
E2
E1
(b) 1st (E1) and 2nd (E2) eigen state respect to fermi energy
(EF )
Figure 3.11: Eigen energies are shown with (solid lines) and without (dotted lines)
incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT) ZrO2 / 5.5 nm InAs / 25
nm SiO2 / Si system.
68
0 0.5 1 1.5 20
5
10
15
20
25
30
VGS
− VFB
(V)
CG
(m
F /
m2 )
w/o strainw strain
(a) Gate capacitance (CG) vs Gate voltage (VG - VFB)
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6
7
8
VGS
− VFB
(V)
I ON (
× 10
3 µ A
/µ m
)
w/o strainw strain
(b) On current (ION ) vs Gate voltage (VG - VFB)
Figure 3.12: Gate capacitance (a) and on current (b) are shown with (solid lines)
and without (dotted lines) incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT)
ZrO2 / 5.5 nm GaAs / 25 nm SiO2 / Si system.
69
0 0.5 1 1.5 20
5
10
15
20
25
30
VGS
− VFB
(V)
CG
(m
F /
m2 )
w/o strainw strain
(a) Gate capacitance (CG) vs Gate voltage (VG - VFB)
0 0.5 1 1.5 2 2.50
5
10
15
20
25
30
VGS
− VFB
(V)
I ON (
× 10
3 µ A
/µ m
)
w/o strainw strain
(b) On current (ION ) vs Gate voltage (VG - VFB)
Figure 3.13: Gate capacitance (a) and on current (b) are shown with (solid lines)
and without (dotted lines) incorporating strain effect for a 3.85 nm (∼ 0.6 nm EOT)
ZrO2 / 5.5 nm InAs / 25 nm SiO2 / Si system.
70
3.4 Conclusion
Performance of n-channel III-V on insulator (III-V-OI) ultrathin body (UTB) fully
depleted (FD) field effect transistors (FETs) have been investigated and compared
to n-channel silicon on insulator (SOI) UTB FD FETs. GaAs and InAs have been
used as III-V materials for the study. Electrostatics of the device is determined using
self-consistent Schrodinger - Poisson simulation considering the effect of wavefunction
penetration and substrate depletion. With the known electrostatics, ballistic drain
current is determined using over-the-barrier model. It is shown that III-V-OI n-
channel devices outperforms SOI n-channel devices. Effects of bi-axial strain on
channel has also been studied. It is found that bi-axial strain increases threshold
voltage (Vt) of III-V-OI devices.
71
CHAPTER 4
HIGH PERFORMANCE GERMANIUM ON INSULATOR FIELD
EFFECT TRANSISTOR
4.1 Introduction
The success of the semiconductor industry has been highly depending on the success of
increasing scaling of Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
for last few decades. Si based technology has served the industry for a long time and
expected to reach its performance limits due to basic physics rather that nuts and
bolts engineering [1]. Device engineers are searching for alternative semiconductor
materials, with higher carrier mobility, to continue the performance enhancement
of MOSFETs [11]. Germanium (Ge) has been studied extensively [21–27, 43, 81, 82]
to replace Si in pMOSFETs for its high hole mobility. Recent study shows that
heterogeneous integration of Ge with silicon on insulator substrate with thermally
grown GeO2 interfacial layer can be useful for high performance fully depleted (FD)
germanium on insulator (GeOI) field effect transistor [43]. In addition ultrathin body
(UTB) semiconductor on insulator is one of the promising alternative structure to
replace bulk planner MOSFETs due to its superior performance in terms of parasitic
capacitance, enhanced mobility, and threshold voltage [1,22,75]. However, gate length
(Lg) of the reported devices by Gu et al. [43] is 2 µm and thickness of the Ge layer is
100 nm. According to International Technology Roadmap for Semiconductors (ITRS)
high performance logic technology requirement UTB fully depleted (FD) devices will
have physical gate length, body thickness and oxide thickness of 17 nm, 5.5 nm and
72
0.6 nm (EOT) respectively at 2015. It is shown that ballistic ratio at such gate length
will be unity [76].
In this chapter, we have investigated the performance of GeOI p-channel MOSFET
at ballistic regime. Performance of GeOI devices are compared to SOI (silicon on
insulator) to show the prospect of Ge for future technology generation.
4.2 Performance Analysis of Ge on Insulator Field Effect Transistor
Intel Intel launched 45 nm technology microprocessor with high-k metal gate in 2009
as the last generation bulk planar MOSFET. Most promising devices for the next
technology generation are ultrathin body (UTB) fully depleted (FD) SOI FET and
FinFET. According to ITRS high performance logic technology requirement, UTB FD
devices should be in chips from 2013 to 2019 [1]. So we are presenting a comparative
analysis of SOI and SOI devices at 17 nm technology node to show the performance
enhancement that can be achieved through heterogeneous integration of Ge material
with Si technology in p-MOSFET. The device structure used for simulation is shown in
Fig. 4.1. For this study we have used the parameters from ITRS Process Integration,
Devices and Structures (PIDS): Table PIDS2. Parameters are listed in table 4.1.
73
17 -3
2
Source Drainn-Ge (10
17cm
-3)
HfO2
Figure 4.1: Schematic diagram of Ge on Insulator field effect transistor.
Table 4.1: Simulation parameters for performance analysis of Ge UTB MOSFETs
Parameter Value
Body thickness (tbody) 5.5 nm
Oxide thickness (tox) 0.6 nm (EOT)
Power supply voltage (Vdd) 0.81 V
Saturation threshold voltage (Vt,sat) 220 mV
1D coupled Schrodinger-Poison self-consistent simulator has been used to calcu-
late the electrostatics of Ge of insulator field effect transistors. Effect of wavefunc-
tion penetration into the gate dielectric has been incorporated using open boundary
conditions at dielectric-semiconductor interfaces [59, 60]. Effect of biaxial strain on
channel material has been incorporated using deformation potential model [77]. Once
the electrostatics of the given device is know, ballistic drain current is calculated us-
ing over-the-barrier model [78, 79]. Metal gate work function is adjusted to fulfil the
74
threshold voltage (Vt) requirement of ITRS (Table 4.1). Vt is defined as the gate
voltage (VGS) at which on current (ION) of the device is 1 µA/µm. However, Strain
effect in GeOI device is not as substantial as in III-V-OI devices. So, effect of stain
has not been included in this chapter.
Fig. 4.2 shows the inversion carrier density, Ninv as a function of gate voltage
(VGS). It is observable that Si device has higher Ninv compared to Ge device. This
is due to the fact that Ge materials have lower density of state (DOS) effective mass
than that of Si.
−0.8 −0.6 −0.4 −0.2 00
2
4
6
8
VGS
(V)
Nin
v (
× 10
12 /c
m2 )
GeSi
Figure 4.2: Inversion carrier - Voltage (Ninv − VGS) characteristics of GeOI and SOI
p-type field effect transistor.
Fig. 4.3 shows the gate capacitance - voltage (CG−VGS) characteristics of Ge and
Si UTB FD devices. It is evident from the figure that Si device has the higher CG
then Ge device in the range of operation. It can be explained from Fig. 4.2. From fig
4.2, it can be understood that as Si device has Ninv - VGS profile with higher slope it
has higher CG then Ge device at inversion.
Fig. 4.4 shows the injection velocity, Vinj as a function of VGS . The velocity at
which ballistic carriers are injected into the channel from source is known as injection
75
−0.8 −0.6 −0.4 −0.2 0−10
0
10
20
30
40
VGS
(V)
CG
(m
F /
m2 )
GeSi
Figure 4.3: Capacitance - Voltage (CG−VGS) characteristics of GeOI and SOI p-type
field effect transistor.
velocity. It is different from the drift and thermal velocity. To calculate Vinj we used
equation 4.1, where ION is the current at higher drain bias when injection from drain
side is seized. It can be seen from Fig. 4.4 that Vinj is higher in Ge device which can
be attributed to the light conduction effective mass of holes in Ge.
ION = qVinjNinv (4.1)
ION depends on two factors i) Vinj ii) Ninv (equation 4.1). Fig. 4.2 shows a lower
Ninv whereas Fig. 4.4 shows a higher Vinj in Ge device compared to Si device. So,
two contentious effects are present to determine ION in GeOI pMOSFETs. In Ge
device, a 33.09% decrease (table 4.2) in Ninv and 685.94% increase (table 4.3) in Vinj
resulted a 425.58% increase (table 4.4) in ION compared to Si device. Fig. 4.5 and 4.6
show the transfer characteristics (ION - VGS) and drain current - voltage (ID - VDS)
characteristics of GeOI and SOI p-channel devices. It is evident that GeOI devices
has higher on current (ION) compared to Si devices.
76
-0.8 -0.6 -0.4 -0.2 0.0
4
5
6
7
8
9
10
0.95
1.00
1.05
1.10
1.15
1.20 Ge
Vin
j (X
107 c
m/s
)
VGS (V)
Si
V
inj (
X 10
7 cm
/s)
Figure 4.4: Injection velocity - Voltage (Vinj − VGS) characteristics of GeOI and SOI
p-type field effect transistor.
−0.8 −0.6 −0.4 −0.2 00
2
4
6
8
VGS
(V)
I ON (
× 10
3 µA
/ µm
)
GeSi
Figure 4.5: Transfer characteristics (I − V ) of GeOI and SOI p-type field effect
transistor.
77
−0.8 −0.6 −0.4 −0.2 00
2
4
6
8
VDS
(V)
I D (
× 10
3 µA
/ µm
)
GeSi
VGS
= 0.8
VGS
= 0.6
Figure 4.6: Drain current - Voltage (ID−VDS) characteristics of GeOI and SOI p-type
field effect transistor.
Table 4.2: Decrease of inversion carrier concentration, Ninv in GeOI devices compared
to SOI devices at VGS = VDS = 0.8 V
Si pMOSFET Ge pMOSFET
Ninv Ninv % decrease
(×1012/cm−2) (×1012/cm−2)
7.349 4.917 33.09
78
Table 4.3: Increase of injection velocity, Vinj in GeOI devices compared to SOI devices
at VGS = VDS = 0.8 V
Si pMOSFET Ge pMOSFET
Vinj Vinj % increase
(×107cm/s) (×107cm/s)
1.188 9.337 685.94
Table 4.4: Enhancement of on current, ION in GeOI devices compared to SOI devices
Si pMOSFET Ge pMOSFET
ION ION % increase
(µA/µm) (µA/µm)
1399 7353 425.58
79
4.3 Conclusion
Performance of n-channel Ge on insulator (GeOI) ultrathin body (UTB) fully depleted
(FD) field effect transistor (FETs) has been investigated compared to p-channel sil-
icon on insulator (SOI) UTB FD FETs. It is shown that GeOI p-channel devices
outperforms SOI p-channel devices.
80
CHAPTER 5
CONCLUSIONS
5.1 Summary
Silicon on insulator (SOI) MOSFET is one of the promising device architectures for
future high speed low power logic devices. Though numerical and compact models of
ultrathin body (UTB) fully depleted (FD) SOI devices have been proposed by numer-
ous researchers, a complete compact model incorporating quantum mechanical (QM)
effects is not available in the literature. In this dissertation, as a first effort, a surface
potential based QM compact model for UTB FD SOI devices is proposed incorporat-
ing QM effects, such as, energy quantization of inversion carriers, and wavefunction
penetration into the front and buried oxides. Most of the SOI MOSFET models
considers substrate as back gate. In the proposed model, substrate depletion is in-
corporated which makes it suitable for simulation of SOI devices with low substrate
doping. To validate the accuracy of the model gate C-V characteristics is calculated
using the compact model and compared with self-consistent simulation over a wide
range of device parameters.
Moreover, III-V and Ge have been investigated widely as a replacement of Si in the
channel and source/drain regions for future CMOS technology. III-V materials are
suitable for n-type MOSFETs for their high electron mobility whereas Ge is suitable
for p-type MOSFETs for its high hole mobility. So, as a second effort, performance
enhancement of semiconductor on insulator architecture is investigated when channel
will be replaced by III-V materials and Ge in n- and p-type SOI devices respectively.
81
Both III-V on insulator and Ge on insulator devices outperform SOI devices.
82
5.2 Future directions
• Compact model is Proposed for SiO2 / Si / SiO2 / Si system. Incorporating
high - κ will cause modification to the values of γ and λ. A possible future work
might be the modification of the existing model for high - κ / Si / SiO2 / Si
system.
• Decreasing the channel thickness below 5 nm will cause inaccurate modeling of
eigen energies. A more accurate compact modeling of eigen energies of UTB
FD SOI devices can be done using superposition of a triangular potential well
and a square potential well.
• Realization of III-V-OI and GeOI devices in integrated circuits will make need
for compact models for these devices. A complete compact incorporating QM
effects would be possible future work.
83
BIBLIOGRAPHY
[1] http://www.itrs.net/links/2009ITRS/Home2009.htm.
[2] G. E. Moore, “Progress in digital integrated electronics,” in Proc. IEDM Dig.,
1975.
[3] J. Atalla and D. Kahng, “Metal oxide semiconductor (mos) transistor demon-
strated: John atalla and dawon kahng fabricate working transistors and demon-
strate the first successful MOS field-effect amplifier,” US Patent no 3102230
(1960).
[4] http://www.intel.com/.
[5] K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos,
I. V. Grigorieva, and A. A. Firsov, “Electric field effect in atomically thin carbon
films,” Science, vol. 306, pp. 666–669, 2004.
[6] G. Liang, N. Neophytou, D. E. Nikonov, and M. S. Lundstrom, “Performance
projections for ballistic graphene nanoribbon field-effect transistors,” IEEE
Trans. Electron Devices, vol. 54, no. 4, p. 677, 2007.
[7] R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, and G. Baccarani, “Graphene
nanoribbons FETs for high-performance logic applications: Perspectives and
challenges,” in Proc. ICSICT, Oct. 2008, pp. 365–368.
[8] X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, “Chemically derived, ultrasmooth
graphene nanoribbon semiconductors,” Science, vol. 319, pp. 1229–1292, Feb.
2008.
84
[9] K. Bolotin, K. Sikes, Z. Jiang, M. Klima, G. Fudenberg, J. Hone, P. Kim, and
H. Stormer, “Ultrahigh electron mobility in suspended graphene,” Solid State
Communications, vol. 146, pp. 351–355, 2008.
[10] D. D. D. Ma, C. S. Lee, F. C. K. Au, S. Y. Tong, and S. T. Lee, “Small-diameter
silicon nanowire surfaces,” Science, vol. 299, pp. 1874–1877, Mar. 2003.
[11] K. C. Saraswat, C. O. Chui, D. Kim, T. Krishnamohan, and A. Pethe, “High
mobility materials and novel device structures for high performance nanoscale
MOSFETs,” in Proc. IEDM Tech. Dig., 2006, pp. 659–662.
[12] N. Goel and et al., “Addressing the gate stack challenge for high mobility ingaas
channels for nfets,” in Proc. IEDM Tech. Dig., 2008, p. 363.
[13] D. Varghese, Y. Xuan, Y. Q. Wu, T. Shen, P. Ye, and M. A. Alam, “Multi-probe
interface characterization of ingaas/al2o3 MOSFET,” in Proc. IEDM Tech. Dig.,
2008, p. 379.
[14] H.-C. Chin, X. Gong, X. Liu, Z. Lin, and Y.-C. Yeo, “Strained In0.53Ga0.47As
n-MOSFETs: Performance boost with in-situ doped lattice-mismatched
source/drain stressors and interface engineering,” in Proc. VLSI Tech. Dig.
Symp, 2009, p. 244.
[15] M. Yokoyama and et al., “High mobility metal S/D III-V-On-Insulator MOS-
FETs on a si substrate using direct wafer bonding,” in Proc. VLSI Tech. Dig.
Symp, 2009, p. 242.
[16] H. Ko, K. Takei, R. Kapadia, S. Chuang, H. Fang, P. W. Leu, K. Ganapathi,
E. Plis, H. S. Kim, S. Y. Chen, M. Madsen, A. C. Ford, Y. L. Chueh, S. Krishna,
S. Salahuddin, and A. Javey, “Ultrathin compound semiconductor on insulator
layers for high-performance nanoscale transistors,” Nature, vol. 468, pp. 286–289,
nov 2010.
85
[17] Y. Xuan, Y. Q. Wu, T. Shen, T. Yang, and P. D. Ye, “High performance sub-
micron inversion-type enhancement-mode InGaAs MOSFETs,” in Proc. IEDM
Tech. Dig., 2007, p. 637.
[18] T. H. Chiang and et al., “Approaching fermi level unpinning in oxide-InGaAs,”
in Proc. IEDM Tech. Dig., 2008, p. 375.
[19] D. H. Kim and J. A. del Alamo, “Logic-performance of 40 nm InAs HEMTs,”
in Proc. IEDM Tech. Dig., 2007, p. 629.
[20] N. Waldron, D. H. Kim, and J. A. del Alamo, “90nm self-aligned enhancement-
mode InGaAs HEMT for logic applications,” in Proc. IEDM Tech. Dig., 2007,
p. 633.
[21] T. Irisawa, S. Tokumitsu, T. Hattori, K. Nakagawa, S. Koh, and Y. Shi-
raki, “Ultrahigh room-temperature hole hall and effective mobility in
Si0.3Ge0.7/Ge/Si0.3Ge0.7 heterostructure,” Applied Physics Letters, vol. 81, p. 847,
2002.
[22] T. Krishnamohan, Z. Krivokapic, K. Uchida, and Y. Nishi, “High-mobility ultra-
thin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling
leakage: Experiments,” IEEE Trans. Electron Devices, vol. 53, p. 990, 2006.
[23] J. Mitard and et al., “Impact of EOT scaling down to 0.85 nm on 70 nm Ge-
pFETs technology with STI,” in Proc. VLSI Tech. Dig. Symp, 2009, p. 82.
[24] T. Takahashi, T. Nishimura, L. Chen, S. Sakata, K. Kita, and A. Toriumi, “Proof
of Ge-interfacing concepts for Metal/High-k/Ge CMOS - Ge-intimate material
selection and interface conscious process flow,” in Proc. IEDM Tech. Dig., 2007,
p. 697.
86
[25] Y. Nakakita, R. Nakane, T. Sasada, H. Matsubara, M. Takenaka, and S. Tak-
agi, “Interface-controlled self-align source/drain Ge pMOSFETs using thermally-
oxidized GeO2 interfacial layers,” in Proc. IEDM Tech. Dig., 2008, p. 877.
[26] M. Kobayashi and et al., “High quality GeO2/Ge interface formed by SPA radical
oxidation and uniaxial stress engineering for high performance Ge NMOSFETs,”
in Proc. VLSI Tech. Dig. Symp, 2009, p. 76.
[27] T. Yamamoto and et al., “High performance 60 nm gate length germanium p-
MOSFETs with Ni germanide metal source/drain,” in Proc. IEDM Tech. Dig.,
2007, p. 1041.
[28] C. C. Wu and et al., “High performance 22/20 nm FinFET CMOS devices with
advanced high- κ /metal gate scheme,” in Proc. IEDM Tech. Dig., 2010, p. 2711.
[29] Q. Zhang, W. Zhao, , and A. Seabaugh, “Low-subthreshold-swing tunnel tran-
sistors,” IEEE Trans. Electron Devices, vol. 27, no. 4, pp. 297–300, 2006.
[30] O. M. Nayfeh, C. Chleirigh, J. Hennessy, L. Gomez, J. Hoyt, and D. Antoniadis,
“Design of tunneling field-effect transistors using strained-silicon/strained-
germanium type-II staggered heterojunctions,” IEEE Trans. Electron Devices,
vol. 29, no. 9, pp. 1074–1077, Sep. 2008.
[31] K. Gopalakrishnan, P. Griffin, and J. Plummer, “I-MOS: A novel semiconductor
device with a subthreshold slope lower than kT/q,” in Proc. IEDM Tech. Dig.,
2002, pp. 289–292.
[32] W. Choi, J. Song, J. Lee, Y. Park, and B. Park, “70-nm impact-ionization metal-
oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect tran-
sistors (TFETs),” in Proc. IEDM Tech. Dig., 2005, pp. 975–978.
87
[33] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage
amplification for low power nanoscale devices,” Nanoletters, vol. 8, no. 2, pp.
405–410, 2008.
[34] R. Yang, A. Ourmazd, and K. F. Lee, “Scaling the si MOSFET: From bulk to
SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704–1710, Jul.
1992.
[35] G. Gildenblat, W. Wu, X. Li, H. Wang, G. Workman, S. Veeraraghavan, and
C. McAndrew, “SP-SOI: A third generation surface potential based compact
MOSFET model,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2005, pp.
819–822.
[36] M. S. L. Lee, B. N. Tenbroek, W. Redman-White, J. Benson, and M. J. Uren, “A
physically based compact model of partially depleted SOI MOSFETs for analog
circuit simulation,” IEEE Trans. Syst. Sci. Cybern., vol. 36, no. 1, pp. 110–121,
Jan. 2001.
[37] K. K. Young, “Short-channel effect in fully depleted SOI MOSFETs,” IEEE
Trans. Electron Devices, vol. 36, no. 2, pp. 399–402, Feb. 1989.
[38] G. F. Niu, R. M. M. Chen, and C. Ruan, “Comparisons and extension of recent
surface potential models for fully depleted short-channel SOI MOSFETs,” IEEE
Trans. Electron Devices, vol. 43, no. 11, pp. 2034–2037, Nov. 1996.
[39] Y. S. Yu, S. H. Kim, S. W. Hwang, and D. Ahm, “All-analytic surface potential
model for SOI MOSFETs,” in Proc. Inst. Elect. Eng. Circuits Devices Syst., vol.
152, no. 2, 2005, pp. 183–189.
[40] N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M.M.Yusoff, T. Ezaki, H. J.
Mattausch, and M. M. Mattausch, “Completely surface-potential based compact
88
model of the fully depleted SOI MOSFET including shortchannel effects,” IEEE
Trans. Electron Devices, vol. 53, no. 9, pp. 2017–2024, Sep. 2006.
[41] P. Agarwal, G. Saraswat, and M. J. Kumar, “Compact surface potential model
for FD SOI MOSFET considering substrate depletion region,” IEEE Trans. Elec-
tron Devices, vol. 55, no. 3, pp. 789–795, Mar. 2008.
[42] R. Chaua, S. Datta, and A. Majumdar, “Opportunities and challenges of III-V
nanoelectronics for future high speed, low power logic applications,” in Proc.
IEEE Compound Semiconductor IC Symp, 2005, pp. 17–20.
[43] J. J. Gu, Y. Q. Liu, M. Xu, G. K. Celler, R. G. Gordon, and P. D. Ye, “High
performance atomic-layer-deposited LaLuO3 /Ge-on-insulator p-channel metal-
oxide-semiconductor field-effect transistor with thermally grown GeO2 as inter-
facial passivation layer,” Applied Physics Letters, vol. 97, p. 012106, 2010.
[44] T. L. Chen and G. Gildenblat, “Analytical approximation for the MOSFET
surface potential,” Solid State Electron., vol. 45, pp. 335–339, 2001.
[45] G. Gildenblat, X. Li, W. Wu, H. Wang, A. Jha, R. V. Langevelde, G. D. J. Smit,
A. J. Scholten, and D. B. M. Klassen, “PSP: An advanced surface-potential-
based MOSFET model for circuit simulation,” IEEE Trans. Electron Devices,
vol. 53, no. 9, pp. 1979–1993, Sep. 2006.
[46] A. R. Boothroyd, S. W. Tarasewicz, , and C. Slaby, “MISNANA physically based
continuous MOSFET model for CAD applications,” IEEE Trans. Comput.-Aided
Design Integr. Circuits Syst., vol. 10, no. 12, pp. 1512–1529, Dec. 1991.
[47] J. He, Y. Song, X. Niu, G. Zhang, M. Chan, B. Li, R. Huang, and Y.Wang,
“PUNSIM: An advanced surface potential based MOSFET model,” in Proc.
MIXDES, Gdynia, Poland, Jun. 2006, pp. 111–116.
89
[48] C. B. Jie, S. Z. Biao, Y. Zhong, S. Ting, and J. Zheng, “Modeling of front and
back gate surface potential of deep-submicro FD-SOI MOSFET,” in Proc. 6th
Int. Conf. Solid State Integr. Circuits Technol., vol. 2, 2001, pp. 867–870.
[49] T.-L. C. X. G. G. Gildenblat, X. Cai and H.Wang, “Reemergence of the surface-
potential-based compact MOSFET models,” in Proc. IEDM Tech. Dig., Dec.
2001, pp. 36.1.1–36.1.4.
[50] G. Gildenblat, H.Wang, T. L. Chen, X. Gu, and X. Cai, “SP: An advanced
surface-potential-based compact MOSFET model,” IEEE J. Solid-State Circuits,
vol. 39, no. 9, pp. 1394–1406, Sep. 2004.
[51] K. Joardar, K. K. Gullapalli, C. McAndrew, M. E. Burnham, and A.Wild, “An
improved MOSFET model for circuit simulation,” IEEE Trans. Electron Devices,
vol. 45, no. 1, pp. 134–148, Jan. 1998.
[52] H. Wang, T. L. Chen, and G. Gildenblat, “Quasi-static and nonquasistatic com-
pact MOSFET models based on symmetric linearization of the bulk and inver-
sion charges,” IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2262–2272, Nov.
2003.
[53] J. R. Brews, “A charge-sheet model of the mosfet,” Solid State Electron., vol. 21,
p. 345, 1978.
[54] J. He, M.Chan, X. Zhang, and Y.Wang, “A physics-based analytic solution to
the MOSFET surface potential from accumulation to strong-inversion region,”
IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2008–2016, Sep. 2006.
[55] J. Benson, N. V. DHalleweyn, W. Redman-White, C. A. Easson, M. J. Uren,
O. Faynot, and J.-L. Pelloie, “A physically based relation between extracted
threshold voltage and surface potential flat band voltage for MOSFET compact
90
modeling,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 1019–1021, May
2008.
[56] M. M. Mattausch, U. Feldmann, A. Rahm, and M. Bollu, “Unified complete
MOSFET model for analysis of digital and analog circuits,” IEEE J. Solid-State
Circuits, vol. 15, no. 1, pp. 1–7, Jan. 1996.
[57] M. M. Mattausch, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh,
A. Kobayashi, and H. Masuda, “100 nm-MOSFET model for circuit simula-
tion: Challenges and solutions,” IEICE Trans. Electron., vol. E86-C, no. 6, pp.
819–822, Jun. 2003.
[58] F. Stern, “Self-consistent results for n-type si inversion layers,” Phys. Rev. B,
vol. 5, no. 12, pp. 4891–4899, Jun. 1972.
[59] S. Mudanai, L. F. Register, A. F. Tasch, and S. K. Banerjee, “Understanding
the effects of wave function penetration on the inversion layer capacitance of N
MOSFETs,” IEEE Electron Device Lett., vol. 22, no. 3, pp. 145–147, Mar. 2001.
[60] A. Haque and M. Z. Kauser, “A comparison of wavefunction penetration ef-
fects on gate capacitance in deep submicron n- and p-MOSFETs,” IEEE Trans.
Electron Devices, vol. 49, no. 9, pp. 1580–1587, Sep. 2002.
[61] F. Pregaldiny, C. Lallement, R. van Langevelde, and D. Mathiot, “An advanced
explicit surface potential model physically accounting for the quantization effects
in deep-submicron MOSFETs,” Solid State Electron., vol. 48, no. 3, pp. 427–435,
Mar. 2004.
[62] R. Rios, N. D. Arora, C. Huang, N. Khalil, J. Faricelli, and L. Gruber, “A
physical compact MOSFET model, including quantum mechanical effects, for
statistical circuit design applications,” in Proc. IEDM Tech. Dig., Dec. 1995, pp.
937–940.
91
[63] G. Gildenblat, T. L. Chen, and P. Bendix, “Closed-form approximation for
the perturbation of MOSFET surface potential by quantum-mechanical effects,”
Electron. Lett., vol. 36, no. 12, pp. 1072–1073, Jun. 2000.
[64] M. A. Karim and A. Haque, “A physically based, accurate model for quantum
mechanical correction to the surface potential of nano-scale MOSFETs,” IEEE
Trans. Electron Devices, vol. 57, no. 2, pp. 496–502, Feb. 2010.
[65] S. Chowdhury, E. Farzana, R. Ahmed, A. T. M. G. Sarwar, and M. Z. R. Khan,
“C-V characterization and analysis of temperature and channel thickness effetcs
on threshold voltage of ultra-thin SOI MOSFET by self-consistent model,” Jour-
nal of WASET, vol. 69, pp. 332–337, 2010.
[66] H. Watanabe, K. Uchida, and A. Kinoshita, “Numerical study of C-V character-
istics of double-gate ultrathin SOI MOSFETs,” IEEE Trans. Electron Devices,
vol. 54, no. 1, pp. 52–58, Jan. 2007.
[67] A. Kumar, J. Kedzierski, and S. E. Laux, “Quantum-based simulation analysis
of scaling in ultrathin body device structures,” IEEE Trans. Electron Devices,
vol. 52, no. 4, pp. 614–617, 2005.
[68] F. Li, S. Mudanai, L. F. Register, and S. K. Banerjee, “A physically based
compact gate CV model for ultrathin (eot 1 nm and below) gate dielectric MOS
devices,” IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1148–1158, Jun. 2005.
[69] T. Ando, B. Fowler, and F. Stern, “Electronic properties of two-dimensional
systems,” Rev. Modern Phys., vol. 54, no. 2, pp. 437–672, 1982.
[70] F. Ren, J. M. Kuo, M. Hong, W. S. Hobson, J. R. Lothian, J. Lin, H. S.
Tsai, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho,
“Ga2O2(Gd2O2)/InGaAs enhancement-mode n-channel MOSFETs,” IEEE Elec-
tron Device Lett., vol. 19, no. 9, pp. 309–311, Aug. 1998.
92
[71] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majum-
dar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-
performance and low-power logic transistor applications,” IEEE Trans. Nan-
otechnol., vol. 4, no. 2, pp. 153–158, Mar. 2005.
[72] U. Singisetti, M. A. Wistey, G. J. Burek, E. Arkun, A. K. Baraskar, Y. Sun, E. W.
Kiewra, B. J. Thibeault, A. C. Gossard, C. J. Palmstrom, and M. J. W. Rod-
well, “InGaAs channel MOSFET with self-aligned source/drain MBE regrowth
technology,” in Proc. International Symposium on Compound Semiconductors,
Rust, Germany, Oct. 2008.
[73] Y. Q. Wu, M. Xu, R. S. Wang, O. Koybasi, and P. Y. Ye, “High performance
deepsubmicron inversion-mode InGaAs MOSFETs with maximum Gm exceeding
1.1 ms/um: new HBr pretreatment and channel engineering,” in Proc. IEDM
Tech Dig., 2009.
[74] M. Radosavljevic and et al, “Advanced high-k gate dielectric for high-
performance short channel In0.7Ga0.3As quantum well field effect transistors on
silicon substrate for low power logic applications,” in Proc. IEDM Tech Dig.,
2009.
[75] A. Majumdar, Z. Ren, S. J. Koester, and W. Haensch, “Undoped-body extremely
thin SOI MOSFETs with back gates,” IEEE Trans. Electron Devices, vol. 56,
no. 10, pp. 2270–2276, 2009.
[76] S. E. Laux, “A simulation study of the switching times of 22- and 17-nm gate
lengths SOI nFETs on high mobility substrate and Si,” IEEE Trans. Electron
Devices, vol. 54, no. 9, pp. 2304–2320, sep 2007.
[77] J. Piprek, Semiconductor Optoelectronic Devices: Introduction to Physics and
Simulation. Academic Press, 2003.
93
[78] K. Natori, “Ballistic metal-oxide-semiconductor field effect transistor,” Journal
of Applied physics, vol. 76, pp. 4879–4890, 1994.
[79] F. Assad, Z. Ren, D. Vasileska, S. Datta, and M. Lundstrom, “On the per-
formance limits for si MOSFETs: A theoretical study,” IEEE Trans. Electron
Devices, vol. 47, no. 1, pp. 232–240, jan 2000.
[80] Y. Liu, N. Neophytou, G. Klimeck, and M. S. Lundstrom, “Band-structure ef-
fects on the performance of IIIV ultrathin-body SOI MOSFETs,” IEEE Trans.
Electron Devices, vol. 55, no. 5, pp. 1116–1122, may 2008.
[81] S. Saito, T. Hosoi, H. Watanabe, and T. Ono, “First-principles study to obtain
evidence of low interface defect density at Ge/GeO2 interfaces,” Applied Physics
Letters, vol. 95, p. 011098, 2009.
[82] A. Zaslavsky, S. Soliveres, C. L. Royer, S. Cristoloveanu, L. Clavelier,
and S. Deleonibus, “Negative transconductance in double-gate germanium-on-
insulator field effect transistors,” Applied Physics Letters, vol. 91, p. 183511,
2007.
94
APPENDIX A
IMPORTANT TABLES
Table A.1: Simulation parameters for performance analysis of III-V-OI and GeOI
MOSFETs
Parameter Value
Body thickness (tbody) 5.5 nm
Oxide thickness (tox) 0.6 nm (EOT)
Power supply voltage (Vdd) 0.81 V
Saturation threshold voltage (Vt,sat) 220 mV
Table A.2: Quantization and DOS effective masses of electrons in Si
Valleys m∗
l m∗
t
Degeneracy, nv 2 4
Quantization mass,mq/m0 0.916 0.197
Density of state mass,md/m0 0.190 0.169
95
Table A.3: Quantization and DOS effective masses of holes in Si
Valleys m∗
hh m∗
lh m∗
sh
Degeneracy, nv 1 1 1
Quantization mass,mq/m0 0.29 0.20 0.29
Density of state mass,md/m0 0.433 0.169 0.433
Table A.4: Quantization and DOS effective masses of electrons in InAs and GaAs
Material Γ-valley L-valley
nv mq/m0 md/m0 nv mq/m0 md/m0
InAs 1 0.026 0.023 4 0.0722 0.1489
GaAs 1 0.067 0.063 4 0.1109 0.3121
Table A.5: Quantization and DOS effective masses of holes in Ge
Valleys m∗
hh m∗
lh
Degeneracy, nv 1 1
Quantization mass,mq/m0 0.2075 0.1525
Density of state mass,md/m0 0.0566 0.0596
96