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Camera Auto FocusPresentation 4, February 14th, 2007
Team W1:Tom Goff (W11)David Hwang (W12)Kate Killfoile (W13)Greg Look (W14)
Design Manager: Bowei GaiProject Goal: Design a low-power, small auto focus chip for
a camera or other hand-held device
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Status• Last Time
– C implementation– Attempt at floor plan
• This WeekStructural Verilog completedMajor architecture revisionRevised floor plan
• In Process…Power control logic implementationLow-power component selection
• UnfinishedSchematicLayoutExtraction, LVS, post-layout simulation
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Big Picture Recap
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Design Decisions
• Optimization of rules
• Reduction of registers, additional preprocessing unit
• Led to a huge change in architecture
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Remember this?
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New Architecture
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AG PreprocessorZoom Out
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Delta I PreprocessorZoom Out
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Rule LogicZoom Out
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Transistor CountComponent Full Chip Count
Registers 1,600
Comparators 2,100
FP multiplier 3,000
FP adder 2,000
Subtractors 2,000
Int to float logic 1,040
Power control 2,000
Buffers 2,000
Muxes 2,480
Total ~18,220
Optimizes down from 25,230!
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Floor Plan
Dimensions: 238 x 266
Let’s make sense of all the wires and modules here…
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3 Input Multiply
Input: 10 bit values (3)
Output: 10 bit value
Accumulator
Input: 10 bit multiply value
10 bit register value
Output: 10 bit acc. value
AG Preprocessor
Input: 8 bit AG value
Output: 8 bit rule values (3)
Input Register
Input: 10 bit Delta I
Output: 9 bit Delta I
Delta I Preprocessor
Input: 9 bit Delta I
Output: 2 bit range
9 bit subtract
result (2)
Input Register
8 bit AGInt to Float
Input: 8 bit rule values (3)
Output: 10 bit rule
values (3)Power Logic
Input: 1 bit ready signal
Output: Control lines to registers and muxes
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Floor Plan
Component Size (µm² x µm²) Size (µm²)
Registers 52 x 8 4,847
Comparators 54 x 13 4,233
FP multiplier 115 x 100 11,494
10 bit muxes 54 x 14 6,080
FP adder 143 x 64 9,161
Subtractors 54 x 45 2,425
Int to float logic 42 x 22 2,766
Power control 88 x 83 7,252
8 bit muxes 43 x 13 2,865
Total ~63,000
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Testing of Components
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Structural Verilog
• Complete structural wiring
• Writing an exhaustive testbench
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Power Logic
• Registers used to shut down modules not in use
• Controls 3-input multiplier args
• Controls accumulator and output registers
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Next Steps
• Produce module schematics
• Continue optimizing logic
• Implement power logic control
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Work Distribution
• Tom: Verilog implementation
• Dave: Verilog implementation
• Greg: Gate level multiplier, adder
• Kate: Floor plan
• Bowei: Destructive criticism
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Problems
• Looking into power gating
• Group members can only work for 10 hours straight before going insane or feral or both
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Questions
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References
• None for this week