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Cell phone jammer with prescheduled time duration
ABSTRACT
Mobile
INTRODUCTION
Communication jamming device were first developed and used by military. This
interest comes from the fundamental objective of denying the successful transport
of information from the sender (tactical commander) to the receiver (the army
personnel), and vice-versa. Nowadays, mobile phones are becoming essential tool
in our daily life. The technology behind cell phone jamming is very simple. The
widely use the mobile phone could create some problems as the sound of ringing
becomes annoying or disrupting. This could happen in some places like conference
room, aw court, libraries, lecture room and mosques. The jamming device
broadcasts an RF signal in the frequency range reserved for cell phones that
interference with the cell phone signal, which results in a “no network available”
display on the cell phone screen. All phones with in the effective radius of the
jammer are science. It should be mentioned that cell phone jammers are illegal
devices in most countries.
Cell phone jammer with prescheduled time duration
A mobile phone jammer is an instrument used to prevent cellular phones from
receiver signal from based station. When used, the jammer effectively disables
cellular phones (fig 1). This device can be used in practically any location, but are
found primarily in places where a phone call would be particularly in places where
a phone call would be particularly disruptive because silence is expected. As with
other radio jamming, cell phone jammers block cell phone use by sending out radio
waves along the same frequencies that cellular phone use. These causes enough
interface with the communication between cell phones and towers to radar the
phones unusable. On most retail phones, the network would simply appear out of
range. Most cell phones use different bands to send
and receive communications from towers (called frequency division depleting,
FDD). Jammers can work by either disrupting phone to tower frequencies or tower
to phone frequencies. Smaller handheld models block all bands from 800 MHz to
1900 MHz within a 30-foot range (9meters). Small devices tend to used the former
method, while larger more expensive models many interfere directly with the
tower. The GSM jammer is a device that transmit signal on the same frequency at
which the GSM system operates, the jamming success when the mobile phone in
the area where the jammer is located can‟t communicate, the basic idea military
use that was called denial of service attack. Mobile jammer is used to prevent
mobile phone from receiving or transmitting signal with the base stations. When
used, the jammer effectively disables cellular phones as shown in fig 2. There are
several ways to jam an RF device. The three most common techniques can be
categorized as follows
In this kind of jamming, the device forces the mobile to turn off itself. This type is
very difficult to be implemented since the jamming device first detects any mobile
phone in a specific area, then the device sends the signal to disable the mobile
Cell phone jammer with prescheduled time duration
phone .some type of this technique can detect if a nearby mobile phone is there and
sends a message to tell the user to switch the phone to the silent mode (intelligent
beacon disablers). Shielding attacks: This is known as TEMPEST or EMF
shielding. This kind required closing an area in a faraday cage so that any device
inside this cage cannot transmit or receiver RF signal from outside of the cage.
This area can be large as buildings. Denial of service: This technique is referred to
DOS. In this technique, the device transmits a noise signal at the same operating
frequency of the mobile phone in order to decrease the signal -to-noise ratio (SNR)
of the mobile under its minimum value. This kind of jamming technique is the
simplest one since the device is always on. Our device is of this type.
The system that to set the scheduled time duration for mobile jammer. The
activation and deactivation time schedules can beprogrammed with
microcontroller. In order to run the RTC (real time clock) one crystal oscillator is
externally interfaced, an oscillator is an electronic circuit that produces a repetitive
electronic signal. The power supply interfaced it is used to battery backup for the
purpose of update the time when the absence of power. The A.C input i.e., 230v
from the mains supply is step down by the transformer to 12v and is fed to a
rectifier. One reset button interface, Reset is used for putting the microcontroller
into a „known‟ condition. That partially means that microcontroller can behave
rather inaccurately under certain undesirable condition. In order to continuous its
proper functioning it has to be reset. Relay is an electrically controllable switch
widely used in industrial controls, automobile and appliances.
Cell phone jammer with prescheduled time duration
LITERATURE SURVEY
2014, Shantanu Krishna Mahato, C.vimala
Cell phones are everywhere these days. It’s great to be able to call anyone at
anytime. Unfortunately, restaurants, public places, class room, shopping malls and
churches all suffer from the spread of cell phones because not all cell-phone users
know when to stop talking while most of us just grumble and move on, some
people are actually going to extremes to retaliate. Mobile jammer is a device used
to prevent mobile phones from receiving or transmitting signals with the base
stations. In this paper, we have to jam a cell phone, all we are developing a device
that broadcasts on the correct frequencies. Although different cellular systems
process signals differently, all cell-phone networks use radio signals that can be
interrupted. GSM, used in digital cellular and PCS-based systems, operates in the
900-MHz, 1800-MHz and WCDMA 2100 bands in Europe and Asia and in the
1900- MHz band in the United States. Jammers can broadcast on any frequency
and are effective against WCDMA, GSM and DCS. This project discusses the
Cell phone jammer with prescheduled time duration
design and development of GSM Mobile jammer and aims to present a solution for
the problems of occur through the cell phone. The main concept of jamming is the
releasing of same frequency which is using by mobile service provider with noise
so user equipment gets destruct.
EXISTING SYSTEM
In market, there are various types of jamming devices available which are using
different jamming techniques. Some of those devices are built with only one
feature in it like it will jam only 2G network compatible cell phones. This type of
device comes with several independent oscillators transmitting jamming signals
capable of blocking frequencies used by paging devices as well as those used by
cellular systems control channels for call establishment. IT does not transmit an
interfering signal on the control channels. The device, when located in the
designated quite area, functions as a detector. It has a unique identification number
for communicating with the cellular base station. The device, when located in the
designated quite area, functions as a beacon and any compatible terminal s
instructed to disable its ringer or disable its operation, while within the coverage
area of beacon. It behaves like a small, independent and portable base station,
which can directly interact with the operation of the local mobile phone. The
jammer is predominantly in receiving mode and will choose to interact and block
the cell phone directly if it is within close proximity of the jammer. Although
labor intensive to construct, the Faraday cage essentially Blocks or greatly
attenuates, virtually all electromagnetic radiation from entering or leaving the cage
or in this case a target room.
DISADVANTAGES
Cell phone jammer with prescheduled time duration
OFMD is highly sensitive to STO. Due to the use of IFFT and FFT for
modulation and demodulation at transmitter and receiver respectively,
correct timing is required at the
It is highly sensitive to carrier frequency offset. Mostof the advantages of
the orthogonal nature of sub-carriers and this orthogonality between sub
carriers will be destroyed if frequency offset arises between them. The
major cause of CFO is Doppler shifts (due to relative motion between
transmitter and channel.
The transmitted signal of OFDM exhibits a high Peak-To-Average Power
Ratio (PAPR). This high PAPR reduces the efficiency of high power
amplifier and degrades the performance of the system.
Cell phone jammer with prescheduled time duration
PROPOSED SYSTEM
We have designed and developed a project based on hardware viewing concept
“Mobile Jammer” which blocks the mobile networks of a designated area that are
receiving their 3G network from the base stations. A jammer is any device that
deliberately blocks, jam or interferes with authorized wireless communications . In
many countries, jammers are illegal and their use can result in large fines. A
mobile phone jammer is an instrument used to prevent cellular phones from
receiving signal from based station. Jammer should recognize that power. Power of
jamming signal should match the power increase from the phone. Sophisticated
jammers can block several networks to head off dual or tri-mode phone that
automatically switch among different network to fin It overpowers the mobile
receiving networks by transmitting the same frequency received by mobile phones.
We have designed a block diagram of mobile jammer which shows the flow of our
project. We have designed it in a way which gives full details about each block,
how a jamming signal is transmitting i.e. how it will jam a mobile phone.
Cell phone jammer with prescheduled time duration
BLOCK DIAGRAM
Cell phone jammer with prescheduled time duration
WORKING PRINCIPLE
The block diagram of the system that to set the scheduled time duration for mobile
jammer. The activation and deactivation time schedules can be programmed with
microcontroller. In order to run the RTC (real time clock) one crystal oscillator is
externally interfaced, an oscillator is an electronic circuit that produces a repetitive
electronic signal. The power supply interfaced it is used to battery backup for the
purpose of update the time when the absence of power. The A.C input i.e., 230v
from the mains supply is step down by the transformer to 12v and is fed to a
rectifier. One reset button interface, Reset is used for putting the microcontroller
Cell phone jammer with prescheduled time duration
into a „known‟ condition. That partially means that microcontroller can behave
rather inaccurately under certain undesirable condition. In order to continuous its
proper functioning it has to be reset. Relay is an electrically controllable switch
widely used in industrial controls, automobile and appliances. One LCD (liquid
crystal display) also interface in this micro controller, it is flat electronic visual
display that used that use the light modulating properties of liquid crystals. These
components are specialized for being used with the microcontrollers, which means
that they cannot be activated by standard IC circuits. RTC (real time clock) is
interface because it is widely used device that provides accurate time and date for
many applications. LED indicator interface in this microcontroller it have a life of
at last ten years and consumer 90 percent less power than conventional indicators,
depend on the type of the materials (Ga, AS, p).
ADVANTAGES
Less Implementation Complexity
Robustness Against Narrowband Interference
Immune to Frequency Selective Fading
High Spectral Efficiency
Using 3g network for speed
Cell phone jammer with prescheduled time duration
SOFTWARE DISCRIPSION
PIC KIT-2 SOFTWARE
Information contained in this publication regarding device applications and the like is
provided only for your convenience and may be superseded by updates. It is your
responsibility to ensure that your application meets with your specifications.
Microchip makes no representations or warranties of any kind whether express or
implied, written or oral, statutory or otherwise, related to the information, including
but not limited to its condition, quality, performance, merchantability or fitness for
purpose. Microchip disclaims all liability arising from this information and its use.
Use of microchip devices in life support and/or safety applications is entirely at the
buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip
from any and all damages, claims, suits, or expenses resulting from such use. No
licenses are conveyed, implicitly or otherwise, under any microchip intellectual
property rights
The PICKit 2 Development Programmer/Debugger kit contains the following items:
1. The PICKit 2 Development Programmer/Debugger
2. USB cable
3. PICKit Starter Kit and MPLAB IDE CD-ROMs Additionally, the PICKit 2 Starter
Kit and PICKit 2 Debug Express kit both contain a demo board with a PIC
microcontroller device.
The PICKit 2 Development Programmer/Debugger is a low-cost development
programmer. It is capable of programming most of Microchips Flash
microcontrollers and serial EEPROM devices. For specific device support, see the
README file included on the PICKit 2 Starter Kit CD-ROM.
Cell phone jammer with prescheduled time duration
PICKit 2 PROGRAMMER APPLICATION
The PICKit 2 Programmer application allows you to program all supported devices
listed in the PICKit 2 Readme file. The programming interface appears. Its controls
are listed in the following sections. For more information on how to install and use
the PICKit 2 Programmer application, see Chapter 2. Picket 2 Programmers Getting
Started.
Cell phone jammer with prescheduled time duration
Menu Bar
The menu bar selects various functions of the PICKit 2 Programmer application. A
summary of the functions are:
File
Cell phone jammer with prescheduled time duration
Import Hex. Import a hex file for programming. The hex file format INHX32 is
supported.
Export Hex. Export a hex file read from a device. The hex file is created in the
NHX32 format.
File History Up to the last four hex files opened are displayed with their file path.
These recent hex files may be selected to quickly import them. Note that the file
history will initially be blank on a new installation until a hex file is imported.
Exit. Exit the program.
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This CD-ROM contains the code files that are used in each chapter of this
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Cell phone jammer with prescheduled time duration
examples that will help solve the problems you might face while developing
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Cell phone jammer with prescheduled time duration
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HARDWARE REQUIREMENT
1. POWER SUPPLY
2. MICROCONTROLLER
3. LCD DISPLAY
4. MOTORS
POWER SUPPLY
Cell phone jammer with prescheduled time duration
In most of our electronic products or projects we need a power supply for converting
mains AC voltage to a regulated DC voltage. For making a power supply
designing of each and every component is essential. Here I’m going to discuss the
designing of regulated 5V Power Supply.
Let’s start with very basic things the choosing of components
Component List :
1. Step down transformer
2. Voltage regulator
3. Capacitors
4. Diodes
Let’s get into detail of rating of the devices:
7805 IC Rating :
Input voltage range 7V- 35V
Current rating Ic = 1A
Output voltage range VMax=5.2V ,VMin=4.8V
LM7805 – Pin Diagram
Transformer:
Cell phone jammer with prescheduled time duration
Selecting a suitable transformer is of great importance. The current rating and the
secondary voltage of the transformer is a crucial factor.
The current rating of the transformer depends upon the current required for the load
to be driven.
The input voltage to the 7805 IC should be at least 2V greater than the required 2V
output; therefore it requires an input voltage at least close to 7V.
So I chose a 6-0-6 transformer with current rating 500mA (Since 6*√2 = 8.4V).
MICROCONTROLLER
High-Performance RISC CPU:
• Only 35 single-word instructions to learn
• All single-cycle instructions except for program branches, which are two-cycle
• Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle
• Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data
Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory
• Pin out compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX
microcontrollers
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via
external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. Resolution is 12.5 ns
- Compare is 16-bit, max. Resolution is 200 ns
- PWM max. Resolution is 10-bit
Cell phone jammer with prescheduled time duration
• Synchronous Serial Port (SSP) with SPI™ (Master mode) and I2C™ (Master/Slave)
• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-
bit address detection
• Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and CS controls
(40/44-pin only)
• Brown-out detection circuitry for Brown-out Reset (BOR)
Analog Features:
• 10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
• Brown-out Reset (BOR)
• Analog Comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference (VREF) module
- Programmable input multiplexing from device inputs and internal voltage reference
- Comparator outputs are externally accessible Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• Data EEPROM Retention > 40 years
• Self-reprogrammable under software control
• In-Circuit Serial Programming™ (ICSP™) via two pins
• Single-supply 5V In-Circuit Serial Programming
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable code protection
• Power saving Sleep mode
• Selectable oscillator options
• In-Circuit Debug (ICD) via two pins CMOS Technology:
Cell phone jammer with prescheduled time duration
• Low-power, high-speed Flash/EEPROM technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Commercial and Industrial temperature ranges
• Low-power consumption
DEVICE OVERVIEW
This document contains device specific information about the following devices:
• PIC16F873A
Cell phone jammer with prescheduled time duration
• PIC16F874A
• PIC16F876A
• PIC16F877A
PIC16F873A/876A devices are available only in 28-pin packages, while
PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All devices
in the PIC16F87XA family share common architecture with the following
differences:
• The PIC16F873A and PIC16F874A have one-half of the total on-chip memory of
the PIC16F876A and PIC16F877A
• The 28-pin devices have three I/O ports, while the 40/44-pin devices have five
• The 28-pin devices have fourteen interrupts, while the 40/44-pin devices have
fifteen
• The 28-pin devices have five A/D input channels, while the 40/44-pin devices have
eight
• The Parallel Slave Port is implemented only on the 40/44-pin devices.
The available features are summarized. Block diagrams of the PIC16F873A/876A
and PIC16F874A/877A devices are provided respectively. The pin outs for these
device families are listed. Additional information may be found in the PICmicro®
Mid-Range Reference Manual (DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from the Microchip web site. The
Reference Manual should be considered a complementary document to this data sheet
and is highly recommended reading for a better understanding of the device
architecture and operation of the peripheral modules.
MEMORY ORGANIZATION
There are three memory blocks in each of the PIC16F87XA devices. The program
memory and data memory have separate buses so that concurrent access can occur
and is detailed in this section. The EEPROM data memory block is detailed “Data
Cell phone jammer with prescheduled time duration
EEPROM and Flash Program Memory”. Additional information on device memory
may be found in the PICmicro® Mid-Range MCU Family Reference Manual.
Program Memory Organization The PIC16F87XA devices have a 13-bit program
counter capable of addressing an 8K word x 14 bit program memory space. The
PIC16F876A/877A devices have 8K words x 14 bits of Flash program memory,
while PIC16F873A/874A devices have 4K words x 14 bits. Accessing a location
above the physically implemented address will cause a wraparound. The Reset vector
is at 0000h and the interrupt vector is at 0004h.
Data Memory Organization
The data memory is partitioned into multiple banks which contain the General
Purpose Registers and the Special Function Registers. Bits RP1 (Status<6>) and
RP0 (Status<5>) are the bank select bits.
Status Register
The Status register contains the arithmetic status of the ALU, the Reset status and the
bank select bits for data memory. The Status register can be the destination for any
instruction, as with any other register. If the Status register is the destination for an
instruction that affects the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the device logic. Furthermore, the
TO and PD bits are not writable, therefore, the result of an instruction with the Status
register as destination may be different than intended.
DATA EEPROM AND FLASH PROGRAM MEMORY
The data EEPROM and Flash program memory is readable and writable during
normal operation (over the full VDD range). This memory is not directly mapped in
the register file space. Instead, it is indirectly addressed through the Special Function
Registers. There are six SFRs used to read and write this memory: • EECON1 •
Cell phone jammer with prescheduled time duration
EECON2 • EEDATA • EEDATH • EEADR • EEADRH When interfacing to the data
memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed. These devices have 128 or 256
bytes of data EEPROM (depending on the device), with an address range from 00h to
FFh. On devices with 128 bytes, addresses from 80h to FFh are unimplemented and
will wraparound to the beginning of data EEPROM memory. When writing to
unimplemented locations, the on-chip charge pump will be turned off. When
interfacing the program memory block, the EEDATA and EEDATH registers form a
two-byte word that holds the 14-bit data for read/write and the EEADR and
EEADRH registers form a two-byte word that holds the 13-bit address of the
program memory location being accessed. These devices have 4 or 8K words of
program Flash, with an address range from 0000h to 0FFFh for the
PIC16F873A/874A and 0000h to 1FFFh for the PIC16F876A/877A. Addresses
above the range of the respective device will wraparound to the beginning of program
memory. The EEPROM data memory allows single-byte read and write. The Flash
program memory allows single-word reads and four-word block writes. Program
memory write operations automatically perform an erase-beforewrite on blocks of
four words. A byte write in data EEPROM memory automatically erases the location
and writes the new data (erase-before-write). The write time is controlled by an on-
chip timer. The write/erase voltages are generated by an on-chip charge pump, rated
to operate over the voltage range of the device for byte or word operations. When the
device is code-protected, the CPU may continue to read and write the data EEPROM
memory. Depending on the settings of the write-protect bits, the device may or may
not be able to write certain blocks of the program memory; however, reads of the
program memory are allowed. When code-protected, the device programmer can no
longer access data or program memory; this does NOT inhibit internal reads or
writes.
Cell phone jammer with prescheduled time duration
I/O PORTS
Some pins for these I/O ports are multiplexed with an alternate function for the
peripheral features on the device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin. Additional information on I/O ports
may be found in the PICmicro™ Mid-Range Reference Manual (DS33023).
PORTA and the TRISA Register
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register
is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an
input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing
a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the
contents of the output latch on the selected pin). Reading the PORTA register reads
the status of the pins, whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that
the port pins are read, the value is modified and then written to the port data latch.
Pin RA4 is multiplexed with the Timer0 module clock input to become the
RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other PORTA pins have TTL input levels and full CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs and the analog VREF input
for both the A/D converters and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits in the ADCON1 and/or
CMCON registers.
PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register
is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB
Cell phone jammer with prescheduled time duration
pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin). Three pins of PORTB are
multiplexed with the In-Circuit Debugger and Low-Voltage Programming function:
RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these pins are
described in Section 14.0 “Special Features of the CPU”. Each of the PORTB pins
has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is
automatically turned off when the port pin is configured as an output. The pull-ups
are disabled on a Power-on Reset.
PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register
is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin). PORTC is multiplexed with
several peripheral functions (Table 4-5). PORTC pins have Schmitt Trigger input
buffers. When the I2C module is enabled, the PORTC<4:3> pins can be configured
with normal I2C levels, or with SMBus levels, by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be taken in defining TRIS bits for
each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals
override the TRIS bit to make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify write instructions (BSF, BCF,
XORWF) with TRISC as the destination, should be avoided. The user should refer to
the corresponding peripheral section for the correct TRIS bit settings.
Cell phone jammer with prescheduled time duration
PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually
configurable as an input or output. PORTD can be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE
(TRISE<4>). In this mode, the input buffers are TTL.
PORTE and TRISE Register
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are
individually configurable as inputs or outputs. These pins have Schmitt Trigger input
buffers. The PORTE pins become the I/O control inputs for the microprocessor port
when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make certain
that the TRISE<2:0> bits are set and that the pins are configured as digital inputs.
Also, ensure that ADCON1 is configured for digital I/O. In this mode, the input
buffers are TTL. Register 4-1 shows the TRISE register which also controls the
Parallel Slave Port operation. PORTE pins are multiplexed with analog inputs. When
selected for analog input, these pins will read as ‘0’s. TRISE controls the direction of
the RE pins, even when they are being used as analog inputs. The user must make
sure to keep the pins configured as inputs when using them as analog inputs.
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on the PIC16F873A or
PIC16F876A. PORTD operates as an 8-bit wide Parallel Slave Port, or
microprocessor port, when control bit PSPMODE (TRISE) is set. In Slave mode, it is
asynchronously readable and writable by the external world through RD control input
pin, RE0/RD/AN5, and WR control input pin, RE1/WR/AN6. The PSP can directly
interface to an 8-bit microprocessor data bus. The external microprocessor can read
Cell phone jammer with prescheduled time duration
or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin
RE0/RD/AN5 to be the RD input, RE1/WR/AN6 to be the WR input and
RE2/CS/AN7 to be the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register (TRISE) must be configured
as inputs (set). The A/D port configuration bits, PCFG3:PCFG0 (ADCON1), must be
set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches: one
for data output and one for data input. The user writes 8-bit data to the PORTD data
latch and reads data from the port pin latch (note that they have the same address). In
this mode, the TRISD register is ignored since the external device is controlling the
direction of data flow. A write to the PSP occurs when both the CS and WR lines are
first detected low. When either the CS or WR lines become high (level triggered), the
Input Buffer Full (IBF) status flag bit (TRISE) is set on the Q4 clock cycle, following
the next Q2 cycle, to signal the write is complete. The interrupt flag bit, PSPIF
(PIR1), is also set on the same Q4 clock cycle. IBF can only be cleared by reading
the PORTD input latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE) is
set if a second write to the PSP is attempted when the previous byte has not been read
out of the buffer. A read from the PSP occurs when both the CS and RD lines are first
detected low. The Output Buffer Full (OBF) status flag bit (TRISE) is cleared
immediately indicating that the PORTD latch is waiting to be read by the external
bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag
bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that
the read is complete. OBF remains low until data is written to PORTD by the user
firmware.
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
Cell phone jammer with prescheduled time duration
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external is a block diagram of the Timer0 module and the prescaler
shared with the WDT. Additional information on the Timer0 module is available in
the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). Timer mode
is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without prescaler). If the TMR0
register is written, the increment is inhibited for the following two instruction cycles.
The user can work around this by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode,
Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail “Using Timer0 with an External Clock”.
The prescaler is mutually exclusively shared between the Timer0 module and the
Watchdog Timer. The prescaler is not readable or writable. “Prescaler” details the
operation of the prescaler.
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers
(TMR1H and TMR1L) which are readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt
Cell phone jammer with prescheduled time duration
flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
• As a Timer
• As a Counter
The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a post scalar. It can be used as the PWM
time base for the PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device Reset. The input clock
(FOSC/4) has a prescaler option of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period
register, PR2. Timer2 increments from 00h until it match PR2 and then resets to 00h
on the next increment cycle. PR2 is a readable and writable register. The PR2 register
is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit post
scalar (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt
(latched in flag bit, TMR2IF (PIR1<1>)). Timer2 can be shut-off by clearing control
bit, TMR2ON (T2CON<2>), to minimize power consumption.
CAPTURE/COMPARE/PWM MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Cell phone jammer with prescheduled time duration
Both the CCP1 and CCP2 modules are identical in operation, with the exception
being the operation of the special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In the following sections, the
operation of a CCP module is described with respect to CCP1. CCP2 operates the
same as CCP1 except where noted.
CCP1 Module:
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers:
CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the
operation of CCP1. The special event trigger is generated by a compare match and
will reset Timer1.
LCD 16X2
Alphanumeric displays are used in a wide range of applications, including palmtop
computers, word processors, photocopiers, point of sale terminals, medical
instruments, cellular phones, etc. The 16 x 2 intelligent alphanumeric dot matrix
displays is capable of displaying 224 different characters and symbols. A full list of
the characters and symbols is printed on pages 7/8 (note these symbols can vary
between brand of LCD used). This booklet provides all the technical specifications
for connecting the unit, which requires a single power supply (+5V). Available as an
optional extra is the Serial LCD Firmware, which allows serial control of the display.
This option provides much easier connection and use of the LCD module. The
firmware enables microcontrollers (and microcontroller based systems such as the
PICAXE) to visually output user instructions or readings onto an LCD module. All
LCD commands are transmitted serially via a single microcontroller pin. The
firmware can also be connected to the serial port of a computer.
Cell phone jammer with prescheduled time duration
MOTOR
The unit operates on 1.5 - 3v (917D & 917D/A, also with higher torque motor 920D
& 920D/A), or 12-24v (927D & 927D/A) D.C. power sources, either battery or
suitable transformer. Its simple versatile design and sturdy construction make it
suitable for a host of uses from powering models and robots to teaching the principles
of mechanics. Current consumption depends on eventual load but is within the range
0.2 to 0.8n amps. The output shaft is 3mm diameter. Designed for heavy-duty
industrial and model applications this robust unit boasts a powerful high quality,
three pole motor with sintered bronze bearings. The all steel gearbox incorporates
bronze output bearings, enabling the high torque transfer from the motor to be
transmitted through the gearbox. The unit is mounted on a 1mm thick plated steel
bracket.
RF section:
This is the most important part of the jammer, since the output of this section will be
interfacing with the mobile. The RF-section consists of three main parts: voltage
controlled oscillator VCO, power amplifier and antenna. The voltage controlled
oscillator (VCO) is the heart of the RF-section. It is the device that generates the RF
signal which will interfere with the cell phone. The output of the VCO has a
frequency which is proportional to the input voltage, thus, we can control the output
frequency by changing the input voltage. When the input voltage is DC, the output is
a specific frequency, while if the input is a triangular waveform, the output will span
a specific frequency range. In our design, we need to find a VCO for GSM 900 and
GSM 1800. There are three selection criteria for selecting a VCO for this application.
Most importantly, it should cover the bands that we need, secondly, it should be
readily available at low cost, and finally, it should run at low power consumption.
Cell phone jammer with prescheduled time duration
Moreover, we need to minimize the size of GSM-jammer. So, we started to search
through the internet for VCO's that work for GSM 900 & GSM 1800 bands.
Finally, we found the following VCO IC’s:-
CVCO55BE; this is for GSM 1800. The output frequency is 1785-1900 MHz and the
output power is up to 5 dBm.
CVCO55CL; this is for GSM 900. The output frequency is 925-970 MHz and the
output power is up to 8 dBm.
We chose these IC’s for the following reasons:-
[A] Surface mount, which reduces the size of product.
[B] Having large output power that reduces the number of amplification stages that
we need.
[C] Having same value of power supply which is typically equal to 5 volt.
[D] Having same noise properties.
Cell phone jammer with prescheduled time duration
CONCLUSION
While testing a jammer we observed that jamming range depends on surroundings
and signal strength in that surrounding. In low network areas, the jamming range
increases to 20 meters also. In general, the jamming attack was protected by
network signal power, and having jammer with high power there is guarantee of
jamming quickly. From above all observation, it can be concluded that the cell
phone jammer worked efficiently And its automatically deactivated by using the
frequency generator.A most of the areas where there is need to jam the signal for
maintaining silence and peace for the people. Also there is need of more powerful
jamming devices for large space. However our jammer is effective in short space
requirements. This work is intended to provide an open base for developing the
prototype in the form of hardware, software, range of antenna etc.
Cell phone jammer with prescheduled time duration
References
[1] Rick Hartley, RF / Microwave PC Board Design and Layout, Avionics
Systems.
[2] John Scourias, Overview of the Global System for Mobile Communications,
University of Waterloo.
[3] Ahmed Jisrawi, "GSM 900 Mobile Jammer", undergrad project, JUST, 2006.
[4] Limor Fried, Social Defense Mechanisms: Tools for Reclaiming our Personal
Space.
[5] Siwiak, K., Radio-wave propagation and Antennas for personal
communication.
[6] Pozar, D., Microwave Engineering, John Wiley and Sons, 2005.
[7] "FREQUENCY PLANNING AND FREQUENCY COORDINATION FOR
THE GSM 900, GSM 1800, E-GSM and GSM-R LAND MOBILE SYSTEMS
(Except direct mode operation (DMO) channels)" by Working Group Frequency
Management" (WGFM).