Transcript
Page 1: Ch 4. Combinational Logic Design Principles

Ch 4. Combinational Logic Design Principles

• Combinational Logic Circuit– Outputs depend only on its current inputs– No feedback loop

• Sequential Logic Circuit– Outputs depend on its current inputs and present states– Feedback loop

Page 2: Ch 4. Combinational Logic Design Principles

4.1 Switching Algebra

Page 3: Ch 4. Combinational Logic Design Principles

‘+’ : ‘OR’

‘’ : ‘AND’

Page 4: Ch 4. Combinational Logic Design Principles
Page 5: Ch 4. Combinational Logic Design Principles
Page 6: Ch 4. Combinational Logic Design Principles

& are obvious (by perfect induction)

is identical to the distributive law for integers and reals

Switching-algebra theorems

Page 7: Ch 4. Combinational Logic Design Principles
Page 8: Ch 4. Combinational Logic Design Principles
Page 9: Ch 4. Combinational Logic Design Principles
Page 10: Ch 4. Combinational Logic Design Principles

NAND

DeMorgan’s Th.

Page 11: Ch 4. Combinational Logic Design Principles

NOR

DeMorgan’s Th.

Page 12: Ch 4. Combinational Logic Design Principles

Black box Representation with Truth table

Active Low

Page 13: Ch 4. Combinational Logic Design Principles

Active Low

Black box Representation with Truth table

Page 14: Ch 4. Combinational Logic Design Principles
Page 15: Ch 4. Combinational Logic Design Principles

DualityPositive Negative 𝑭 (𝑿𝟏 ,𝑿𝟐 ,… 𝑿𝒏 )⇒ 𝑭 𝑫 (𝑿𝟏

′ , 𝑿𝟐′ ,…𝑿𝒏′ )

𝑭 (𝑿𝟏 ,𝑿𝟐 ,… 𝑿𝒏 )=[𝑭 𝑫 (𝑿𝟏′ ,𝑿𝟐

′ ,…𝑿𝒏′ ) ]′

[𝑭 (𝑿𝟏 ,𝑿𝟐 ,…𝑿𝒏 ) ]′=[𝑭 𝑫 (𝑿𝟏′ , 𝑿𝟐

′ ,… 𝑿𝒏′ ) ]❑

→𝑮𝒆𝒏𝒆𝒓𝒂𝒍𝒊𝒛𝒆𝒅 𝑫𝒆𝑴𝒐𝒓𝒈𝒂𝒏′ 𝒔𝑻𝒉 .

𝑫𝒖𝒂𝒍𝒊𝒕𝒚

Page 16: Ch 4. Combinational Logic Design Principles

Function with 3 inputX, Y, Z

Page 17: Ch 4. Combinational Logic Design Principles

𝑭 (𝑿 ,𝒀 ,𝒁 )

Page 18: Ch 4. Combinational Logic Design Principles

𝑪𝒂𝒏𝒐𝒏𝒊𝒄𝒂𝒍 𝑺𝒖𝒎−𝑨𝒔𝒖𝒎𝒐𝒇 𝒎𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝒕𝒐𝒑𝒓𝒐𝒅𝒖𝒄𝒆𝒐𝒖𝒕𝒑𝒖𝒕𝒔 ′ 𝟏 ′

DeMorgan’s Th.

Page 19: Ch 4. Combinational Logic Design Principles

4.2 Combinational-Circuit Analysis

Page 20: Ch 4. Combinational Logic Design Principles

F(X, Y, Z)

Page 21: Ch 4. Combinational Logic Design Principles

F(X, Y, Z)

Page 22: Ch 4. Combinational Logic Design Principles

¿ 𝑿𝒁+𝒀 ′ 𝒁+𝑿 ′𝒀𝒁 ′

Three-level without considering inverter

Page 23: Ch 4. Combinational Logic Design Principles
Page 24: Ch 4. Combinational Logic Design Principles

(𝑽 ∙𝑾 ∙𝐗 )+ (𝐘 ∙𝒁 )=(𝑽 +𝒀 ) ∙ (𝑽 +𝒁 ) ∙ (𝑾 +𝒀 ) ∙(𝑾 +𝒁 )∙(𝑿+𝒀 ) ∙(𝑿+𝒁 )

“Add-out” to obtain a product of sums by T8’

T8’

Sum of products

Product of sums

(Figure 4-12)

(Figure 4-13)

Same

Page 25: Ch 4. Combinational Logic Design Principles
Page 26: Ch 4. Combinational Logic Design Principles
Page 27: Ch 4. Combinational Logic Design Principles
Page 28: Ch 4. Combinational Logic Design Principles
Page 29: Ch 4. Combinational Logic Design Principles

4.3 Combinational-Circuit Synthesis

Prime number detector

Page 30: Ch 4. Combinational Logic Design Principles

¿𝑷𝒂𝒏𝒊𝒄+𝑬𝒏𝒂𝒃𝒍𝒆 ∙𝑬𝒙𝒊𝒕𝒊𝒏𝒈 ′ ∙𝑺𝒆𝒄𝒖𝒓𝒆 ′

Page 31: Ch 4. Combinational Logic Design Principles
Page 32: Ch 4. Combinational Logic Design Principles
Page 33: Ch 4. Combinational Logic Design Principles
Page 34: Ch 4. Combinational Logic Design Principles
Page 35: Ch 4. Combinational Logic Design Principles

𝒏𝒐𝒏𝒔𝒕𝒂𝒏𝒅𝒂𝒓𝒅𝒈𝒂𝒕𝒆

𝒆𝒍𝒎𝒊𝒏𝒂𝒕𝒆𝒔 𝒏𝒐𝒏𝒔𝒕𝒂𝒏𝒅𝒂𝒓𝒅𝒈𝒂𝒕𝒆

NAND

NOR

Page 36: Ch 4. Combinational Logic Design Principles

𝐹= ∑𝑁3𝑁2𝑁1𝑁0

(1,3,5,7,2,11,13 )

Page 37: Ch 4. Combinational Logic Design Principles

𝑮𝒓𝒂𝒚 𝑺𝒆𝒒𝒖𝒆𝒏𝒄𝒆

𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝑮𝒓𝒂𝒚 𝑺𝒆𝒒𝒖𝒆𝒏𝒄𝒆

Page 38: Ch 4. Combinational Logic Design Principles
Page 39: Ch 4. Combinational Logic Design Principles
Page 40: Ch 4. Combinational Logic Design Principles
Page 41: Ch 4. Combinational Logic Design Principles
Page 42: Ch 4. Combinational Logic Design Principles
Page 43: Ch 4. Combinational Logic Design Principles
Page 44: Ch 4. Combinational Logic Design Principles

𝒅𝒊𝒔𝒕𝒊𝒏𝒈𝒖𝒊𝒔𝒉𝒆𝒅𝟏−𝒄𝒆𝒍𝒍𝒔

𝑬𝑷𝑰

𝑬𝑷𝑰

Page 45: Ch 4. Combinational Logic Design Principles
Page 46: Ch 4. Combinational Logic Design Principles
Page 47: Ch 4. Combinational Logic Design Principles
Page 48: Ch 4. Combinational Logic Design Principles
Page 49: Ch 4. Combinational Logic Design Principles
Page 50: Ch 4. Combinational Logic Design Principles
Page 51: Ch 4. Combinational Logic Design Principles
Page 52: Ch 4. Combinational Logic Design Principles
Page 53: Ch 4. Combinational Logic Design Principles
Page 54: Ch 4. Combinational Logic Design Principles
Page 55: Ch 4. Combinational Logic Design Principles
Page 56: Ch 4. Combinational Logic Design Principles
Page 57: Ch 4. Combinational Logic Design Principles
Page 58: Ch 4. Combinational Logic Design Principles
Page 59: Ch 4. Combinational Logic Design Principles

4.4 Timing Hazards

𝑿𝒁𝑷=𝟏𝑿=𝟏

𝐘 𝒁=𝟎

Unwanted Output

Static-1 Hazard : Momentary output ‘0’ to occur during a transition in the differing input variable

Static-0 Hazard : Momentary output ‘1’ to occur during a transition in the differing input variable

Page 60: Ch 4. Combinational Logic Design Principles

Unwanted Output

Page 61: Ch 4. Combinational Logic Design Principles
Page 62: Ch 4. Combinational Logic Design Principles

𝑻𝒐𝒆𝒍𝒊𝒎𝒊𝒏𝒂𝒕𝒆 𝒔𝒕𝒂𝒕𝒊𝒄𝟏−𝒉𝒂𝒛𝒂𝒓𝒅

Page 63: Ch 4. Combinational Logic Design Principles
Page 64: Ch 4. Combinational Logic Design Principles
Page 65: Ch 4. Combinational Logic Design Principles
Page 66: Ch 4. Combinational Logic Design Principles
Page 67: Ch 4. Combinational Logic Design Principles
Page 68: Ch 4. Combinational Logic Design Principles
Page 69: Ch 4. Combinational Logic Design Principles

Top Related