Download - Chapter 08 Central Processing Unit
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Princess Sumaya Univ.Computer Engineering Dept.
Chapter 8:Chapter 8:
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.
Register File
CPUCPU
CU
ALU
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.General Register OrganizationGeneral Register Organization
R1
R2
R3
R4
R5
R6
R7
MUX MUX
ALU
3 x 8Decoder
LD
SELD
SELA SELB
OPR
Input
A B
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.General Register OrganizationGeneral Register Organization
OPR Operation00000 Transfer A00001 Increment A00010 Add A + B00101 Subtract A − B00110 Decrement A01000 AND A and B01010 OR A and B01100 XOR A and B01110 Complement A10000 Shift right A11000 Shift left A
R1
R2
R3
R4
R5
R6
R7
MUX MUX
ALU
3 x 8Decoder
LD
SELD
SELA SELB
OPR
Input
A B
Examples: Microoperation SELA SELB SELD OPRR1 ← R2 − R3 010 011 001 00101R4 ← SHL R4 100 000 100 11000
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Stack OrganizationStack Organization
SP
Stack Bottom
CurrentTop of Stack
TOS
LIFO
Last In First Out0
1
2
3
4
7
8
9
10
5
6
Stack
0 0 5 5
0 0 0 8
0 0 2 5
0 0 1 5
0 1 2 3
FULL EMPTY
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Stack OrganizationStack Organization
SP
Stack Bottom
CurrentTop of Stack
TOS
PUSH
SP ← SP – 1
M[SP] ← DR
If (SP = 0) then (FULL ← 1)
EMPTY ← 0
0
1
2
3
4
7
8
9
10
5
6
Stack
0 0 5 5
0 0 0 8
0 0 2 5
0 0 1 5
0 1 2 3
FULL EMPTY
1 6 9 0
1 6 9 0CurrentTop of Stack
TOS
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Stack OrganizationStack Organization
SP
Stack Bottom
CurrentTop of Stack
TOS
POP
DR ← M[SP]
SP ← SP + 1
If (SP = 11) then (EMPTY ← 1)
FULL ← 0
0
1
2
3
4
7
8
9
10
5
6
Stack
0 0 5 5
0 0 0 8
0 0 2 5
0 0 1 5
0 1 2 3
FULL EMPTY
1 6 9 01 6 9 0
CurrentTop of Stack
TOS
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.
0
1
2
102
202
201
200
100
101
Stack OrganizationStack Organization
Memory Stack
● PUSH
SP ← SP – 1
M[SP] ← DR
● POP
DR ← M[SP]
SP ← SP + 1
PC
AR
SP
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Reverse Polish NotationReverse Polish Notation
Infix Notation
A + B
Prefix or Polish Notation
+ A B
Postfix or Reverse Polish Notation (RPN)
A B +
A B + C D A B C D +RPN
(2) (4) (3) (3) +
(8) (3) (3) +
(8) (9) +
17
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Reverse Polish NotationReverse Polish Notation
Example
(A + B) [C (D + E) + F]
(A B +) (D E +) C F +
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Reverse Polish NotationReverse Polish Notation
Stack Operation
(3) (4) (5) (6) +
PUSH 3
PUSH 4
MULT
PUSH 5
PUSH 6
MULT
ADD
3
4
12
5
6
30
42
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.CPU OrganizationCPU Organization
Single Accumulator
● Result usually goes to the Accumulator
● Accumulator has to be saved to memory quite often
General Register
● Registers hold operands thus reduce memory traffic
● Register bookkeeping
Stack
● Operands and result are always in the stack
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Instruction FormatsInstruction Formats
Three-Address Instructions● ADD R1, R2, R3 R1 ← R2 + R3
Two-Address Instructions● ADD R1, R2 R1 ← R1 + R2
One-Address Instructions● ADD M AC ← AC + M[AR]
Zero-Address Instructions● ADD TOS ← TOS + (TOS – 1)
RISC Instructions● Lots of registers. Memory is restricted to Load & Store
Opcode Operand(s) or Address(es)
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Instruction FormatsInstruction Formats
Example: Evaluate (A+B) (C+D)
Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1 R2
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Instruction FormatsInstruction Formats
Example: Evaluate (A+B) (C+D)
Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1 R2
6. MOV X, R1 ; M[X] ← R1
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Instruction FormatsInstruction Formats
Example: Evaluate (A+B) (C+D)
One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC M[T]
7. STORE X ; M[X] ← AC
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Instruction FormatsInstruction Formats
Example: Evaluate (A+B) (C+D)
Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Instruction FormatsInstruction Formats
Example: Evaluate (A+B) (C+D)
RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1 R3
8. STORE X, R1 ; M[X] ← R1
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Addressing ModesAddressing Modes
Implied
● AC is implied in “ADD M[AR]” in “One-Address” instr.
● TOS is implied in “ADD” in “Zero-Address” instr.
Immediate
● The use of a constant in “MOV R1, 5”, i.e. R1 ← 5
Register
● Indicate which register holds the operand
Opcode Mode ...
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Addressing ModesAddressing Modes
Register Indirect
● Indicate the register that holds the number of the register that holds the operand
MOV R1, (R2)
Autoincrement / Autodecrement
● Access & update in 1 instr.
Direct Address
● Use the given address to access a memory location
R1
R2 = 3
R3 = 5
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Addressing ModesAddressing Modes
Indirect Address
● Indicate the memory location that holds the address of the memory location that holds the data
AR = 101
100
101
102
103
104
0 1 0 4
1 1 0 A
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.
100
101
102
103
104
0
1
2
Addressing ModesAddressing Modes
Relative Address
● EA = PC + Relative Addr
AR = 100
1 1 0 A
PC = 2
+
Could be Positive or Negative
(2’s Complement)
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Addressing ModesAddressing Modes
Indexed
● EA = Index Register + Relative Addr
100
101
102
103
104
AR = 100
1 1 0 A
XR = 2
+
Could be Positive or Negative
(2’s Complement)
Useful with “Autoincrement” or “Autodecrement”
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Addressing ModesAddressing Modes
Base Register
● EA = Base Register + Relative Addr
100
101
102
103
104
BR = 100
0 0 0 A
AR = 2
+
Could be Positive or Negative
(2’s Complement)
Usually points to the beginning
of an array
0 0 0 5
0 0 1 2
0 1 0 7
0 0 5 9
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Types of InstructionsTypes of Instructions
Data Transfer Instructions
Data Manipulation Instructions
Program Control Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data value is not modified
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Data Transfer InstructionsData Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Data Manipulation InstructionsData Manipulation Instructions
Arithmetic
Logical & Bit Manipulation
Shift
Name MnemonicIncrement INCDecrement DEC
Add ADDSubtract SUBMultiply MULDivide DIV
Add with carry ADDCSubtract with borrow SUBB
Negate NEGName MnemonicClear CLR
Complement COMAND ANDOR OR
Exclusive-OR XORClear carry CLRC
Set carry SETCComplement carry COMCEnable interrupt EIDisable interrupt DI
Name MnemonicLogical shift right SHRLogical shift left SHL
Arithmetic shift right SHRAArithmetic shift left SHLA
Rotate right RORRotate left ROL
Rotate right through carry RORCRotate left through carry ROLC
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Program Control InstructionsProgram Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (Subtract) CMP
Test (AND) TST
Subtract A – B but don’t store the result
1 0 1 1 0 0 0 1
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0Mask
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Status BitsStatus Bits
ALU
V Z S C
Zero Check
Cn
Cn-1
Fn-1
A B
F
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Conditional Branch InstructionsConditional Branch Instructions
Mnemonic Branch Condition Tested Condition
BZ Branch if zero Z = 1
BNZ Branch if not zero Z = 0
BC Branch if carry C = 1
BNC Branch if no carry C = 0
BP Branch if plus S = 0
BM Branch if minus S = 1
BV Branch if overflow V = 1
BNV Branch if no overflow V = 0
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Conditional Branch InstructionsConditional Branch Instructions
Example:
● A: 1 1 1 1 0 0 0 0
● B: 0 0 0 1 0 1 0 0
A: 1 1 1 1 0 0 0 0
+(−B): 1 1 1 0 1 1 0 0
1 1 0 1 1 1 0 0
C = 1
S = 1
V = 0
Z = 0
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Program InterruptsProgram Interrupts
Save:
● PC
● Registers
● Status Bits
Main Program • •
••
10 CMA11 •12 STA [201]
•••••
Interrupt
ISR•
Load AC••
RETProgram
Status Word
PSW
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.Types of InterruptsTypes of Interrupts
External Interrupts
● Keyboard, Mouse … etc
Internal Interrupts
● Timers, Divide-By-Zero … etc
Software Interrupts Main Program • •
••
10 INT11 •
••
ISR••••
RET
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.CISCCISC
Complex Instruction Set Computer
● Large number of instructions with a complicated ALU
● Some instructions perform specialized tasks and are used infrequently
● Large variety of addressing modes
● Variable length instruction formats
● Instructions can manipulate operands in memory
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.RISCRISC
Reduced Instruction Set Computer
● Relatively few instructions, hence simple ALU
● Relatively few addressing modes
● Memory access limited to “load” and “store”
● All operations done within “registers” of the CPU
● Fixed-length and easily decoded instruction format
● Single-cycle instruction execution
● Hardwired control unit
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
Chapter 8♦ 8-1♦ 8-3♦ 8-7♦ 8-8♦ 8-9♦ 8-11♦ 8-13♦ 8-14♦ 8-15♦ 8-16♦ 8-17♦ 8-18♦ 8-32
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
Mano8-1 A bus-organized CPU has 16 registers with 32 bits in
each, an ALU, and a destination decoder.
a. How many multiplexers are there in the A bus, and what is the size of each multiplexer?
b. How many selection inputs are needed for MUX A and MUX B?
c. How many inputs and outputs are there in the decoder?
d. How many inputs and outputs are there in the ALU for data, including input and output carries?
e. Formulate a control word for the system assuming that the ALU has 35 operations.
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
8-3 Specify the control word that must be applied to the processor of Fig. 8-2 to implement the following microoperations.
a. R1 ← R2 + R3
b. R4 ← R4
c. R5 ← R5 – 1
d. R6 ← shl R1
e. R7 ← input
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
8-7 Convert the following arithmetic expressions from infix to reverse Polish notation.
a. A B + C D + E F
b. A B + A (B D + C E)
c. A + B [C D + E (F + G)]
A * [B + C (D + E)]d. ─────────────
F (G + H)
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Princess Sumaya University 4343 – Computer Organization & DesignPrincess Sumaya University 4343 – Computer Organization & Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework
8-5 Convert the following arithmetic expressions from reverse Polish notation to infix notation.
a. A B C D E + − /
b. A B C D E / − +
c. A B C / D − E F / +
d. A B C D E F G + + +
8-9 Convert the following numerical arithmetic expression into reverse Polish notation and show the stack operations for evaluating the numerical result.
(3 + 4) [10 (2 + 6) + 8]
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8-11 A computer has 32-bit instructions and 12-bit addresses. If there are 250 two-address instructions, how many one-address instructions can be formulated?
8-13 The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field if the instruction is in one memory word.
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8-14 A two-word instruction is stored in memory at an address designated by the symbol W. The address field of the instruction (stored at W + 1) is designated by the symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by Z. An index register contains the value X. State how Z is calculated from the other addresses if the addressing mode of the instruction is
a. direct
b. indirect
c. relative
d. indexed
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8-15 A relative mode branch type of instruction is stored in memory at an address equivalent to decimal 750. The branch is made to an address equivalent to decimal 500.
a. What should be the value of the relative address field of the instruction (in decimal)?
b. Determine the relative address value in binary using 12 bits. (Why must the number be in 2’s complement?)
c. Determine the binary value in PC after the fetch phase and calculate the binary value of 500. Then show that the binary value in PC plus the relative address calculated in part (b) is equal to the binary value of 500.
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8-16 How many times does the control unit refer to memory when it fetches and executes an indirect addressing mode instruction if the instruction is (a) a computational type requiring an operand from memory; (b) a branch type.
8-17 What must the address field of an indexed addressing mode instruction be to make it the same as a register indirect mode instruction?
8-18 An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is (a) direct; (b) immediate; (c) relative; (d) register direct; (e) index with R1 as the index register.
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8-32 The content of the top of a memory stack is 5320. The content of the stack pointer SP is 3560. A two-word call subroutine instruction is located in memory at address 1120 followed by the address field of 6720 at location 1121. What are the content of PC, SP, and the top of the stack:
a. Before the call instruction is fetched from memory?
b. After the call instruction is executed?
c. After the return from subroutine?