Download - Chapter 1
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Computer Organization
Course Web Sitehttp://www.engr.uconn.edu/~ibrahim/hardware
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Textbooks
Computer Organization, 5th ed. Carl Hamacher, Zvonko Vranesic, Safwat
Zaky
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Processor
Computer Functional Units
Memory
Arithmetic& Logic
Control
I/O
Input
Output
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Course Organization
Computer Structure (Ch 1) Instruction Sets & Addressing Modes (Ch 2) Control Unit Design (Ch 7)
Computer Arithmetic (Ch 6) Memory (Ch 5) Input/Output (Ch 4) Pipelining (Ch 8) Embedded Systems (Ch 9)
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Computer Information (Binary)
(Machine) Instructions (Machine Language) Programs
Data 2's complement BCD ASCII
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Output Display Printer Speakers
I/O
Input Keyboard Mouse Microphone Camera Scanner
Serial Communications Network Modem
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Memory
Primary Random Access
Memory (RAM) Read Only
Memory (ROM)
Organization Word Address Read/Write
Secondary Magnetic
Disks Tape
Optical Disks
Hierarchy Cache Main Virtual
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ALU
Arithmetic Addition Subtraction Multiplication Division Comparison
Logic AND OR NOT XOR
Registers Store Shift
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Control Unit
Coordinates/Directs other Units
Computer Operation Input
Program/Data stored in Memory Processing
Information fetched into RegistersProcessed by ALU
Output
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History
First Generation (miliseconds) von Neumann (stored program) Vacuum Tubes Magnetic Core Memory Teletypes/Magnetic Tapes
Second Generation (microseconds) Transistor High-level Languages (Fortran)
Compilers I/O Processors
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History
Third Generation Integrated Circuits Microprogramming Parallelism/Pipelining Operating Systems (sharing) Cache/VM
Fourth Generation (nanoseconds) VLSI (Single Chip Microprocessor) Personal Computers Networks
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Processor
Computer Functional Units
Memory
Arithmetic& Logic
Control
I/O
Input
Output
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MAR - Memory Address Register
MDR - Memory Data Register
PC - Program Counter
IR - Instruction Register
Control Unit
Arithmetic Logic Unit
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Computer Instructions
Assembly Language
MOVE NUM1,R1
MOVE #1,R2
ADD #1,R1
ADD R1,R2
Register Transfer Notation
R1 [NUM1]
R2 1
R1 1 + [R1]
R2 [R1] + [R2]
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The “fetch-execute cycle”
Fetch the instruction whose address is in the program counter
Increment the PC so it holds the address of the next instruction
Execute the instruction just fetched Fetch the next instruction Etc.
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Arithmetic/Logic Unit
Memory
Control Unit
Instruction Register
Program CounterData Register
Data Register
instruction
instruction fetch
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Memory
CPU
Bus
MAR MDR
instruction address
instruction
PC IR
Memory Control
Instruction Fetch
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Arithmetic/Logic Unit
Memory
Control Unit
Instruction Register
Program CounterData Register
Data Register
data
instruction execute
data
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Memory
CPU
Bus
MAR MDR
operand (data) address
data
IR R1
Memory Control
Instruction Execution
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Example Instruction
Fetch MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]
Execute MAR NUM1 MDR [MEM([MAR])] R1 [MDR]
MOVE NUM1,R1
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Another Example
Fetch MAR [PC] PC [PC] + 1 MDR [MEM([MAR])] IR [MDR]
Execute R1 1 + [R1]
ADD #1,R1
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Single-Bus Structure
Memory ProcessorInput Output
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System Software
Compiler High-level Language Machine Language
Assembler Assembly Language Machine Language
Text Editor Keyboard Input File
Operating System Control Sharing & Interaction Assign & Manage Resources
Memory Disk Space
Handle I/O
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Memory Performance
MainMemory
ProcessorCacheMemory
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Processor Clock
Period (P)
Rate (R)
CLK
R = 1/P
1 GHz = 1/1ns
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Performance Equation
Processor Execution Time (T) Number of Machine Language Instructions (N) Average Steps per Machine Instruction (S) Clock Rate (R)
MIPS: Millions of instructions per second Megaflops: Millions of floating point operations per second Megahertz: Millions of clock cycles per second
T N S
R
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Pipelining
F1 E1
I1
F2 E2
I2
F3 E3
I3
Sequential Execution
F1 E1I1
F2 E2I2
F3 E3I3
Pipelined Execution
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Parallel Processing
Parallel Execution Superscalar
Multiprocessors Shared-Memory
Multicomputers Message-Passing
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Multiprocessing, multitasking.
A system that provides for concurrent execution
of multiple programs, i.e., manages multiple processes
Programs share use of the processor (take turns).
Multiprogramming
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1) Multiprogramming
2) Parallel processing (multiple
processors)
Multiprocessing:
Multitasking:
1) Multiprogramming
2) A particular form of multiprogramming
depending on context
depending on context
Multiprogramming
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Figure 1.4. User program and OS routine sharing of the processor.
Printer
Disk
Program
routinesOS
Timet 0 t 1 t 2 t 3 t 4 t 5
Figure 1.4. User program and OS routine sharing of the processor.
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CISC vs RISC
Complex Instruction Set Computers (CISC) Smaller N Larger S
Reduced Instruction Set Computers (RISC) Larger N Smaller S Easier to Pipeline