Download - Chapter 14 High Speed IO Slides 121107
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
1/44
EE1411
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 1
Chapter 14Chapter 14
HighHigh--Speed I/O InterfaceSpeed I/O Interface
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
2/44
EE1412
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 2
What is this chapter about? What is this chapter about? HighHigh--speed I/O interfacesspeed I/O interfaces
Have been widely used in computer,
communication, and consumer electronics systems Are able to transmit and receive data at higher rates
with fewer I/O pins
Focus on High-speed I/O architectures I/O interface testing
At the Component/subsystem levelAt the System level
Using DFT-assisted Methods
New challenges in high-speed I/O and testing
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
3/44
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
4/44
EE1414
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 4
I. HighI. High--Speed I/O ArchitecturesSpeed I/O Architectures
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
5/44
EE1415
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 5
(a) Global Clock (GC)(a) Global Clock (GC) Synchronized global
clock
System clock for Txdata driving and Rxdata sampling
Clock skew onboard limits its useto < a few 100 Mbpsdata rate
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
6/44
EE1416
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 6
(b) Source Synchronous (SS)(b) Source Synchronous (SS)
Tx sends dataalong with
strobe (anotherclock)
Rx uses sentstrobe to samplethe data
No clock orstrobe skewissue
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
7/44
EE1417
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 7
Source Synchronous (SS) (Cont Source Synchronous (SS) (Cont ’ ’ d)d)
Some designs use strobe/strobe# to improve timing accuracy
Data
Strobe
Strobe#
All driven
bysame bus
clock
& matched
signal
paths
Tvb Tva TvaTvb
Tsetup Thold
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
8/44
EE1418
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 8
Source Synchronous (SS) (Cont Source Synchronous (SS) (Cont ’ ’ d)d) Limited by data to
data skew due touneven channels
Board layout E-M issues: e.g .,
coupling, noises Variation in drive
among channels
Achieve up to~1000 Mbps datarates for wide bus Can improve data
rate with splittinginto many narrower
bus
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
9/44
EE1419
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 9
(c) Embedded Clock (EC)(c) Embedded Clock (EC)
Bit clock is embedded in the serial data and gets recovered at Rx via clock
recovery circuit
Link layer is composed of encoder/decoder Physical layer (PHY) is composed of Tx, channel, and Rx
Jitter is the major limiting factor for EC link architecture
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
10/44
EE14110
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 10
Basics on Jitter, Noise, and Bit Error Rate (BER)Basics on Jitter, Noise, and Bit Error Rate (BER)
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
11/44
EE14111
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 11
Jitter Components and Terminology Jitter Components and Terminology
Jitter
Random
DDJ PJ MGJ GJBUJ
Deterministic
DCD ISICorrelated Jitter
Uncorrelated Jitter
DJ is bounded, and RJ is unbounded
RJ is commonly modeled by a Gaussian
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
12/44
EE14112
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 12
Characteristics of Jitter ComponentCharacteristics of Jitter Component PDFsPDFs
ISI; different waveform traces
DCD: dual peak due to non-ideal reference voltage
PJ: Saddle shape or Golden Gate suspension bridge
RJ: Bell shape or Gaussian
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
13/44
EE14113
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 13
Jitter Separation (a): PDF Based Jitter Separation (a): PDF Based
Tailfit is the industry de facto standard for separating DJ and RJ Use RJ Gaussians to model the Tail distributions
Distance between left and right Gaussian means gives DJ pk-pk
Average of left and right Gaussian sigmas gives DJ sigma
Keep adjusting σ, mean andmagnitude until tails obtain best
fit with the data
σL σR
µL µR
DJ=µL- µR
σRJ=(σL+ σR)/2
mean
mean
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
14/44
EE14114
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 14
Jitter Separation (a): CDF Based (Cont Jitter Separation (a): CDF Based (Cont ’ ’ d)d)
Tailfit the CDFs RJ model is an integrated Gaussian
RJ becomes linear in Q-space
Same basic concept, transformed data and model
0 ts 1 (UI)
CDFL(ts) CDFR(ts)
Integrated
Gaussians /erfc(ts)
B E R C D F ( t s )
10-12 1UI-TJ
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
15/44
EE14115
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 15
Jitter Separation (b): Spectrum Based Jitter Separation (b): Spectrum Based
DDJ the estimated in time-domain via average first PJ is the spikes in the spectrum
RJ the background of the spectrum
f
p s d ( f )
PJRJ
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
16/44
EE14116
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 16
Jitter, Noise, and BER in 2 Jitter, Noise, and BER in 2 - - DimensionDimension
Noise PDFs
Jitter PDFs
BER (10-12) Compliance Zone Both jitter andnoise can causeBER
Eye and BERcontour are 2-dimensional
No dot should be
in the compliancezone to pass
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
17/44
EE14117
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 17
II. Testing of I/O InterfacesII. Testing of I/O Interfaces
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
18/44
EE14118
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 18
Testing Global Clock (GC) I/O Testing Global Clock (GC) I/O
Test with an ATE
Data and clock are
generated and bythe tester (level,pattern, and timing)
Setup and hold timeis controlled by the
tester
Data output isstrobed by thetester
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
19/44
EE14119
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 19
Testing Source Synchronous (SS) I/O Testing Source Synchronous (SS) I/O
It is a difficult task totest SS I/O DUT witha deterministic ATE
that cannot use anexternal DUT clock orstrobe
Strobe may begenerated by tester
via a linear searchthat can be timeconsuming
Strobe timing marginis reduced by thetester accuracy/jitter
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
20/44
EE14120
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 20
Testing Embedded Clock (EC) I/O (a):Testing Embedded Clock (EC) I/O (a): Tx Tx
Tx needs to be tested with a compliance clock recovery defining a jittertransfer function (JTF)
Eye-diagram, jitter PDF, BER CDF manifests JNB test
TJ is the eye-closure at a BER level (e.g ., 10
-12
)
+
_
CR/PLL
UI-TJBERCDF
ZeroLevel
JitterPDF
10-1 2
Data Input
Eye-diagram,Jitter PDF,
BER CDF, andMeasurementSystem
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
21/44
EE14121
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 21
Testing Embedded Clock (EC) I/O (a):Testing Embedded Clock (EC) I/O (a): Tx Tx (Cont (Cont ’ ’ d)d)
≤10-12 BER zone
Jitter PDFs
JNB within the context of an eye-diagram (2-dimensional)
TJ and TN defines the compliance zone
No data sample should fall within the compliance zone (e.g ., BER
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
22/44
EE14122
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 22
Testing Embedded Clock (EC) I/O (b): ChannelTesting Embedded Clock (EC) I/O (b): Channel
Lossy channel is a low-pass filter
Digital square input waveform becomes slow edge round waveforms due to
the loss of high-frequency contents Data-dependent jitter (DDJ) and Data-dependent noise (DDN) manifest lossy
and intersymbol interference effects
Tx RxChannel
f
M a g
fbw
|Hch(s)|
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
23/44
EE14123
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 23
Testing Embedded Clock (EC) I/O (b): Channel (Cont Testing Embedded Clock (EC) I/O (b): Channel (Cont ’ ’ d)d)
Channel compliance test may be done in terms of S-parameter S21 An compliance |S21| curve sets the upper limit for the test
This method suffers from phase coverage skipping
Compliance |S21| curve
Passing Channel
Failing channel
f
S 2 1 M a g
( d B )
0
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
24/44
EE14124
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 24
Testing Embedded Clock (EC) I/O (c): RxTesting Embedded Clock (EC) I/O (c): Rx
Rx clock recovery (CR) jitter tolerance/tracking test
The compliance jitter tolerance mask is derived from Rx CR JTF
The mask sets the lower limit for pass/fail test
Be able to tolerant/track more lower frequency jitter is a key requirement for
Rx CR
Frequency (f)f c
M a g
n i t u d e
( d B )
Jitter tolerance
threshold
Pass
Fail
10-12 BER
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
25/44
EE14125System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 25
Testing Embedded Clock (EC) I/O (c): Rx (Cont Testing Embedded Clock (EC) I/O (c): Rx (Cont ’ ’ d)d)
Worst case signaling is a Rx subsystem test
It covers Rx clock recovery, equalization, sensitivity, and internal jitter and
noise generation
Both focused and subsystem test are important, depending on the test goals
and needs
Rx
Worst case eye
Worst case
eye opening
Ideal
eye
Jitter,
noise
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
26/44
EE14126System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 26
Testing Embedded Clock (EC) I/O (c): Rx (Cont Testing Embedded Clock (EC) I/O (c): Rx (Cont ’ ’ d)d)
A generic Rx test functional block diagram
Capable of providing both focused, worst case signaling, and full coverage
Rx tolerance/stress test Be able to emulate all jitter components and signal signatures with
controllability for magnitude and frequency band are critical
Rx
DCD
RJ
BER
Measure
BUJ
PJ/SSC
Ref Channel /DDJ
DUT
Pat Gen
With
AM/PM
/FM
Mod
DN
RN
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
27/44
EE14127System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 27
Testing Embedded Clock (EC) I/O (d): Ref ClockTesting Embedded Clock (EC) I/O (d): Ref Clock
Period or cycle-to-cycle jitter are not suitable metrics for reference clock inthe common clock architecture
Phase jitter after the reference clock JTF is called for Reference clock JTF is a band-pass filter function
Reference clock JTF is determined by Tx PLL, Rx PLL, and transport delaybetween them
0 dB
f1: f 2
Frequency
M a g n
i t u d e ( d B )
Peaking
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
28/44
EE14128System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 28
Testing Embedded Clock (EC) I/O (d): Ref Clock (Cont Testing Embedded Clock (EC) I/O (d): Ref Clock (Cont ’ ’ d)d)
Phase jitter spectrum before and after the ref clock JTF is applied
Phase jitter spectrum after JTF is what the Rx sees and related to Rx BER Spread spectrum clock (SSC) at ~ 33 KHz is significantly suppressed by the
ref clock JTF
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
29/44
EE14129System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 29
SystemSystem- - Level BER EstimationLevel BER Estimation
BER can be estimated given the Rx input jitter spectrum and CR JTF
CR phase delay can cause the Rx BER to increase (e.g ., region 2)
This method enables fast/high-through BER testing in production
R1 R2 R3 R4
Number of Samples
J i t t e r
( s e c o n d s )
J i t t e r ( s e c o n d s )
Number of Samples
Region 2
Jittercharacteristics
Region 3
Jittercharacteristics
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
30/44
EE141
30
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 30
Tester Apparatus ConsiderationsTester Apparatus Considerations
Front-end bandwidth (BW) needs to be high enough (e.g ., 5th harmonic, 2.5X
the data rate)
DJ and RJ floor needs to be small enough to avoid margin loss due to thetester jitter floor (~ps for DJ, and ~ sub-ps RJ at ~ 10 Gbps data rate)
Clock recovery emulation is critical for Tx testing
Tolerance and stressing is critical for Rx testing
Model-assisted method (e.g ., Tailfit jitter and BER extrapolation method)
speeds-up the throughput of the tester
Tetser Accuracy Requirements
0
5
10
0 5 10 15
Dat Rate (Gb/s)
T
i m i n g
A c c u r a c y ( p s )
RJ rms DJ pk-pk
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
31/44
EE141
31
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 31
III. DFTIII. DFT--Assisted TestAssisted Test
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
32/44
EE141
32
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 32
AC I/O AC I/O Loopback Loopback Self Self - - TestTest
driver
latch
Dx
Strobe
Bus Clock
board trace delay
wire delay
wire delay
board trace delay
system clock
clock domain 1 clock domain 2data
strobes
receiver
latch
Similar circuit as the receiving end!Testing hardware already exists!
-- test for both drive/receive-- low overhead
Loop time = Tco (or Tvb) + Tsetup OR Tva+Thold
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
33/44
EE141
33
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 33
Strobedelay
stress to fail by
pushing
strobes to the data
edge
(driver or receiver)
buffer group
should have tight
distribution
bus group
faulty buffer
good buffers distribution
wider distribution => local
defective buffers
AC I/O AC I/O Loopback Loopback Test Based DefectsTest Based Defects
A wider
spread ofdata validtime indicatefaults
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
34/44
EE141
34
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 34
AC I/O AC I/O Loopback Loopback Test Resources and MechanismsTest Resources and Mechanisms
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
35/44
EE141
35
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 35
HighHigh- - Speed Serial Speed Serial - - LinkLink Loopback Loopback Testing (a): anTesting (a): an
Under Under - - Sampling MethodSampling Method
Use a reference clock close to the data frequency to strobe the data rather
than the recovered clock Jitter due to the channel carried in the received data bit timing
Hi h S d S i l Li k L b k T ti (b) T t
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
36/44
EE141
36
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 36
HighHigh- - Speed Serial Speed Serial - - LinkLink Loopback Loopback Testing (b): TestTesting (b): Test
SetupSetup
Use the SERDES resources
Pattern generation and data comparison/jitter analysis at the receiver can beeither on-chip or off-chip
Hi hHi h S d S i lS d S i l Li kLi k L b kL b k T ti ( ) T tT ti ( ) T t
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
37/44
EE141
37
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 37
HighHigh- - Speed Serial Speed Serial - - LinkLink Loopback Loopback Testing (c): TestTesting (c): Test
EqualizersEqualizers
DFT resources needed: digital pattern generator, 3 full-swing digital taps forcrosstalk canceller, and one shift-register chain
No access of DFE output for testing DFE
Suited for production test
Slicer
DFE
CDR X T a l k
C a n c e l l e r
FFE
Data
DataTX
RX
Pattern
Generator
M U X
RxP
RxN
ClockPattern
Verification
TxN
TxP
P
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
38/44
EE141
38
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 38
IV. SystemIV. System--Level Interconnect TestingLevel Interconnect Testing
I t t T ti ith B d S
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
39/44
EE141
39
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 39
Interconnect Testing with Boundary ScanInterconnect Testing with Boundary Scan
IEEE 1149.1 boundary-scan standard developed for testing board-levelmanufacture defects
Chip 1
TAP
TCK
TMS
TDI
TDO
Chip 2
I t t T ti ith Hi hI t t T ti ith Hi h S d B d SS d B d S
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
40/44
EE141
40
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 40
Interconnect Testing with HighInterconnect Testing with High- - Speed Boundary ScanSpeed Boundary Scan
IEEE 1149.1 boundary-scan standard has been extendedto IEEE 1149.6 for high-speed boundary-scan test.
IEEE 1149.6 supports AC-coupled differential signaling.
Digital driver logic and digital receiver logic along with theanalog test receiver are added to support the high-speeddifferential signaling, under the control of the 1149.1 TAP
controller. More information about 1149.6 can be found in Chapter 1.
However, its reliability for testing Gbps I/O interfaces
remains to be a problem for IEEE 1149.6.
I t t B iltI t t B ilt I S lfI S lf T tT t
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
41/44
EE141
41
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 41
Interconnect Built Interconnect Built - - In Self In Self - - Test Test
Built-in reference and programmable Tx and Rx
Use the reference Tx to test Rx DUT, or use the reference Rx to test Tx DUT Various pattern generation support is a key for system-level test
To core
Component B
TX
RX
From core
Pattern
Generator
Error
Control
To core
Component A
TX
RX
From core
Pattern
Generator
Error
Control
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
42/44
EE141
42
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 42
V. Future ChallengesV. Future Challenges
F t Ch llFuture Challenges
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
43/44
EE141
43
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 43
Future ChallengesFuture Challenges
Data rate keeps increasing
Link jitter margin gets smaller, device components and tester have to be
more accurate
Eye-will be closed at the Rx input, reference Tx and Rx will be mandatory for
testing Advanced signaling/equalizations (Tx, Rx, continuous, discrete, linear,
adaptive)
More complex link system, Tx and Rx subsystems means more complex test
requirements
Femto second (fs) accuracy is coming for 10 Gbps and higher
Test solution should be optimized for accuracy, throughput, parallelism, faultcoverage, and cost requirements (somewhat conflicting), for both on-chipDFT/BIST and off-chip ATE/instruments
More analog DFT/BIST, adaptive design and test with low power Insuring JNB test quality from design characterization to high-volume
production with high-confidence and low cost
Concluding RemarksConcluding Remarks
-
8/19/2019 Chapter 14 High Speed IO Slides 121107
44/44
EE141
44
System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 44
Concluding RemarksConcluding Remarks Three leading I/O architectures:
• Global clock (GC), source synchronous (SS), and embedded
Link architecture determines the relevant test parameters and methods.Key parameters include:
• Data valid to clock/strobe, setup/hold times for GC and SS; jitter, noise, and
BER (JNB) for embedded• Clock recovery and equalization must be included in test
DFE-assisted test methods:• Largely rely on loopback: AC loopback, under-sampling loopback, and
equalizer testing
System-level test methods:• Boundary scan for testing manufacturing defects
• BIST for testing Tx and Rx, and link system
Future challenges:
• Higher data rate, smaller jitter margin, higher channel counter, better
accuracy• More complex test requirements and platform, more DFT/BIST to address
cost and avoid tester-DUT interface bandwidth bottleneck