Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-1
Chapter 4. Basics of Device Fabrication
Schematic cross section of n-MOSFET
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-2
Wafer Cleaning
11 22 33 44 55
1 Organics 2 Oxides 3 Particles 4 Metals 5 Dry
H2SO4 + HF + NH4OH + HCl + H2O or IPA +
H2O2 H2O H2O2 + H2O H2O2 + H2O N2
H2O Rinse H2O Rinse H2O Rinse H2O Rinse
Wet station Spin dryer
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-3
Thermal Oxidation A process to form a thermal SiO2 thin film
Si (s) + O2 (g) → SiO2 (s)
Si (s) + 2H2O(g) → SiO2 (s) + 2H2(g)
Dry oxidation: slow but dense film
Wet oxidation: fast but less dense film
900 ~ 1200 oC, 1atm
900 ~ 1200 oC, 1atm
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-4
Chemical Vapor Deposition Vacuum deposition of thin film (SiO2, Si3N4, poly-Si, etc)
SiH4 (g) + O2(g) → SiO2 (s) + 2H2(g) ~ 450 oC
SiO2 film:
3SiCl2H2 (g) + 4NH3(g) → Si3N4 (s) + 6HCl (g) + 6H2(g) ~ 750 oC
Si3N4 film:
SiH4 → Si(s) + 2H2(g) ~ 600 oC
Poly-Si film:
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-5
Physical Vapor Deposition Metallization for interconnection (Aluminum)
Thermal evaporation
E-beam
evaporation
Sputtering
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-6
Chemical-Mechanical Polishing (CMP) A process for planarization due to the multilevel interconnection
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-7
Photolithography A process to make a pattern of a film
• Critical dimension (CD):
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-8
Step Operation Process
1 PR coating Apply PR on a substrate by spin coating
2 Soft baking Low temperature cure to dry resist
3 Exposure Align and expose to selectively polymerize the PR
4 Development Dissolve the un-polymerized PR
5 Inspection Verify accurate image transfer to PR
6 Post-exposure
baking
Higher temperature cure to completely dry and polymerize
the PR. (also called “hard baking”)
7 Etching Form a patterned film
8 PR strip Remove the PR pattern
9 Inspection Verify accurate image transfer to the film
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-9
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-10
Positive PR
• Positive resists decomposes by being exposed by UV light.
• Exposure to the UV light changes the chemical structure of the resist
so that it becomes more soluble in the developer.
• The unexposed region will be polymerized by soft and hard baking.
Negative PR
• Exposure to the UV light causes the negative resist to become
polymerized, and more difficult to dissolve.
• Therefore, the negative resist remains on the surface wherever it is
exposed, and the developer solution removes only the unexposed
portions.
• Masks used for negative photoresists, therefore, contain the inverse
(or photographic "negative") of the pattern to be transferred.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-11
Etching
• Etching is the process where unwanted areas of films are
removed by either dissolving them in a wet chemical
solution (Wet Etching) or by reacting them with gases in
a plasma to form volatile products (Dry Etching).
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-12
Wet Etching
• For SiO2 etching
- HF + NH4F+H20 (buffered oxide etch or BOE)
• For Si3N4
- Hot phosphoric acid: H3PO4 at 180 °C
- need to use oxide hard mask
• Silicon
- Nitric, HF, acetic acids
- HNO3 + HF + CH3COOH + H2O
• Aluminum
- Acetic, nitric, phosphoric acids at 35-45 °C
- CH3COOH+HNO3+H3PO4
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-13
Dry Etching
• SiO2 : CF4/CHF3/Ar
• Si3N4 : CHF3/O2
• Silicon : HBr/NF3/O2/SF6
• Aluminum : BCl3/Cl2
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-14
Impurity Doping A process to introduce a controlled amount of impurity atoms to Si
Diffusion
Implantation
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-15
Electrical Test
Defective IC
Individual integrated circuits
are tested to distinguish good
die from bad ones.
n-well
p-channel transistor
p-well
n-channel transistor p+ substrate
bonding pad nitride
Metal 2
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-16
Die Cut and Assembly
Good chips are attached
to a lead frame package.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-17
Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-18
Final Test
Chips are electrically
tested under varying
environmental conditions.
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-19
Moore’s Law
• Moore's law is the
observation that
the number of
transistors on IC
doubles
approximately
every two years.
• The law is named
after Intel co-
founder Gordon E.
Moore, who
described the trend
in his 1965 paper
Prof. Yo-Sep Min Electronic Materials: Semiconductor Physics & Devices Chapt. 4 - Lec 23-20
Announcements
• Final EXAM: Dec. 15, 13:00 ~ 15:00, 별 232
Everything studied after the Mid-Term EXM
• Homework problem set (due to Dec. 15):
18. 2; 18.6; 18.15