CMOS RFIC Design for Direct Conversion
ReceiversZhaofeng ZHANG
Outline of Presentation
• Background Introduction• Design Issues and Solutions• A Direct Conversion Pager Receiver • Conclusion
Research Goal• Low Cost
– Process: CMOS• Device is good enough• Improved passive components
– Integration level• Minimize external components• Minimize IC area and pin numbers
• Low Power– High integration = low power– Low power individual block design– System architecture is important
Heterodyne Receivers• High IF: more than 2 down-conversions
– Best sensitivity– Need off-chip image-rejection SAW filters and
channel-selection filters– Highest cost, high power, low integration
• Low IF– Relaxed image-rejection requirement compared to
high-IF– No DC offset problem– Quadrature LO is required– Flicker noise may be a problem– High integration level, low cost
Homodyne Receivers
Simple architecture No image problem No 50ohm interfaces High integration level Lowest cost, low power
DC offsets Flicker noise LO leakage Even-order distortion
ProsCons
90º
I
Q
LNA
Origin of Problem DC offsets Flicker noise LO leakage Even-order distortion Linearity requirement Noise requirement IQ mismatch
The mixer: the most critical component!All problems are limited by the mixer design!
Our research focus!
DC Offsets & LO Leakage
+ Offset
• The offset originates from self-mixing.• It can be as large as mV range at the mixer output.• It varies with the environment and moving speed of the mobile and changes with time. • The maximum bandwidth can be as large as kHz range.• LO leakage forms an interference to other receivers.
LO Leakage
Zero IF
Po w
e r
Narrow Band Broad Band
Frequency
Pow
er
Frequency
Pow
er
Frequency
Pow
er
Frequency
Signal
DC O
ffset
sOff
set-F
ree
DC offset
Spectrum Illustration
Flicker noise
High-pass corner
Existing Solutions on DC Offset
• AC coupling or high pass filtering• Autozeroing or double sampling• Offset cancellation in digital domain• Double LO frequency method [ISSCC99]• Adaptive dual-loop algorithm combined with the mixer
[RAWCON00]• Pulse-width-modulation based bipolar harmonic mixer [CICC97]
However, these methods are either not so effective or too complicated, or not suitable
for CMOS process.
Proposed Harmonic Mixing
Conv
entio
nal
Our W
ork
flo=frf
RF Signal
frf
BB Signal
0
2flo=frf
RF Signal
frf
BB Signal
0
LO Leakage DC Offset
LO Leakage
flo=frf/2 flo
Square-law Based Mixer
• LO leakage free.• Ideally self-mixing free.• Current controlled switching.• No noise contribution from LO stage.
LO
2
RF IFCurrent
Voltage
Voltage
CouplingNo
Vlo+ Vlo-
Vrf+ Vrf-
3V
Flicker Noise Reduction
• Flicker noise is proportional to the current.• Current injection is used to reduce flicker noise.• No noise contribution from current source too.
Vrf+I0
Vlo+ Vlo-
Vrf-
3V
Offset Cancellation20
10
0-10
-20
-30
-40 -22 -20 -18 -16LO Input Power (dBm)
Gai
n (d
B) >35dB
TSMC0.35
Noise Performance60
50
40
30
20400 600 800 1000
Injected Current I0 (A)
Noi
se F
igur
e @
10k
Hz
(dB
)
How to improve more?• However, flicker noise is still too large due to CMOS
devices, minimum noise figure achieved is larger than 24dB @ 10kHz for CMOS harmonic mixer. It requires a high gain and low noise LNA to overcome flicker noise while the front-end linearity suffers.
• For a narrow-band communication system such as FLEX pager, the noise requirement at low frequency is very tough.
• It is well known that bipolar device is a good candidate to eliminate flicker noise.
• But, can we do it in a CMOS process and how good is the device? YES!
Lateral Bipolar Transistor in a Bulk CMOS Process
W.T. Holman95
Gate
Emitter
Collector
Base
Ground
P+ N+
Emitter
Vertical
Collector
Collector
Lateral
Base
Gate
Physical Model of LBJT
D. Mac98
P-Sub
Gate
EmitterCollector
Base Base
P-Sub
M1Q1
Q2Q3
Pure LBJT: M1, Q3 off, Q1, Q2 on.
Gummel Plot of LBJTTSMC0.35
>40 at mAs
max fT 4GHz
LBJT Harmonic Mixer
RLRLOUT- OUT+
VRF+ VRF-Ii
VLO-VLO+ M1 M2
VDD
Q1 Q2
Noise Performance
Large LO improves noise.
Even Order DistortionRF Signal
frf
BB Signal
0
Interference IM2 (f2-f1)
• It is mainly introduced by layout asymmetry and device mismatch.• Since direct-conversion, the intermodulation components IM2 will fall into the demodulated signal spectrum.• Therefore, good IIP2 is required for homodyne receivers.• It is found that varying the loading resister or voltage bias can compensate the device mismatch and improve IIP2 significantly.
a1x+a2x2+a3x3+…
f1 f2
IIP2 Improvement
IIP2=18dBm IIP2>40dBmSame DC bias Compensation
LBJT Mixer PerformanceTechnology TSMC 3M2P 0.35mVDD 3VSignal Gain +15dBDC offset suppression >30dBNoise figure @ 10kHz <18dB1dB compression point >-20dBmInput-referred IP3 >-9dBmInput-referred IP2 >+40dBmPower consumption <2.2mW
Summary on Mixer• Flicker noise free, corner frequency is
below 10kHz.• DC offset free, more than 30dB DC offset
suppression is achieved.• No LO leakage problem.• Sufficient IIP2 after bias compensation.• High gain and low power consumption.• Complete CMOS process.• Suitable for CMOS direct conversion
applications.
Difficulties in FLEX PagerFLEX 6400, 4FSK
0
-20
-40
-60
dB
1050-5-10kHz
• Narrow band modulation• Significant energy near DC• High pass filtering is not viable• DC offset problem• Flicker noise is significant
10 -1
10 -2
10 0
BE
R
Eb/N0 (dB)4 8 12 16
DC O
ffset
Effe
ctHi
gh p
ass e
ffect
High pass corner (Hz)
BE
R @
12d
B E
b/N
0
-210
-1
Big Challenges
4-FSK Pager Receiver
• Fully differential architecture to reject substrate noise.• Harmonic mixers are used to solve time-varying DC offset.• Peak detectors are used to cancel static DC offset.• High front-end gain and current injection to reduce flicker noise.
45
AGC
AGC
LNA DEMODVCO
RF: Zhaofeng
BB: Zhiheng
LNA• Non-quasi-static
phenomenon makes it unnecessary to do on-chip matching.
• Off-chip matching by a single inductor and a balun.
• |S11|<-20dB @ 930MHz
• Both on-chip and off-chip inductive loads were tried.
Double Balanced Mixer
Improve the linearity; Provide constant impedance to LNA;Current injection provides more than 20dB flicker noise reduction.
Ring Oscillator
Half RF frequency,
Provide 45 phase.
Static DC Offset Cancellation
Peak Detector Fmin200Hz
Zero-IF 4-FSKSignal
Performance SummaryPager receiver with off-chip ind
Maximum Gain: 62dB
Noise figure@10kHz: 14.5dB
Overall DC offset at LPF output: <1mV
(Signal: 400mV)
Power dissipation: 58mW
Technology: TSMC0.35m 4M2P
Die area: 4.6 mm2
Front-End Off-chip ind On-chip ind
RF/BB gain: 51.13dB 40.33dB
NF@10kHz: 11.5dB 24.0dB
NF@100kHz: 5.8dB 15.0dB
IIP3: -26dBm -20.7dBm
IIP2: -10dBm -5.6dBm
Operating frequency: 930.1MHz
LO frequency: 465MHz
IQ gain mismatch: < 0.3dB
IQ phase mismatch: < 5
RF/BB over LO/BB: > 54dB
Self-mixing free
Input matching: < -20dB
Power dissipation: 52.76mW
Baseband (Zhiheng)AGC gain: -14.5dB~18.6dB
LPF: Pass-band gain-6.2dB, ripple .5dB (9kHz)
Stop-band attenuation 63dB ( 17.8kHz)
Offset cancellation: <2mV (under ±100mV input offset)
Input Referred Noise: 600nV/ @ 10kHz
Clock Recovery: Capture range > 550Hz
Power dissipation: 5.4mW (including all testing buffers)
Hz
Die Photo
DEM
OD
LPF
AG
C
Mixer
OSC
LNA
LNA
OSC
Mixer
Base Band Circuitry[Zhiheng]
RF Front-End
RF Front-End
45
AGC
AGC
LNA DEMODVCO
Summary on Pager Receiver
• Feasibility of direct conversion has been demonstrated.
• Proposed harmonic mixing technique solves self-mixing induced DC offset problem successfully.
• With the help of static DC offset cancellation, the total DC offset is less than 1mV at the receiver output.
• The modified ZIFZCD 4-FSK demodulator functions correctly.
• A 4-FSK FLEX pager receiver in a single chip has been implemented successfully.
Conclusion• Circuit design for direct-conversion has been
discussed.– DC offset: more than 30dB improvement– LO leakage: no longer a problem– Flicker noise: corner frequency is less than kHz
due to lateral bipolar device.– IIP2: larger than +40dBm after bias compensation.
• System on chip has been successfully demonstrated using CMOS direct conversion architecture.