Download - CMOS VLSI Design MIPS Processor Example
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CMOS VLSIDesign
MIPS Processor Example
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Slide 2CMOS VLSI Design
Outline Design Partitioning MIPS Processor Example
– Architecture– Microarchitecture– Logic Design– Circuit Design– Physical Design
Fabrication, Packaging, Testing
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Slide 3CMOS VLSI Design
Review Sketch a stick diagram for a 4-input NOR gate
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Slide 4CMOS VLSI Design
Review Sketch a stick diagram for a 4-input NOR gate
AVDD
GND
B C
Y
D
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Slide 5CMOS VLSI Design
Coping with Complexity How to design System-on-Chip?
– Many millions (soon billions!) of transistors– Tens to hundreds of engineers
Structured Design Design Partitioning
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Slide 6CMOS VLSI Design
Structured Design Hierarchy: Divide and Conquer
– Recursively system into modules Regularity
– Reuse modules wherever possible– Ex: Standard cell library
Modularity: well-formed interfaces– Allows modules to be treated as black boxes
Locality– Physical and temporal
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Slide 7CMOS VLSI Design
Design Partitioning Architecture: User’s perspective, what does it do?
– Instruction set, registers– MIPS, x86, Alpha, PIC, ARM, …
Microarchitecture– Single cycle, multi-cycle, pipelined, superscalar?
Logic: how are functional blocks constructed– Ripple carry, carry lookahead, carry select adders
Circuit: how are transistors used– Complementary CMOS, pass transistors, domino
Physical: chip layout– Datapaths, memories, random logic
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Slide 8CMOS VLSI Design
Gajski Y-Chart
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Slide 9CMOS VLSI Design
MIPS Architecture Example: subset of MIPS processor architecture
– Drawn from Patterson & Hennessy’s textbook MIPS is a 32-bit architecture with 32 registers
– Consider 8-bit subset using 8-bit datapath– Only implement 8 registers ($0 - $7)– $0 hardwired to 00000000– 8-bit program counter– Illustrate the key concepts in VLSI design
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Slide 10CMOS VLSI Design
MIPS Microarchitecture Multicycle architecture from Patterson & Hennessy
PCMux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction[15: 11]
Mux
0
1
Mux
0
1
1
Instruction[7: 0]
Instruction[25 : 21]
Instruction[20 : 16]
Instruction[15 : 0]
Instructionregister
ALUcontrol
ALUresult
ALUZero
Memorydata
register
A
B
IorD
MemRead
MemWrite
MemtoReg
PCWriteCond
PCWrite
IRWrite[3:0]
ALUOp
ALUSrcB
ALUSrcA
RegDst
PCSource
RegWrite
Control
Outputs
Op[5 : 0]
Instruction[31:26]
Instruction [5 : 0]
Mux
0
2
JumpaddressInstruction [5 : 0] 6 8
Shiftleft 2
1
1 Mux
0
32
Mux
0
1ALUOut
Memory
MemData
Writedata
Address
PCEn
ALUControl
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Slide 11CMOS VLSI Design
Multicycle Controller
PCWritePCSource = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond
PCSource = 01
ALUSrcA =1ALUSrcB = 00ALUOp= 10
RegDst = 1RegWrite
MemtoReg = 0MemWriteIorD = 1
MemReadIorD = 1
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst= 0RegWrite
MemtoReg=1
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
MemReadALUSrcA = 0
IorD = 0IRWrite3
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
Instruction fetch
Instruction decode/register fetch
Jumpcompletion
BranchcompletionExecution
Memory addresscomputation
Memoryaccess
Memoryaccess R-type completion
Write-back step
(Op = 'LB ') or (Op = 'SB ') (Op = R-type)
(Op
= 'BEQ')
(Op
='J
')
(Op = 'SB')
(Op
='L
B')
7
0
4
121195
1086
Reset
MemReadALUSrcA = 0
IorD = 0IRWrite2
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
1MemRead
ALUSrcA = 0IorD = 0IRWrite1
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
2MemRead
ALUSrcA = 0IorD = 0IRWrite0
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
3
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Slide 12CMOS VLSI Design
Logic Design Start at top level
– Hierarchically decompose MIPS into units Top-level interface
reset
ph1
ph2
crystaloscillator
2-phaseclockgenerator MIPS
processor adr
writedata
memdata
externalmemory
memreadmemwrite
8
8
8
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Slide 13CMOS VLSI Design
Block Diagram
datapath
controlleralucontrol
ph1
ph2
reset
memdata[7:0]
writedata[7:0]
adr[7:0]
memread
memwrite
op[5:0]
zero
pcen
regwrite
irwrite[3:0]
mem
toreg
iord
pcsource[1:0]
alusrcb[1:0]
alusrca
aluop[1:0]
regdst
funct[5:0]
alucontrol[2:0]
PCMux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction[15: 11]
Mux
0
1
Mux
0
1
1
Instruction[7 : 0]
Instruction[25 : 21]
Instruction[20 : 16]
Instruction[15: 0]
Instructionregister
ALUcontrol
ALUresult
ALUZero
Memorydata
register
A
B
IorD
MemRead
MemWrite
MemtoReg
PCWriteCond
PCWrite
IRWrite[3:0]
ALUOp
ALUSrcB
ALUSrcA
RegDst
PCSource
RegWrite
Control
Outputs
Op[5 : 0]
Instruction[31:26]
Instruction [5: 0]
Mux
0
2
JumpaddressInstruction [5 : 0] 6 8
Shiftleft 2
1
1 Mux
0
32
Mux
0
1ALUOut
Memory
MemData
Writedata
Address
PCEn
ALUContro l
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Slide 14CMOS VLSI Design
Hierarchical Designmips
controller alucontrol datapath
standardcell library
bitslice zipper
alu
and2
flopinv4x
mux2
mux4
ramslice
fulladder
nand2nor2
or2
inv
tri
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Slide 15CMOS VLSI Design
HDLs Hardware Description Languages
– Widely used in logic design– Verilog and VHDL
Describe hardware using code– Document logic functions– Simulate logic before building– Synthesize code into gates and layout
• Requires a library of standard cells
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Slide 16CMOS VLSI Design
Verilog Examplemodule fulladder(input a, b, c, output s, cout); sum s1(a, b, c, s);carry c1(a, b, c, cout);endmodule module carry(input a, b, c, output cout) assign cout = (a&b) | (a&c) | (b&c);endmodule
a b
c
s
cout carrysum
s
a b c
cout
fulladder
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Slide 17CMOS VLSI Design
Circuit Design How should logic be implemented?
– NANDs and NORs vs. ANDs and ORs?– Fan-in and fan-out?– How wide should transistors be?
These choices affect speed, area, power Logic synthesis makes these choices for you
– Good enough for many applications– Hand-crafted circuits are still better
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Slide 18CMOS VLSI Design
Example: Carry Logic assign cout = (a&b) | (a&c) | (b&c);
Transistors? Gate Delays?
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Slide 19CMOS VLSI Design
Example: Carry Logic assign cout = (a&b) | (a&c) | (b&c);
ab
ac
bc
cout
x
y
z
g1
g2
g3
g4
Transistors? Gate Delays?
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Slide 20CMOS VLSI Design
Gate-level Netlistmodule carry(input a, b, c, output cout)
wire x, y, z;
and g1(x, a, b);and g2(y, a, c);and g3(z, b, c);or g4(cout, x, y, z);
endmodule
ab
ac
bc
cout
x
y
z
g1
g2
g3
g4
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Slide 21CMOS VLSI Design
SPICE Netlist.SUBCKT CARRY A B C COUT VDD GNDMN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5PMN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5PMN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5PMN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5PMN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15PMP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 PMP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1PMP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1PMP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1PMP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3PMN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1PMP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2PCI1 I1 GND 2FFCI3 I3 GND 3FFCA A GND 4FFCB B GND 4FFCC C GND 2FFCCN CN GND 4FFCCOUT COUT GND 2FF.ENDS
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Slide 22CMOS VLSI Design
Physical Design Floorplan Standard cells
– Place & route Datapaths
– Slice planning Area estimation
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Slide 23CMOS VLSI Design
MIPS Floorplan
datapath2700 x 1050
(2.8 M2)
alucontrol200 x 100
(20 k2)
zipper 2700 x 250
2700
1690
wiring channel: 30 tracks = 240
mips(4.6 M2)
bitslice 2700 x 100
control1500 x 400
(0.6 M2)
3500
3500
5000
5000
10 I/O pads
10 I/O pads
10 I/O pads
10 I/O pads
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Slide 24CMOS VLSI Design
MIPS Layout
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Slide 25CMOS VLSI Design
Standard Cells Uniform cell height Uniform well height M1 VDD and GND rails M2 Access to I/Os Well / substrate taps Exploits regularity
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Slide 26CMOS VLSI Design
Synthesized Controller Synthesize HDL into gate-level netlist Place & Route using standard cell library
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Slide 27CMOS VLSI Design
Pitch Matching Synthesized controller area is mostly wires
– Design is smaller if wires run through/over cells– Smaller = faster, lower power as well!
Design snap-together cells for datapaths and arrays– Plan wires into cells– Connect by abutment
• Exploits locality• Takes lots of effort
A A A A
A A A A
A A A A
A A A A
B
B
B
B
C C Dsnap-together cells require more design and layout effort for small area and shorter wires,
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Slide 28CMOS VLSI Design
MIPS Datapath 8-bit datapath built from 8 bitslices (regularity) Zipper at top drives control signals to datapath
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Slide 29CMOS VLSI Design
MIPS ALU Arithmetic / Logic Unit is part of bitslice
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Slide 30CMOS VLSI Design
Design Verification Fabrication is slow & expensive
– MOSIS 0.6m: $1000, 3 months– State of art: $1M, 1 month
Debugging chips is very hard– Limited visibility into operation
Prove design is right before building!– Logic simulation– Ckt. simulation / formal verification– Layout vs. schematic comparison– Design & electrical rule checks
Verification is > 50% of effort on most chips!
Specification
ArchitectureDesign
LogicDesign
CircuitDesign
PhysicalDesign
=
=
=
=
Function
Function
Function
FunctionTimingPower
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Slide 31CMOS VLSI Design
Fabrication & Packaging Tapeout final layout Fabrication
– 6, 8, 12” wafers– Optimized for throughput, not latency (10 weeks!)– Processed wafers are sliced into dice (chips) and
packaged. Packaging
– Bond gold wires from die I/O pads to package
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Slide 32CMOS VLSI Design
Testing Test that chip operates
– Design errors– Manufacturing errors
A single dust particle or wafer defect kills a die– Yields from 90% to < 10%– Depends on die size, maturity of process– Test each part before shipping to customer