Coarse and Fine Grain Programmable Overlay Architectures for FPGAsAlex Brant
Advisor: Guy Lemieux
University of British Columbia
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Motivation - 1FPGA Overlays
FPGA designs that can be further programmed by the userWhat are the benefits?
Ease of use (simpler languages, tools, etc.)Optimized for particular problem domainsOpen access to architecture & CADUser-configured logic added to fixed FPGA bitstreamDynamic reconfiguration on any devicePortability between vendors and devices
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Motivation - 2Fine Grain Overlay – ZUMAFPGA-like architecture
Compatible with VTR CAD tools“Virtual” FPGA for portability of designsOpen source for research and applications
Implements fine grain part of MALIBU architectureGeneric implementation has high area overhead
Overcome by utilizing low level FPGA resources, implementing more efficient structures
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Motivation - 3Coarse Grain Overlay – CARBONArray of time-multiplexed ALUs
Fast compileHigh densityEfficient mapping of word oriented circuits
Implements coarse grain part of MALIBUTime-multiplexing limits overall performance
Performance gained using overclocking with error tolerance (CARBON-Razor)
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Contributions
Area efficient implementation of fine grain routing and logic with LUTRAMs
Area efficient 2-stage local routing network and configuration controller
Extension of Razor error tolerance from pipelined processors to 2D processing arrays
Design of an overclockable coarse grain FPGA overlay with in-circuit error correction
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Publications
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ZUMA: An Open FPGA Overlay Architecture, Alexander Brant and Guy G.F. Lemieux (FCCM 2012)
Pipeline Frequency Boosting: Hiding Dual-Ported Block RAM Latency using Intentional Clock Skew, Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G.F. Lemieux (FPT 2012)
CARBON-Razor: An Error-Tolerant Coarse Grain FPGA (in preparation)
MALIBU Architecture
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Hybrid coarse/fine grain FPGA Time-multiplexed ALU (CG) combined with FPGA cluster CG passes data to neighbors through memories
MALIBU Hybrid FPGA CGs are run on fast system clock (e.g. > 1GHz) System clock / Schedule length = User clock rate Advantages:
Greater density from time-multiplexing Ability to trade-off between area and speed Compiles up to 300x faster than normal FPGA Better performance for word-oriented circuits
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Razor Timing Error Tolerance
Works with feed-forward pipeline circuits Detects timing errors by capturing data a second time
with a delayed clock Tolerates errors by stalling pipeline one cycle
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Razor Timing Error Example
Data captured in main FF Fraction of cycle later, data captured by shadow latch
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Razor Timing Error Example
Data captured in main FF Fraction of cycle later, data captured by shadow latch Main FF and Shadow latch are compared
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Razor Timing Error Example
Data captured in main FF Fraction of cycle later, data captured by shadow latch Main FF and Shadow latch are compared
If different, shadow data loaded to main FF, pipeline is stalled
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Razor Timing Error Example
Data captured in main FF Fraction of cycle later, data captured by shadow latch Main FF and Shadow latch are compared
If different, shadow data loaded to main FF, pipeline is stalled If not, pipelining proceeds normally
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ZUMA Overlay
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Island style FPGA architecture, implemented on an FPGA
Initially implemented in generic Verilog High area overhead, 125+ host LUTs for each ZUMA
LUT (eLUT) Area efficiency improvements:
Implementation of routing and logic with FPGA LUTRAMs
Design of efficient 2-stage local interconnect
ZUMA Layout
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K-LUT FFTwo Stage
Crossbar Network
S-Block
Input Block
Logic Cluster
One tile of ZUMA Architecture
Details - LUTRAM
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we
data outConfig Bits
2k
Decoder
rd addr
wr addr
data in
k
kConfig Bits
2k
Reprogrammable LUTRAM in Xilinx and Altera Devices
Details – LUTRAM Multiplexer
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6-LUTs0
yy
s1
d1d2d3
d0d1d2d3
d0
d4d5
6-LUT, configured as a 4-to-1 MUX
6-LUT6-LUT, configured as a 6-to-1 MUX in RAM mode
LUTRAM can implement larger MUXs than a normal LUT, need no extra configuration memory
Details – Local Routing Crossbar
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K-LUTk
1 1
k
k
1 1
k
k
1 1
k
P
1 1
N
P
1 1
N
P
1 1
N
1
k
P k x kLUTRAMs
k P x NLUTRAMs
N k-input LUTs
K-LUT1
k
K-LUT1
k
P=(I+N)/k
I+NInputs
N*kOutputs
Reduced Two Stage Network ZUMAeLUTs
Two-Stage (I+N) x (k*N) crossbar used in ZUMA Logic Cluster
Results
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Both Xilinx and Altera versions implementedOur generic version is 125-150 LUTs per eLUTArea overhead as low as 40 Host LUTs per eLUT
with improvementsCompared to previous work (vFPGA) on 4-LUT
host, overhead reduced 3x with same parameters
CARBON Overlay FPGA implementation of MALIBU CG
Modifications to support FPGA block RAMs Critical Path is Memory to ALU to Memory
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CARBON-Razor
Razor is applied to the CARBON overlay Error tolerance on memory to memory critical path
How to do it: Shadow registers apply to CARBON memories CARBON schedule 1-3 extra timeslots for error
recovery Stall propagation extend from 1D pipeline (Razor)
to 2D array (CARBON)
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CARBON-Razor Memory
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Shadow register paired with RAM Stratix memory mode allows read-back of previously written
data
2D Error PropagationCan’t propagate errors to entire chip fast enough
We can propagate it one tile per cycleError propagation logic can then combine multiple
errors into one stall region
2D Error Propagation Example
Error at tile at cycle 0 Each cycle, stall
propagates to nearest neighbors
0
2D Error Propagation Example
0 1
1
1
1
Error at tile at cycle 0 Each cycle, stall
propagates to nearest neighbors
2D Error Propagation Example
2 2
2
0 1
2
1
1
1
2
2
Error at tile at cycle 0 Each cycle, stall
propagates to nearest neighbors
2D Error Propagation Example
3
3 2
3
2
3 2
0 1
2
1
1
1
2
2
Error at tile at cycle 0 Each cycle, stall
propagates to nearest neighbors
2D Error Propagation Example
4 3
3 2
3
2
3 2
0 1
2
1
1
1
2
2
Error at tile at cycle 0 Each cycle, stall
propagates to nearest neighbors
2D Error Propagation Example
4 3
3 2
3
2
3 2
0 1
2
1
1
1
2
2
Error at tile at cycle 0 Each cycle, stall
propagates to nearest neighbors
Stall Propagation Logic
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When an error is detected at a CG: Instruction schedule stalls Memories in CG load from shadow register Any writes from neighbor captured in shadow register
Next cycle: Schedule resumes Neighbor’s write performed from shadow register 4 neighbors stall, unless they stalled last cycle
Stall region continues in expanding diamond shaped wave
Carbon Schedule Extension We add 1-3 cycles of slack to schedule
Allows margin of safety Speedup determined by difference in FMAX and schedule
length If no hard deadline is needed (eg. when used as compute
accelerator), average extension of schedule can be used to find speedup
FMAX-Razor * SLBase
FMAX-Base * SLRazor
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Speedup =
Results
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Performance compared between CARBON and CARBON-Razor for 4 benchmarks
Maximum performance found by pushing clock speed and shadow register delay
Average increases to 14% with no hard deadline
Benchmark SL Extra Cycles Speedup
Random Ops 24 2 11%
Wang 28 1 6%
Mean(256) 67 2 20%
PR 29 1 3%
Average 13%
Contributions
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Area efficient implementation of FPGA routing and logic with LUTRAMs
Area efficient 2-stage local routing network and configuration controller
Extension of Razor error tolerance from pipelined processors to 2D processing arrays
Design of an overclockable coarse grain FPGA overlay with in-circuit error correction
SummaryFine Grain Overlay – ZUMAFPGA-like architecture, compatible with VTR CAD toolsHigh area overhead implementing fine grain structures
Overcome by utilizing FPGA resources, implementing alternate structuresArea reduced to 40 host LUTs per eLUT, 3x improvement
Coarse Grain Overlay – CARBONFast compile, efficient mapping of word oriented circuitsTime-multiplexing decreases overall performance
Performance gained using overclocking with error toleranceSpeedup of 13% on average compared to baseline design
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ZUMA Config Controller
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data
2k bit counter
Bitstream In(ROM, JTAG)
Tile
addr
Overflow
FF
Begin Config
weD Q
Count
we
dataTile
addrFF
weD Q we
Shift Chain
dataTile
addr
weLUTRAM
data[0]
data[1]LUTRAM
LUTRAM Crossbar
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2m x n Memory
rd addr
wr addr
data in
data out
m
m
LUTRAM
we
nn
n x m Crossbar
data in
data out