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CSE507Computer-Aided Reasoning for Software
Emina Torlak [email protected]
courses.cs.washington.edu/courses/cse507/18sp/
Solver-Aided Languages
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Today
2
Last lecture• Program synthesis
Today • Solver-aided languages
Announcements • Next Wednesday: guest lecture by James Bornholt
• Project presentations next Friday in class• 13 min per team: 10 min presentation + 3 min questions
• Project reports and prototypes due next Friday at 11:00pm topi
cs
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How to build your own solver-aided tool
The classic (hard) way to build a toolWhat is hard about building a solver-aided tool?
An easier way: tools as languagesHow to build tools by stacking layers of languages.
Behind the scenes: symbolic virtual machineHow Rosette works so you don’t have to.
A last look: a few recent applicationsCool tools built with Rosette!
SDSL
SVM
SMT
The classic (hard) way to build a tool
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How to build your own solver-aided tool
The classic (hard) way to build a toolWhat is hard about building a solver-aided tool?
An easier way: tools as languagesHow to build tools by stacking layers of languages.
Behind the scenes: symbolic virtual machineHow Rosette works so you don’t have to.
A last look: a few recent applicationsCool tools built with Rosette!
SDSL
SVM
SMT
The classic (hard) way to build a tool
![Page 5: Computer-Aided Reasoning for Software CSE507 · 2018-05-25 · Layers of classic languages: DSLs and hosts 14 host language library (shallow) embedding interpreter (deep) embedding](https://reader033.vdocument.in/reader033/viewer/2022050315/5f77ce0f383b644612556747/html5/thumbnails/5.jpg)
The classic (hard) way to build a tool
SMT solversolver-aided tool
assert safe(x, P(x))?
P(x) {……
}
Recall the solver-aided programming tool chain: the tool reduces a query about program behavior to an SMT problem.
specification
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Find an input on which the program fails.P(x) {……
}assert safe(x, P(x))
∃x . ¬safe(x, P(x))
42
SMT solver
verifydebugsolvesynthesize
The classic (hard) way to build a tool
solver-aided tool
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Find an input on which the program fails.
Localize bad parts of the program.
assert safe(x, P(x))
∃x . ¬safe(x, P(x))
x = 42 ⋀ safe(x, P(x))
42
SMT solver
verifydebugsolvesynthesize
P(x) {v = x + 2…
}
The classic (hard) way to build a tool
solver-aided tool
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Find an input on which the program fails.
Localize bad parts of the program.
Find values that repair the failing run.
assert safe(x, P(x))
∃x . ¬safe(x, P(x))
x = 42 ⋀ safe(x, P(x))
∃v . safe(42, Pv(42))
42
SMT solver
verifydebugsolvesynthesize
P(x) {v = choice() …
}
40
The classic (hard) way to build a tool
solver-aided tool
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Find an input on which the program fails.
Localize bad parts of the program.
Find values that repair the failing run.
Find code that repairs the program.assert safe(x, P(x))
∃x . ¬safe(x, P(x))
x = 42 ⋀ safe(x, P(x))
∃v . safe(42, Pv(42))
∃e.∀x. safe(x, Pe(x))
SMT solver
verifydebugsolvesynthesize
P(x) {v = ??…
}
x-2
The classic (hard) way to build a tool
solver-aided tool
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SMT solver
The classic (hard) way to build a tool
solver-aided tool
P(x)
symbolic compiler
assert safe(x, P(x))
verifydebugsolvesynthesize
P(x) {……
}
What all queries have in common: they need to translate programs to constraints!
9
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SMT solver
The classic (hard) way to build a tool
10
P(x)
expertise in PL, FM, SE
symbolic compiler
assert safe(x, P(x))
verifydebugsolvesynthesize
P(x) {……
}
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SDSL
programming
Wanted: an easier way to build tools
11
an interpreter for the source
language
assert safe(x, P(x))
verifydebugsolvesynthesize
P(x) {……
}
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SMTSVM
ROSETTE
SMT solversymbolic virtual machine
programming
Wanted: an easier way to build tools
12
assert safe(x, P(x))
verifydebugsolvesynthesize
P(x) {……
}
SDSLan interpreter for the source
language
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SMTSVM
ROSETTE
SMT solversymbolic virtual machine
Wanted: an easier way to build tools
12
[Torlak & Bodik, PLDI’14]
Technical challenge: how to efficiently translate a program and its interpreter?assert safe(x, P(x))
verifydebugsolvesynthesize
P(x) {……
}
SDSLan interpreter for the source
language
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How to build your own solver-aided tool
The classic (hard) way to build a toolWhat is hard about building a solver-aided tool?
An easier way: tools as languagesHow to build tools by stacking layers of languages.
Behind the scenes: symbolic virtual machineHow Rosette works so you don’t have to.
A last look: a few recent applicationsCool tools built with Rosette!
SVM
SMT
The classic (hard) way to build a tool
SDSL
![Page 16: Computer-Aided Reasoning for Software CSE507 · 2018-05-25 · Layers of classic languages: DSLs and hosts 14 host language library (shallow) embedding interpreter (deep) embedding](https://reader033.vdocument.in/reader033/viewer/2022050315/5f77ce0f383b644612556747/html5/thumbnails/16.jpg)
domain-specific language (DSL)
Layers of classic languages: DSLs and hosts
14
host language
A formal language that is specialized to a particular application domain and often limited in capability.
A high-level language for implementing DSLs, usually with meta-programming features.
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domain-specific language (DSL)
Layers of classic languages: DSLs and hosts
14
host language
library(shallow)embedding
interpreter(deep)embedding
A formal language that is specialized to a particular application domain and often limited in capability.
A high-level language for implementing DSLs, usually with meta-programming features.
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domain-specific language (DSL)
Layers of classic languages: many DSLs and hosts
15
host language
library(shallow)embedding
interpreter(deep)embedding
artificial intelligenceChurch, BLOG
databasesSQL, Datalog
hardware designBluespec, Chisel, Verilog, VHDL
math and statisticsEigen, Matlab, R
layout and visualizationLaTex, dot, dygraphs, D3
Racket, Scala, JavaScript, …
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C = A * Bdomain-specific language (DSL)
Layers of classic languages: why DSLs?
16
host language
library(shallow)embedding
interpreter(deep)embedding C / Java
Eigen / Matlab
for (i = 0; i < n; i++) for (j = 0; j < m; j++) for (k = 0; k < p; k++) C[i][k] += A[i][j] * B[j][k]
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C = A * Bdomain-specific language (DSL)
Layers of classic languages: why DSLs?
16
host language
library(shallow)embedding
interpreter(deep)embedding C / Java
Eigen / Matlab
[associativity]C = A * B
for (i = 0; i < n; i++) for (j = 0; j < m; j++) for (k = 0; k < p; k++) C[i][k] += A[i][j] * B[j][k]
Easier for people to read, write, and get right.
Easier for tools to analyze.
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solver-aided domain-specific language (SDSL)
Layers of solver-aided languages
17
solver-aided host language
library(shallow)embedding
interpreter(deep)embedding
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solver-aided domain-specific language (SDSL)
Layers of solver-aided languages: tools as SDSLs
18
library(shallow)embedding
interpreter(deep)embedding
education and gamesEnlearn, RuleSy (VMCAI’18), Nonograms (FDG’17), UCB feedback generator (ITiCSE'17)
synthesis-aided compilationLinkiTools, Chlorophyll (PLDI’14), GreenThumb (ASPLOS’16)
type system soundnessBonsai (POPL’18)
computer architecture MemSynth (PLDI’17)
databasesCosette (CIDR’17)
radiation therapy controlNeutrons (CAV’16)
… and more
ROSETTE
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solver-aided domain-specific language (SDSL)
Layers of solver-aided languages: tools as SDSLs
18
library(shallow)embedding
interpreter(deep)embedding
education and gamesEnlearn, RuleSy (VMCAI’18), Nonograms (FDG’17), UCB feedback generator (ITiCSE'17)
synthesis-aided compilationLinkiTools, Chlorophyll (PLDI’14), GreenThumb (ASPLOS’16)
type system soundnessBonsai (POPL’18)
computer architecture MemSynth (PLDI’17)
databasesCosette (CIDR’17)
radiation therapy controlNeutrons (CAV’16)
… and more
ROSETTE
education and gamesEnlearn, RuleSy (VMCAI’18), Nonograms (FDG’17), UCB feedback generator (ITiCSE'17)
synthesis-aided compilationLinkiTools, Chlorophyll (PLDI’14), GreenThumb (ASPLOS’16)
type system soundnessBonsai (POPL’18)
computer architecture MemSynth (PLDI’17)
databasesCosette (CIDR’17)
radiation therapy controlNeutrons (CAV’16)
… and more
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The anatomy of a solver-aided host language
assertions
symbolic values
queries= +
(define-symbolic id type) (define-symbolic* id type)
(assert expr)
(verify expr) (debug [type ...+] expr) (solve expr) (synthesize #:forall expr #:guarantee expr)
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A tiny example SDSL
BV: A tiny assembly-like language for writing fast, low-level library functions.
20
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
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A tiny example SDSL
BV: A tiny assembly-like language for writing fast, low-level library functions.
20
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
We want to test, verify, debug, and synthesize programs in the BV SDSL.
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A tiny example SDSL
BV: A tiny assembly-like language for writing fast, low-level library functions.
20
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
We want to test, verify, debug, and synthesize programs in the BV SDSL.
1. interpreter [10 LOC]
2. verifier [free]
3. debugger [free]
4. synthesizer [free]
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21
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1)
A tiny example SDSL ROSETTE
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(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
21
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1)
A tiny example SDSL
parse
ROSETTE
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(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
21
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1)
A tiny example SDSL
parse
ROSETTE
(out opcode in ...)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
`(-2 -1)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
(2 bvsge 0 1)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
(2 bvsge 0 1)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
(2 bvsge 0 1)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
(2 bvsge 0 1)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
(2 bvsge 0 1)
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22
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
interpret
0 -21 -12 03 04 -25 06 -1
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
(2 bvsge 0 1)
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23
A tiny example SDSL ROSETTE
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> bvmax(-2, -1) -1
(define bvmax `((2 bvsge 0 1) (3 bvneg 2) (4 bvxor 0 2) (5 bvand 3 4) (6 bvxor 1 5)))
‣ pattern matching‣ dynamic evaluation‣ first-class & higher-
order procedures‣ side effects
(define (interpret prog inputs) (make-registers prog inputs) (for ([stmt prog]) (match stmt [(list out opcode in ...) (define op (eval opcode)) (define args (map load in)) (store out (apply op args))])) (load (last)))
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24
A tiny example SDSL ROSETTE
(define-symbolic* in (bitvector 32) [2]) (verify (assert (equal? (interpret bvmax in) (interpret max in))))
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> verify(bvmax, max) (0, -2)
> bvmax(0, -2) -1
query
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24
A tiny example SDSL ROSETTE
(define-symbolic* in (bitvector 32) [2]) (verify (assert (equal? (interpret bvmax in) (interpret max in))))
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> verify(bvmax, max) (0, -2)
> bvmax(0, -2) -1
query
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24
A tiny example SDSL ROSETTE
(define-symbolic* in (bitvector 32) [2]) (verify (assert (equal? (interpret bvmax in) (interpret max in))))
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> verify(bvmax, max) (0, -2)
> bvmax(0, -2) -1
query
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25
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> debug(bvmax, max,‘(0, -2))
A tiny example SDSL ROSETTE
(define in (list (bv 0 32) (bv -2 32))) (debug [integer?] (assert (equal? (interpret bvmax in) (interpret max in))))
query
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25
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
> debug(bvmax, max,‘(0, -2))
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r2) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
A tiny example SDSL ROSETTE
(define in (list (bv 0 32) (bv -2 32))) (debug [integer?] (assert (equal? (interpret bvmax in) (interpret max in))))
query
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26
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(??, ??) r5 = bvand(r3, ??) r6 = bvxor(??, ??) return r6
> synthesize(bvmax, max)
A tiny example SDSL ROSETTE
(define-symbolic* in (bitvector 32) [2]) (synthesize #:forall in #:guarantee (assert (equal? (interpret bvmax in) (interpret max in)))))
query
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26
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(??, ??) r5 = bvand(r3, ??) r6 = bvxor(??, ??) return r6
> synthesize(bvmax, max)
def bvmax(r0, r1) : r2 = bvsge(r0, r1) r3 = bvneg(r2) r4 = bvxor(r0, r1) r5 = bvand(r3, r4) r6 = bvxor(r1, r5) return r6
A tiny example SDSL ROSETTE
(define-symbolic* in (bitvector 32) [2]) (synthesize #:forall in #:guarantee (assert (equal? (interpret bvmax in) (interpret max in)))))
query
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How to build your own solver-aided tool
The classic (hard) way to build a toolWhat is hard about building a solver-aided tool?
An easier way: tools as languagesHow to build tools by stacking layers of languages.
Behind the scenes: symbolic virtual machineHow Rosette works so you don’t have to.
A last look: a few recent applicationsCool tools built with Rosette!
SVM
SMT
The classic (hard) way to build a tool
SDSL
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SMT solverZ3
ROSETTE
How it all works: a big picture view
28
SDSL
program
query
Symbolic Virtual
Machine
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SMT solverZ3
ROSETTE
How it all works: a big picture view
28
SDSL
program
query result
Symbolic Virtual
Machine
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SMT solverZ3
ROSETTE
How it all works: a big picture view
28
SDSL
program
query result
‣ pattern matching‣ dynamic evaluation‣ first-class procedures ‣ higher-order procedures‣ side effects‣ macros
theories of bitvectors, integers, reals, and uninterpreted functions
Symbolic Virtual
Machine
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(3, 1, -2) (1, 3)
Translation to constraints by example
29
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
reverse and filter, keeping only positive numbers
vs ps
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(3, 1, -2) (1, 3)
Translation to constraints by example
29
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
vs ps
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Translation to constraints by example
29
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
vs psconstraints
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(a, b)
Translation to constraints by example
29
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
vs psconstraints
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a>0 ∧ b>0 (a, b)
Translation to constraints by example
29
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
vs psconstraints
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Design space of precise symbolic encodings
30
symbolic execution
bounded model checkingsolve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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{ }a > 0b ≤ 0false
Design space of precise symbolic encodings
30
a > 0
b ≤ 0
ps ↦ (a)
ps ↦ (a)
vs ↦ (a, b)ps ↦ ( )
symbolic execution
bounded model checkingsolve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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{ }a > 0b ≤ 0false
∨ ∨ ∨
Design space of precise symbolic encodings
30
a > 0
b ≤ 0
ps ↦ (a)
ps ↦ (a)
vs ↦ (a, b)ps ↦ ( )
b > 0b > 0
ps ↦ (b) ps ↦ (b, a)
{ }a ≤ 0b > 0false
{ }a > 0b > 0true
a ≤ 0
b ≤ 0
ps ↦ ( )
ps ↦ ( )
{ }a ≤ 0b ≤ 0false
symbolic execution
bounded model checkingsolve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)
ps ↦ ps0
ps ↦ ( )
{ }a > 0b ≤ 0false
∨ ∨ ∨
Design space of precise symbolic encodings
30
a > 0a ≤ 0
ps0 = ite(a > 0, (a), ( ))ps1 = insert(b, ps0)ps2 = ite(b > 0, ps0, ps1)assert len(ps2) = 2
a > 0
b ≤ 0
ps ↦ (a)
ps ↦ (a)
vs ↦ (a, b)ps ↦ ( )
b > 0b > 0
ps ↦ (b) ps ↦ (b, a)
{ }a ≤ 0b > 0false
{ }a > 0b > 0true
a ≤ 0
b ≤ 0
ps ↦ ( )
ps ↦ ( )
{ }a ≤ 0b ≤ 0false
symbolic execution
bounded model checkingsolve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)
ps ↦ ps0
ps ↦ ( )
ps ↦ ps1
{ }a > 0b ≤ 0false
∨ ∨ ∨
Design space of precise symbolic encodings
30
a > 0a ≤ 0
ps0 = ite(a > 0, (a), ( ))ps1 = insert(b, ps0)ps2 = ite(b > 0, ps0, ps1)assert len(ps2) = 2
a > 0
b ≤ 0
ps ↦ (a)
ps ↦ (a)
vs ↦ (a, b)ps ↦ ( )
b > 0b > 0
ps ↦ (b) ps ↦ (b, a)
{ }a ≤ 0b > 0false
{ }a > 0b > 0true
a ≤ 0
b ≤ 0
ps ↦ ( )
ps ↦ ( )
{ }a ≤ 0b ≤ 0false
symbolic execution
bounded model checking
b > 0
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)
ps ↦ ps0
ps ↦ ( )
ps ↦ ps1
ps ↦ ps2
ps ↦ ps0
{ }a > 0b ≤ 0false
∨ ∨ ∨
Design space of precise symbolic encodings
30
a > 0a ≤ 0
ps0 = ite(a > 0, (a), ( ))ps1 = insert(b, ps0)ps2 = ite(b > 0, ps0, ps1)assert len(ps2) = 2
a > 0
b ≤ 0
ps ↦ (a)
ps ↦ (a)
vs ↦ (a, b)ps ↦ ( )
b > 0b > 0
ps ↦ (b) ps ↦ (b, a)
{ }a ≤ 0b > 0false
{ }a > 0b > 0true
a ≤ 0
b ≤ 0
ps ↦ ( )
ps ↦ ( )
{ }a ≤ 0b ≤ 0false
symbolic execution
bounded model checking
b > 0b ≤ 0
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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A new design: type-driven state merging
31
{ }a > 0b > 0true
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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Merge values of‣ primitive types: symbolically‣ immutable types: structurally‣ all other types: via unions
A new design: type-driven state merging
31
{ }a > 0b > 0true
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
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Merge values of‣ primitive types: symbolically‣ immutable types: structurally‣ all other types: via unions
ba
A new design: type-driven state merging
31
{ }a > 0b > 0true
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
⁊g g
c
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Merge values of‣ primitive types: symbolically‣ immutable types: structurally‣ all other types: via unions
ba (c, d)(a, b)
A new design: type-driven state merging
31
{ }a > 0b > 0true
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
⁊g g
c(e, f)
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Merge values of‣ primitive types: symbolically‣ immutable types: structurally‣ all other types: via unions
ba (c, d)
A new design: type-driven state merging
31
{ }a > 0b > 0true
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
⁊g g
c(e, f){ ¬g ⊦ a, g ⊦ () }
()
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solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
A new design: type-driven state merging
32
symbolic virtual machine
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solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
a > 0a ≤ 0
A new design: type-driven state merging
32
vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)ps ↦ ( )
symbolic virtual machine
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Symbolic union: a set of guarded values, with disjoint guards.
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
g0 = a > 0g1 = b > 0 g2 = g0 ∧ g1
g3 = ¬(g0 ⇔ g1)g4 = ¬g0 ∧ ¬g1
c = ite(g1, b, a)assert g2
a > 0a ≤ 0 g0¬ g0
A new design: type-driven state merging
32
vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)ps ↦ ( )
symbolic virtual machine
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
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Execute insert concretely on all lists in the union.
solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
g0 = a > 0g1 = b > 0 g2 = g0 ∧ g1
g3 = ¬(g0 ⇔ g1)g4 = ¬g0 ∧ ¬g1
c = ite(g1, b, a)assert g2
a > 0a ≤ 0
g1
g0¬ g0
A new design: type-driven state merging
32
vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)ps ↦ ( )
symbolic virtual machine
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
ps ↦ { g0 ⊦ (b, a), ¬g0 ⊦ (b) }
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solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
g0 = a > 0g1 = b > 0 g2 = g0 ∧ g1
g3 = ¬(g0 ⇔ g1)g4 = ¬g0 ∧ ¬g1
c = ite(g1, b, a)assert g2
a > 0a ≤ 0
¬ g1 g1
g0¬ g0
A new design: type-driven state merging
32
vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)ps ↦ ( )
symbolic virtual machine
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
ps ↦ { g0 ⊦ (b, a), ¬g0 ⊦ (b) }
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
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solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
Evaluate len concretely on all lists in the union; assertion true only on the list guarded by g2.
g0 = a > 0g1 = b > 0 g2 = g0 ∧ g1
g3 = ¬(g0 ⇔ g1)g4 = ¬g0 ∧ ¬g1
c = ite(g1, b, a)assert g2
a > 0a ≤ 0
¬ g1 g1
g0¬ g0
A new design: type-driven state merging
32
vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)ps ↦ ( )
symbolic virtual machine
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
ps ↦ { g0 ⊦ (b, a), ¬g0 ⊦ (b) }
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
ps ↦ { g2 ⊦ (b, a), g3 ⊦ (c), g4 ⊦ ( ) }
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solve: ps = () for v in vs: if v > 0: ps = insert(v, ps) assert len(ps) == len(vs)
g0 = a > 0g1 = b > 0 g2 = g0 ∧ g1
g3 = ¬(g0 ⇔ g1)g4 = ¬g0 ∧ ¬g1
c = ite(g1, b, a)assert g2
a > 0a ≤ 0
¬ g1 g1
g0¬ g0
A new design: type-driven state merging
32
vs ↦ (a, b)ps ↦ ( )
ps ↦ (a)ps ↦ ( )
symbolic virtual machine
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
ps ↦ { g0 ⊦ (b, a), ¬g0 ⊦ (b) }
ps ↦ { g0 ⊦ (a), ¬g0 ⊦ ( ) }
ps ↦ { g2 ⊦ (b, a), g3 ⊦ (c), g4 ⊦ ( ) }
concrete evaluation
polynomial encoding
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How to build your own solver-aided tool
The classic (hard) way to build a toolWhat is hard about building a solver-aided tool?
An easier way: tools as languagesHow to build tools by stacking layers of languages.
Behind the scenes: symbolic virtual machineHow Rosette works so you don’t have to.
A last look: a few recent applicationsCool tools built with Rosette!
SVM
SMT
The classic (hard) way to build a tool
SDSL
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Chlorophyll: ultra low-power computing
DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11 5
2. Basic Architecture The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host") configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O committed as possible so that pure, dedicated applications may be prototyped.
2.1 Highlights Three FTDI USB to serial chips provide high speed (960 kBaud) communications for interactive software development and general-purpose host communications.
An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply. Whichever of these is offering the highest voltage is used by the regulator.
A barrier strip provides for connection of bench power supplies. Each of the power buses of the two GA144 chips may selectively be run from external power in lieu of the onboard regulator, allowing you to run either chip from any desired VDD voltage and also facilitating current measurements.
The Host chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord (2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eForth and polyFORTH, or for direct use by your own F18 code.
The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully configurable, and with the exception of a SERDES line connecting it with the Host chip, all other communications (two 2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for any desired use.
Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers. By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as those made by SchmartBoard. The grid is intentionally large enough to support an 8- or 16-bit PC-104 socket.
The periphery of the prototyping area is provided with hole patterns for many popular connectors, and there are six 8-bit bidirectional level shifters for interfacing with external circuits that may not run on 1.8v. In addition, one 1.8v 2-input OR and three NANDs are available for use in external circuitry.
Figure by Per Ljung
Instructions/Second vs Power
~100x
GreenArrays GA144 Processor
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Chlorophyll: ultra low-power computing
DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11 5
2. Basic Architecture The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host") configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O committed as possible so that pure, dedicated applications may be prototyped.
2.1 Highlights Three FTDI USB to serial chips provide high speed (960 kBaud) communications for interactive software development and general-purpose host communications.
An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply. Whichever of these is offering the highest voltage is used by the regulator.
A barrier strip provides for connection of bench power supplies. Each of the power buses of the two GA144 chips may selectively be run from external power in lieu of the onboard regulator, allowing you to run either chip from any desired VDD voltage and also facilitating current measurements.
The Host chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord (2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eForth and polyFORTH, or for direct use by your own F18 code.
The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully configurable, and with the exception of a SERDES line connecting it with the Host chip, all other communications (two 2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for any desired use.
Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers. By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as those made by SchmartBoard. The grid is intentionally large enough to support an 8- or 16-bit PC-104 socket.
The periphery of the prototyping area is provided with hole patterns for many popular connectors, and there are six 8-bit bidirectional level shifters for interfacing with external circuits that may not run on 1.8v. In addition, one 1.8v 2-input OR and three NANDs are available for use in external circuitry.
Manual program partitioning: break programs up into a pipeline with a few operations per core.
Drawing by Mangpo Phothilimthana
GreenArrays GA144 Processor
‣ Stack-based 18-bit architecture‣ 32 instructions ‣ 8 x 18 array of asynchronous cores‣ No shared resources (cache, memory)‣ Limited communication, neighbors only‣ < 300 byte memory per core
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Chlorophyll: ultra low-power computing
DB003 Evaluation Board Reference for EVB001
Copyright© 2010-2011 GreenArrays, Inc. 9/26/11 5
2. Basic Architecture The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host") configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O committed as possible so that pure, dedicated applications may be prototyped.
2.1 Highlights Three FTDI USB to serial chips provide high speed (960 kBaud) communications for interactive software development and general-purpose host communications.
An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply. Whichever of these is offering the highest voltage is used by the regulator.
A barrier strip provides for connection of bench power supplies. Each of the power buses of the two GA144 chips may selectively be run from external power in lieu of the onboard regulator, allowing you to run either chip from any desired VDD voltage and also facilitating current measurements.
The Host chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord (2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eForth and polyFORTH, or for direct use by your own F18 code.
The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully configurable, and with the exception of a SERDES line connecting it with the Host chip, all other communications (two 2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for any desired use.
Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers. By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as those made by SchmartBoard. The grid is intentionally large enough to support an 8- or 16-bit PC-104 socket.
The periphery of the prototyping area is provided with hole patterns for many popular connectors, and there are six 8-bit bidirectional level shifters for interfacing with external circuits that may not run on 1.8v. In addition, one 1.8v 2-input OR and three NANDs are available for use in external circuitry.
Drawing by Mangpo Phothilimthana
GreenArrays GA144 Processor
‣ Stack-based 18-bit architecture‣ 32 instructions ‣ 8 x 18 array of asynchronous cores‣ No shared resources (cache, memory)‣ Limited communication, neighbors only‣ < 300 byte memory per core
34
ab
1
*
2
c
3
c = a * b
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Synthesizes placement of code and data onto cores, by type-checking a program sketch in a C-like DSL.
int a, b; int c = a * b;
ab
1
*
2
c
3
Chlorophyll: ultra low-power computing
35
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Synthesizes placement of code and data onto cores, by type-checking a program sketch in a C-like DSL.
int a, b; int c = a * b;
ab
1
*
2
c
3
int@1 a, b; int@3 c = a *@2 b;
type-checking a program
Chlorophyll: ultra low-power computing
35
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Synthesizes placement of code and data onto cores, by type-checking a program sketch in a C-like DSL.
int a, b; int c = a * b;
ab
1
*
2
c
3
int@1 a, b; int@3 c = a *@2 b;int@?? a, b; int@?? c = a *@?? b;
sketch
Chlorophyll: ultra low-power computing
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int a, b; int c = a * b;
ab
1
*
2
c
3
int@1 a, b; int@3 c = a *@2 b;int@?? a, b; int@?? c = a *@?? b;
Phitchaya Mangpo Phothilimthana
Built by a first-year grad in a few weeks
Chlorophyll: ultra low-power computing
35
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int a, b; int c = a * b;
ab
1
*
2
c
3
int@1 a, b; int@3 c = a *@2 b;int@?? a, b; int@?? c = a *@?? b;
[Phothilimthana et al., PLDI’14]
Chlorophyll: ultra low-power computing
35
With Chlorophyll, it took one afternoon to build a set of apps that took 3 months to build manually.
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• 30 years of incident-free service. • Controlled by custom software, built
by CNTS engineering staff. • Third generation of Therapy Control
software built recently.
Clinical Neutron Therapy System (CNTS) at UW
Neutrons: verifying a radiotherapy system
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Sensors
Beam, motors, etc.
Prescription
Therapy Control Software
Clinical Neutron Therapy System (CNTS) at UW
Neutrons: verifying a radiotherapy system
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Experimental Physics and Industrial Control System (EPICS) Dataflow Language
Neutrons: verifying a radiotherapy system
37
Sensors
Beam, motors, etc.
Prescription
Therapy Control Software
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The Maximize Severity attribute is one of NMS (Non-Maximize Severity), MS (Maximize Severity), MSS (Maximize Status and Severity) or MSI (Maximize Severity if Invalid). It determines whether alarm severity is propagated across links. If the attribute is MSI only a severity of INVALID_ALARM is propagated; settings of MS or MSS propagate all alarms that are more severe than the record's current severity. For input links the alarm severity of the record referred to by the link is propagated to the record containing the link. For output links the alarm severity of the record containing the link is propagated to the record referred to by the link. If the severity is changed the associated alarm status is set to LINK_ALARM, except if the attribute is MSS when the alarm status will be copied along with the severity.
EPICS documentation / semantics
Neutrons: verifying a radiotherapy system
37
Sensors
Beam, motors, etc.
Prescription
Therapy Control Software
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bug report
Built by a 2nd year grad in a few days
Calvin Loncaric
EPICS Verifier
safety propertyEPICS
program
Neutrons: verifying a radiotherapy system
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Found a bug in the EPICS runtime! Therapy Control depended on this bug for correct operation.
Neutrons: verifying a radiotherapy system
39
[Pernsteiner et al., CAV’16]
EPICS Verifier
safety propertyEPICS
program
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40
MemSynth: synthesizing memory models
x = y = 0a = x b = yy = 1 x = 1a ≡ b ≡ 1
Memory consistency models define memory reordering behaviors on multiprocessors.
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40
MemSynth: synthesizing memory models
x = y = 0a = x b = yy = 1 x = 1a ≡ b ≡ 1
Memory consistency models define memory reordering behaviors on multiprocessors.
Forbidden by sequential consistency.
Allowed by x86 and other hardware memory models.
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40
MemSynth: synthesizing memory models
x = y = 0a = x b = yy = 1 x = 1a ≡ b ≡ 1
Memory consistency models define memory reordering behaviors on multiprocessors.
Forbidden by sequential consistency.
Allowed by x86 and other hardware memory models.
Formalizing memory models is hard: e.g., PowerPC formalized over 7 publications in 2009-2015.
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40
MemSynth: synthesizing memory models
x = y = 0a = x b = yy = 1 x = 1a ≡ b ≡ 1
Memory consistency models define memory reordering behaviors on multiprocessors.
Forbidden by sequential consistency.
Allowed by x86 and other hardware memory models.
Memory model specification
Relational logic
A set of litmus tests
A framework sketch
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MemSynth: synthesizing memory models
Memory model specification
Relational logic
A set of litmus tests
A framework sketch
Built by a 2nd year grad in a few weeks
James Bornholt
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MemSynth: synthesizing memory models
Memory model specification
Relational logic
A set of litmus tests
A framework sketch
[Bornholt and Torlak, PLDI’17]
Synthesized PowerPC in 12 seconds from 768 previously published tests.Synthesized x86 in 2 seconds from Intel’s litmus tests. Discovered 4 tests are missing from the Intel manual.
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Thanks for a great quarter!