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Page 1: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

Conditional StatementsConditional Statements

if if and and else if else if statementsstatements if if (expressio(expression)n) statementsstatements { { else if else if (expressio(expression)n) statements statements }} [ [ elseelse statements statements ]] if if (total < 60) (total < 60) beginbegin grade = C;grade = C; total_C = total_C + 1;total_C = total_C + 1; endend else if else if (sum < 75) (sum < 75) beginbegin grade = B;grade = B; total_B = total_B + 1;total_B = total_B + 1; endend else else grade = A;grade = A;

Page 2: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

Conditional StatementsConditional Statements

case case statementstatement case case (case_expressio(case_expression)n) case_item_expressioncase_item_expression {, {, case_item_expression case_item_expression }:}: statements statements case_item_expressioncase_item_expression {, {, case_item_expression case_item_expression }:}: statements statements …… …… [ [ defauldefault: t: statements statements ]] endcaseendcase

casecase (OP_CODE) (OP_CODE) 2`b10: Z = A + B;2`b10: Z = A + B; 2`b11: Z = A – B;2`b11: Z = A – B; 2`b01: Z = A * B;2`b01: Z = A * B; 2`b00: Z = A / B;2`b00: Z = A / B; defaultdefault: Z = 2`bx;: Z = 2`bx; endcaseendcase

Page 3: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

Loop StatementsLoop Statements

Four loop statements are supportedFour loop statements are supported– ThThe for e for looploop– ThThe while e while looploop– ThThe repeat e repeat looploop– ThThe forever e forever looploop

The syntax of loop statements is very The syntax of loop statements is very similar to that in C languagesimilar to that in C language

Most of the loop statements are not Most of the loop statements are not synthesizable in current commercial synthesizable in current commercial synthesizerssynthesizers

Page 4: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

for loopfor loop for (initial condition; terminating condition; increment)for (initial condition; terminating condition; increment)

beginbegin……....endend

for (i=0;i<32;i=i+1) state[i]=0;for (i=0;i<32;i=i+1) state[i]=0; for (i=0;i<32;i=i+2)for (i=0;i<32;i=i+2)

beginbeginstate[i]=1;state[i]=1;

state[i+32]=0;state[i+32]=0;endend

Page 5: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

repeat looprepeat loop

repeat(constant number)repeat(constant number) connot be used to loop on a general logical exconnot be used to loop on a general logical ex

pressionpression repeat(128)repeat(128)

beginbegin$display(“count=%d”,count);$display(“count=%d”,count);count=count+1;count=count+1;endend

Page 6: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

forever loop forever loop

execute forever until the execute forever until the $finish$finish task task is encountered.is encountered.

clock=1’b0;clock=1’b0;

forever #10 clock=~clock;forever #10 clock=~clock;

Page 7: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

while loopwhile loop

while (logical expression)while (logical expression)beginbegin

…… …….. endend

while ((i<128) && continue)while ((i<128) && continue)beginbegin

$display(“count=%d”, count);$display(“count=%d”, count);i=i+1;i=i+1;

endend

while ((i<128) && continue) i=i+1;while ((i<128) && continue) i=i+1;

Page 8: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

ExampleExample-- ASM designed by HDL-- ASM designed by HDL

This example is referred from “Digital Design “, M. Morris Mano

Page 9: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

ExampleExample-- ASM designed by HDL-- ASM designed by HDL

Page 10: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

ExampleExample-- ASM designed by HDL-- ASM designed by HDL

Page 11: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

ExampleExample-- ASM designed by HDL-- ASM designed by HDL

Page 12: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

ExampleExample-- ASM designed by HDL-- ASM designed by HDL

//RTL description of design example (Fig.8-11) module Example_RTL (S,CLK,Clr,E,F,A);//Specify inputs and outputs //See block diagram Fig. 8-10 input S,CLK,Clr;output E, F;output [4:1] A;//Specify system registersreg [4:1] A; //A register reg E, F; //E and F flip-flops reg [1:0] pstate, nstate; //control register //Encode the statesparameter T0 = 2'b00, T1= 2'b01, T2 = 2'b11;//State transition for control logic //See state diagram Fig. 8-11(a)always @(posedge CLK or negedge Clr)if (~Clr) pstate = T0; //Initial state else pstate <= nstate; //Clocked operations always @ (S or A or pstate) case (pstate) T0: if (S) nstate = T1; else nstate = T0; T1: if (A[3] & A[4]) nstate = T2; else nstate = T1; T2: nstate = T0;endcase

//Register transfer operations //See list of operation Fig.8-11(b)always @ (posedge CLK) case (pstate) T0: if (S) begin A <= 4'b0000; F <= 1'b0; end T1: begin A <= A + 1'b1; if (A[3]) E <= 1'b1; else E <= 1'b0; end T2: F <= 1'b1;endcase endmodule

Page 13: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

ExampleExample-- ASM designed by HDL-- ASM designed by HDL

//Test bench for design example//Test bench for design examplemodulemodule test_design_example; test_design_example;regreg S, CLK, Clr; S, CLK, Clr; wire [4:1] A;wire [4:1] A; wirewire E, E, F; F;//Instantiate design example//Instantiate design exampleExample_RTL dsexp (S,CLK.Clr,E,F,A);Example_RTL dsexp (S,CLK.Clr,E,F,A);initialbeginClr = 0;S = 0;CLK = 0;#5 Clr = 1; S = 1;repeat (32)begin#5 CLK = ~ CLK;endendinitial$monitor("A = %b E = %b F = %b time = %0d”, A.E.F,$time);endmodule

Page 14: Conditional Statements if and else if statements if (expression) if (expression) statements statements { else if (expression) { else if (expression)

Simulation resultsSimulation results計 數 器 正 反 器

A4 A3 A2 A1 E F 條 件 狀 態

0 0 0 0 1 0

0 0 0 1 0 0

0 0 1 0 0 0

0 0 1 1 0 0

A3 = 0 , A4 = 0 T1

0 1 0 0 0 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 1 0

A3 = 1 , A4 = 0

1 0 0 0 1 0

1 0 0 1 0 0

1 0 1 0 0 0

1 0 1 1 0 0

A3 = 0 , A4 = 1

1 1 0 0 0 0 A3 = 1 , A4 = 1

1 1 0 1 1 0 T2

1 1 0 1 1 1 T0

Table 8-2


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