copyright 2002
An Analog Turbo Decoderfor an (8,4) Product Code
Matthew C. Valenti
Assistant Professor
Lane Dept. of Comp. Sci. & Elect. Eng.
West Virginia University
Morgantown, WV
Neiyer Correal and Joe Heck
Florida Communications Research Labs
Motorola
Plantation, FL
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Motivation & Goals
Motivation Iteratively decodable code are capable of near-
Shannon limit performance.• e.g. turbo codes, LDPC codes, turbo product codes.
Digital hardware has its limitations• Clock functions demand power and real estate.• Turbo decoding uses nonlinear functions that are
awkward in digital but natural in analog.
Goal of this study To design and implement a simple iterative
decoder in analog.• Simple: (8,4) product code created using a 2 by 2 array
of (3,2) single parity check codes. Target throughput is 1 Gbps
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Overview of Talk
Related work Single parity check (SPC) codes
Encoder Soft-input/Soft-output (SISO) decoder Analog design of the SISO decoder
Turbo product codes Encoder Turbo Decoder
Comments & Conclusions
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Related Work
Inspiration: Carver Mead (Cal Tech) 1980’s Observation: nervous cells and CMOS transistors
operating in subthreshold mode have same physics.
Adaptive analog systems with the robustness of digital yet 2-orders of magnitude reduction in power.
Primarily image processing applications. Recent work: Turbo Decoding
J. Hagenauer (T.U. Munich)• Log-likelihood domain circuits.
Loeliger + Lustenberger (E.T.H. Zurich)• Circuits operate on raw probabilities rather than LLRs.
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Single Parity Check Codes
Generic (n,k) SPC code: The input to the SPC encoder is a stream of k data
bits: {u1, u2, …, uk} A single parity bit is created by xor-ing the data:
up = u1u2uk
The n=k+1 bit output is the k input bits and the parity bit: u = {u1, u2, …, uk ,up}
The (3,2) SPC code: Let the two input bits be denoted uj and uk
The parity bit is uj,k = ujuk
The output is u = {uj, uk, uj,k }
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Modulation and Channel Model
BPSK modulation x = +1 if u = 0 and x = -1 if u = 1 Modulated code word: x = {xj, xk, xj,k }
Received code word: y = {yj, yk, yj,k }
Channel characterized by conditional pdf: f(y|x)
• AWGN:
• Rayleigh flat-fading
2,Ε~)|( 0Nxxyf s
2,~)|( 0NEaxxyf s
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Scaling the Input
Input to the SISO decoder must be scaled: In log-likelihood form:
Decoder input is: r={rj,rk,rj,k}={L(yj|xj),L(yk|xk),L(yj,k|xj,k)}
0
4)1|(
)1|(ln)|(
N
Eay
xyf
xyfxyL s
SNRfade coefficient (=1 for AWGN)
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APP SISO Decoder
Input-output relationships (BCRJ algorithm):
SISOdec.#1rk
rjrj,k
scaledchannel
observations
L(xk)
L(xj)
a prioriinformationfrom other
decoders
Le(xj)
Le(xk)
extrinsicinformationto other decoders
L(uj|y)
L(uk|y)
a posterioriestimates:
used to makefinal bit decision
)()()|(
)()()|(
2
)(tanh
2tanhtanh2)(
2
)(tanh
2tanhtanh2)(
,1
,1
kekkk
jejjj
jjkjke
kkkjje
xLxLrxL
xLxLrxL
xLrrxL
xLrrxL
y
y
extrinsicinformation:exploits structure of code
a posterioriLLR estimates
]1[
]1[ln)(
xP
xPxL
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Box-Plus Operator
The heart of the decoder is a soft-xor operation, also called “box-plus”
This can be implemented in analog by a modified Gilbert multiplier
2
)(tanh
2
)(tanhtanh2 )( ,1
,,kjj
kjjkjj
uLuLuuuuL
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1V
2V
II
oV
EEI
1I 2IccV
ccV
Current Mirror
Current Mirror
2
)(tanh
2
)(tanhtanh2 )( ,1
,,kjj
kjjkjj
uLuLuuuuL
Modified Gilbert Multiplier
Computing Extrinsic Information
Vgp
rk/VT L(xk)/VT
Vdda
Vdda Vdda
Vbn
rj,k/VT
Le(xj)/VT
Q10Q13
R12
Q0Q1
L(xk)
Le(xj)
rk
rj,k
50 A
50 A
+
+
+
+
Computing a Posteriori LLR
+rj/VT
Vdda
+L(xj)/VT
+Le(xj)/VT
R8
R6 R7
Vbn
L(xj|y)/VT
+
L(xj|y)
rj
L(xj)
Le(xj)
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SISO Decoder for (3,2) SPC Code
Components: 2 units for computing extrinsic information.
• 6 PMOS + 10 BJT transistors + 7 resistors each. 2 units for computing a priori LLR.
• 9 BJT transistors + 9 resistors each.
L(xj)
L(xk)
Le(xj)
Le(xk)
rj
rk
L(xj|y)
rj,k
L(xk|y)
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Product Codes
A more powerful code can be created by using multiple SPC codes. 2 by 2 array of SPC codes can correct a single
error when using hard decision decoding. However, we want a soft-decision decoder.
=
=
u1 u2 u1,2
u3 u4 u3,4
u1,3 u2,4
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Turbo Decoding of Product Codes
r1 r2 r1,2
r3 r4 r3,4
r1,3 r2,4
Le(x1) Le(x2)
Le(x3) Le(x4)
Le(x1)
Le(x3)
Le(x2)Le(x4)
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Turbo DecoderL(u1|y)
L(u2|y)
L(u3|y)
L(u4|y)
horiz.dec.#1
horiz.dec.#2
verticaldec. #1
verticaldec. #2
r1 r2r1,2
r3,4
r3
r4
r1,3 r2,4
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Vertical Decoder
The a priori LLR is computed using the output of the horizontal decoding.
Thus, the vertical decoder does not need the three-input adders
L(xj)
L(xk)
Le(xj)
Le(xk)
rj
rk
rj,k
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Circuit Complexity
Two horizontal decoders, each with: 2 units for computing extrinsic information. 2 units for computing a priori LLR.
Two vertical decoders, each with: 2 units for computing extrinsic information.
Total complexity: 8 units for computing extrinsic information. 4 units for computing a priori LLR. 48 PMOS transistors 116 BJT transistors 92 Resistors
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Comments on Analog Decoding
Complicated codes can be decoded using the same approach.
Cascade of analog cells. Problems
Transistor mismatch.• Equivalent to having additional noise at input.• Current transistor tolerances have same impact as using 5-10
bit quantization in a digital implementation. Thermal gradients
• Proper scaling will mitigate intercell gradients.• However, intracell gradients will hurt performance.
Decoding serial data in parallel• Need to store analog values (e.g. sample/hold).• Could work well with multicarrier modulation.
Design and test• Spice-level simulations needed, but take too long.
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Conclusion
Advantages of analog decoders: No costly clock functions smaller footprint/expense. No concept of iteration faster convergence. easily implemented nonlinear functions.
Implementation issues may hinder performance However, suboptimality in local cells is okay as long as
overall system performance is acceptable.
Extensions of this work (n,k) SPC code for k>2. Product code with 3 dimensions or more. Other types of codes: Hamming, BCH. Turbo and LDPC codes. Other iterative processing schemes, e.g. turbo-EQ