Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
2
Copyright © 2005 Altera Corporation
ObjectivesObjectives Generate & Optimize a Cyclone & Cyclone II
Design Use Quartus II Software to Enable & Disable
Cyclone & Cyclone II Features Design a Multi-Clock System Using PLLs & Clock
Resources Describe features in Cyclone & Cyclone II for
implementing a DDR Memory Interface Choose a Configuration Strategy Configure a Cyclone Device
3
Copyright © 2005 Altera Corporation
AgendaAgenda Introduction to Altera, Cyclone™, & Cyclone II Architecture
Logic Structure Clocking Infrastructure & PLLs Memory Embedded Multipliers I/O Architecture
Double-Data Rate (DDR) Low-Voltage Differential Signaling (LVDS)
Configuration
4
Copyright © 2005 Altera Corporation
Intellectual Property (IP) Signal Processing Communications Embedded Processors
Nios®, Nios II
Devices (continued) MAX® II Mercury™ Devices ACEX® Devices FLEX® Devices MAX Devices
Tools Quartus® II Software SOPC Builder DSP Builder Nios II IDE
Devices Stratix® II™
Cyclone II Stratix GX Stratix Cyclone
The Programmable Solutions Company®The Programmable Solutions Company®
5
Copyright © 2005 Altera Corporation
Structured ASIC Stratix HardCopy, HardCopy Stratix
High & Medium Density FPGAs Stratix II, Stratix, APEX™II, APEX 20K,
& FLEX 10K Low-Cost FPGAs
Cyclone II, Cyclone FPGAs with Clock Data Recovery
Stratix GX & Mercury CPLDs
MAX II, MAX 7000 & MAX 3000 Embedded Processor Solutions
Nios™ II, Excalibur™
Configuration Devices Serial (EPCS) & Enhanced (EPC)
Programmable Logic FamiliesProgrammable Logic Families
6
Copyright © 2005 Altera Corporation
Software & Development ToolsSoftware & Development Tools Quartus II
All Stratix, Cyclone & Hardcopy Devices APEX II, APEX 20K/E/C, Excalibur, &
Mercury Devices FLEX 10K/A/E, ACEX 1K, FLEX 6000
Devices MAX II, MAX 7000S/AE/B, MAX 3000A
Devices Quartus II Web Edition
Free Version Not All Features & Devices Included
See www.altera.com for Feature Comparison
MAX+PLUS® II All FLEX, ACEX, & MAX Devices
7
Copyright © 2005 Altera Corporation
Altera’s Low-Cost RoadmapAltera’s Low-Cost Roadmap
1997 2000 2002 2004
Low Cost by DesignLow Cost by Design
New Era of Designingfor Low Cost
8
Copyright © 2005 Altera Corporation
Designing for Low CostDesigning for Low CostCustomerRequirements
Populate Core with LEs & Dedicated Functions
Optimize Layout
PLLs
MemoryLogic
I/O
Optimize I/O Pins for Each Package1 2
3 4
9
Copyright © 2005 Altera Corporation
Cyclone Device FamilyCyclone Device Family Altera’s First-Generation Low-
Cost FPGA Family Designed Based on Customer
Requirements
Industry’s Lowest-Cost FPGA Family Shipping Today Higher Performance Than
Other Low-Cost FPGAs
Millions of Units Shipped Fastest Product Ramp in
20-Year Altera History Eliminates Low-End ASIC
Decision
Shipping Today in Production Volumes!
10
Copyright © 2005 Altera Corporation
Introducing Cyclone II FPGAsIntroducing Cyclone II FPGAs The Lowest-Cost FPGAs Ever
30% Lower Cost than Cyclone Over 3X the Density than Cyclone
Optimized for Cost from the Start Lowest Price per Logic Density I/O-Rich Offerings
Enhanced Feature Set Dedicated DSP Functionality Dedicated External Memory
Interface Circuitry Proven 90-nm Process Technology
Second Altera Product on TSMC’s90-nm Process
11
Copyright © 2005 Altera Corporation
Cyclone Family OverviewCyclone Family Overview
Device Logic Elements
PLL Memory Bits
Maximum User I/O
Pins
LVDS Compatible Channels
EP1C3 2,910 1 59 K 104 34
EP1C4 4,000 2 76 K 301 129
EP1C6 5,980 2 90 K 185 72
EP1C12 12,060 2 234 K 249 103
EP1C20 20,060 2 288 K 301 129
12
Copyright © 2005 Altera Corporation
Cyclone Packaging & User I/OCyclone Packaging & User I/O
Device
100-PinTQFP0.5 mm
16 x 16
144-PinTQFP0.5 mm
22 x 22
240-Pin PQFP0.5 mm
32 x 32
256-PinFBGA1.0 mm
17 x 17
324-Pin FBGA1.0 mm19 x 19
400-Pin FBGA1.0 mm
21 x 21
EP1C3 65 104
EP1C4 249 301
EP1C6 98 185 185
EP1C12 173 185 249
EP1C20 233 301
Denotes Vertical Migration
13
Copyright © 2005 Altera Corporation
Cyclone II Family OverviewCyclone II Family Overview
DeviceLogic
Elements PLLsM4K
MemoryBlocks
Total Memory
Bits
18x18 Embedded Multipliers
MaximumUser
I/O Pins
EP2C5 4,608 2 26 119,808 13 142
EP2C8 8,256 2 36 165,888 18 182
EP2C20 18,752 4 52 239,616 26 315
EP2C35 33,216 4 105 483,840 35 475
EP2C50 50,528 4 129 594,432 86 450
EP2C70 68,416 4 250 1,152,000 150 622
14
Copyright © 2005 Altera Corporation
Cyclone II Packaging & User I/OCyclone II Packaging & User I/O
15
Copyright © 2005 Altera Corporation
Over 40 Optimized IP CoresOver 40 Optimized IP Cores Nios II Soft-Core Processor
Plus a Large Suite of Peripherals in SOPC Builder
Digital Signal Processing FFT & FIR Compiler
I/O Interfaces 10/100/1000 Ethernet MAC PCI & PCI-X PL2 & PL3 Utopia
Memory Controllers DDR2 & QDRII
16
Copyright © 2005 Altera Corporation
Ordering CodesOrdering Codes
EP2C
35
F
484
C
7
Device Family (EP1C = Cyclone; EP2C = Cyclone II)
Approximately # of Logic Elements (LE)s x 1000
Package Type: F = Fineline BGA, P = PQFP
Total Package Pins
Operating Temperature: Commercial, Industrial
Speed Grade: 6 (Fastest), 7, or 8
EP2C35F484C7
17
Copyright © 2005 Altera Corporation
Cyclone/Cyclone II ArchitectureCyclone/Cyclone II Architecture Logic Elements
General Purpose Logic Functions PLLs & Clock Generation
On- & Off-Chip Timing Management Embedded Memory
General Purpose Internal Storage Embedded Multipliers (Cyclone II)
DSP Functions Input/Output (I/O)
Double-Data Rate (DDR) & High-Speed Differential Support
Configuration
18
Copyright © 2005 Altera Corporation
EP1C3 Device FloorplanEP1C3 Device Floorplan
EP1C3
PLL
M4K RAM Block
Logic Array
IOEs
19
Copyright © 2005 Altera Corporation
EP1C20 Device FloorplanEP1C20 Device FloorplanEP1C20
Phase-Locked Loops (PLLs)
Logic Array
M4K RAM Block
Bottom IOEs: LVDS & DDR
Top IOEs: LVDS & DDR
Side IOEs: LVDS, DDR
& PCI
Side I/O Elements (IOEs): LVDS,
DDR & PCI
20
Copyright © 2005 Altera Corporation
EP2C35 Cyclone II FloorplanEP2C35 Cyclone II Floorplan
Logic Elements
PLLs
M4K Blocks
Embedded Multipliers
Column I/O
Row I/O
21
Copyright © 2005 Altera Corporation
Parameter
Device FamilyCyclone II
AdvantagesCyclone Cyclone II
Core Voltage 1.5 V 1.2 V Lower Power
Process 130 nm 90 nm Lower Cost
Logic Density (LEs) 2,910 to 20,060 4,608 to 68,416 3X
I/O Pin Count 65 to 301 85 to 622 2X
Embedded Memory (M4K Blocks - 4Kbit)
13 to 64 26 to 250 4X
Memory Density (Bits)
60K to 295K 120K to 1,152K 4X
Relative Performance 1.0 1.0 Same
Lower Power
Architecture ComparisonArchitecture ComparisonArchitecture ComparisonArchitecture Comparison
Relative Standby Power Relative
Active Power
1.01.0
ParityLower
22
Copyright © 2005 Altera Corporation
ParameterDevice Family
Cyclone Cyclone II
DSP Implementation
Built with Logic ElementsUp to 150 18x18
Embedded Multipliers
PLLs per Device 1 to 2 2 to 4
I/O StandardsSingle Ended + Differential I/O
Same as Cyclone + 4 New Standards
External Memory Device Interfaces
SDR, DDR SDRAMSDR, DDR, DDR2 SDRAM
& QDR II SRAM
Feature ComparisonFeature ComparisonFeature ComparisonFeature Comparison
Bottom Line: Embedded Multipliers Capable of Running at 250 MHz 2x the PLLs for a Complete System Clock Management Solution 4 New I/O Standards (mini-LVDS, LVPECL, HSTL, PCI-X) 2 New External Memory Device Interfaces (DDR2, QDRII)
Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
Architecture – Logic StructureArchitecture – Logic Structure
24
Copyright © 2005 Altera Corporation
Architecture – Logic StructureArchitecture – Logic Structure
Cyclone Logic Array Blocks (LABs) & LEs Cyclone II LABs & LEs Interconnects (Routing)
25
Copyright © 2005 Altera Corporation
Cyclone/Cyclone II Logic ElementsCyclone/Cyclone II Logic Elements
Smallest Units of Logic Used for Combinatorial/Registered Logic Arranged in Groups Called LABs
26
Copyright © 2005 Altera Corporation
LAB ResourcesLAB Resources
DeviceLAB
RowsLAB
Columns
EP1C3 13 24
EP1C4 26 17
EP1C6 20 32
EP1C12 26 48
EP1C20 32 64
DeviceLAB
RowsLAB
Columns
EP2C5 24 13
EP2C8 30 18
EP2C20 46 26
EP2C35 60 35
EP2C50 74 43
EP2C70 86 50
27
Copyright © 2005 Altera Corporation
Total LE ResourcesTotal LE Resources
Device Total LEs
EP1C3 2,910
EP1C4 4,000
EP1C6 5,980
EP1C12 12,060
EP1C20 20,060
Device Total LEs
EP2C5 4,608
EP2C8 8,256
EP2C20 18,752
EP2C35 33,216
EP2C50 50,528
EP2C75 68,416
Cyclone Cyclone II
28
Copyright © 2005 Altera Corporation
Cyclone LABsCyclone LABs 10 LEs Local interconnect LAB-Wide Control
Signals
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE10
LE9
4
4
4
4
4
4
4
4
4
4
Control Signals
Lo
cal i
nte
rco
nn
ect
30 LAB input Lines
Carry & Register Chain
10 LE Feedback Lines
29
Copyright © 2005 Altera Corporation
LAB ArrangementLAB Arrangement LABs Communicate Directly to Each Other &
Other Blocks Both Horizontally & Vertically
LA
B
LA
B
LA
B
LA
B
LA
B
LA
B
LA
B
LA
B
LA
B
LA
B
M51
2
LA
B
LA
B
M51
2
LAB Row
LAB Column
LA
B
LA
B
LA
B
LA
B
30
Copyright © 2005 Altera Corporation
Cyclone LAB-Wide Control SignalsCyclone LAB-Wide Control Signals
10 Available LAB-Wide Signals 2 Clocks 2 Clock Enables (1 Per Clock) 2 Asynchronous Clears 1 Asynchronous Load or Preset 1 Synchronous Clear 1 Synchronous Load 1 Add/Subtract Control
31
Copyright © 2005 Altera Corporation
CLR2
CLR1ASYNCLOAD
/LABPRE
SYNCLOAD
CLK1
CLKENA1
LAB Row Clocks
Per Region
Local
interconnect
Local
interconnect
Local
interconnect
Local
interconnect
/8
LAB Control Signal Generation
CLK2
CLKENA2
SYNCCLR
ADDNSUB
Local
interconnect
Local
interconnect
32
Copyright © 2005 Altera Corporation
Control Signal DetailsControl Signal Details Clock & Clock Enables Are Linked
LABCLKENA1 Cannot Control LABCLK0
Clock Inversions Are Performed at the LAB 1 Global Clock Can Be Used for Rising & Falling
Edges Registers But Requires 2 LAB Clocks
Synchronous Load & Clear Affect All LAB LEs Other Registers Must Be Placed in Other Labs
33
Copyright © 2005 Altera Corporation
Cyclone LE Datasheet ImageCyclone LE Datasheet Image
34
Copyright © 2005 Altera Corporation
Cyclone LE FeaturesCyclone LE Features 4-Input Look-Up Table (LUT) Configurable Register 2 Operation Modes Dynamic Add/Subtract Control Carry-Select Chain Logic Performance-Enhancing Features
LUT & Register Chain
Area-Enhancing Features Register Packing & Feedback
35
Copyright © 2005 Altera Corporation
Cyclone LE Inputs/OutputsCyclone LE Inputs/Outputs Inputs
4 Data 2 LE Carry-Ins & 1 Lab Carry-In 1 Dynamic Addition/Subtraction Control Register Controls
Outputs 2 LE Carry-Outs 2 Row/Column/DirectLink Outputs 1 Local Output 1 LUT Chain & 1 Register Chain
36
Copyright © 2005 Altera Corporation
LE Register ControlsLE Register Controls Clock/Clock Enable Synchronous & Asynchronous Clear Synchronous & Asynchronous Load & Data Asynchronous Preset
Preset Function Loads a ‘1ALD/PRE
ADATA
D Q
ENACLRN
37
Copyright © 2005 Altera Corporation
Cyclone LE Operation ModesCyclone LE Operation Modes Normal
General Combinatorial or Registered Logic Dynamic Arithmetic
Used for Adders Counters Accumulators Comparators
Uses Carry Chain for Faster Operation Chosen Automatically by Quartus® II &
Nativelink® Synthesis tools Based On Design & Design Constraints
38
Copyright © 2005 Altera Corporation
Cyclone LE Normal ModeCyclone LE Normal Mode
data1
addnsub
data2
data34-input
LUT4-input
LUTcin
data4
Register Chain
RegReg
sload sclear aload
clockenaaclr
Row,Column & Direct Link Routing
Local Routing
LUT Chain
Register Chain
39
Copyright © 2005 Altera Corporation
Cyclone Dynamic Arithmetic ModeCyclone Dynamic Arithmetic Mode
Sync Load&
Clear Logic Reg
Two2-inputLUTs
(Carry)
Register Control Signals
Register Chain input
Data1
Data2
Data3
Row, Column& Direct LinkRouting
Local Routing
Two2-inputLUTs(Sum)
Register Chain Output
addnsub
Carry-OutLogic
Carry-inLogic
LAB Carry-inCarry-in0Carry-in1
Carry-Out1
Carry-Out0
40
Copyright © 2005 Altera Corporation
Cyclone Carry Chain DetailsCyclone Carry Chain Details
Carry Chains Begin & End in Any LE
2 Carry Chains Can Exist in Any LAB
Carry-Select Generated in LEs 5 & 10 Every LE Not in Critical
Timing Path
Le1
Le2
Le3
Le4
Sum1
Sum2
Sum3
Sum4
A1B1
A2B2
A3B3
A4B4 LE4
LE2
Le3
LE10 1LAB Carry-in
LE3
LE5 Sum5A5B5
LE6
LE7
LE8
0 1
LE9
LE10
Sum6
Sum7
Sum8
Sum9
Sum10
LAB Carry-out
A6B6
A7B7
A8B8
A9B9
A10B10
41
Copyright © 2005 Altera Corporation
LE1
LUT & Register ChainsLUT & Register Chains LUT Chain
Output of LUT Connects Directly to LUT Below
Available Only in Normal Mode Ex. Wide Fan-in Functions
Register Chain Output of Register Connects
Directly to Register Below (Shift Register)
LUT Can Be Used for Unrelated Function
Ex. LE Shift Register
Both Chains End at LAB Boundary
Lut D Q
LE2D Q
Les 3 - 10
LUT Chain
Register Chain
Lut
42
Copyright © 2005 Altera Corporation
Register Packing & FeedbackRegister Packing & Feedback Register Packing
LUT & Register Drive Different Outputs Normal Mode Only Ex. State Machines
Register Feedback Register Output Feeds Its Own LUT
LeLUT D Q
LeLUT D Q
Register Packing Register Feedback
43
Copyright © 2005 Altera Corporation
Controlling Register PackingControlling Register Packing
Settings Affect Both Register Packing & Register Feedback OFF: No Packing Except Registers Packed by Another EDA tool Normal (Default): Register Packing Used with No Decrease in fmax Minimize Area: Aggressive Register Packing: May Decrease fmax Minimize Area with Chains: Aggressive Packing of Functions that Are Part
of Arithmetic or Register Cascade Chains.
Auto Packed Registers
Quartus II Assignment Editor
44
Copyright © 2005 Altera Corporation
Cyclone II LABsCyclone II LABs 16 LEs Local interconnect LAB-Wide Control
Signals
Control Signals
38 LAB Input Lines
LE14
4
4
4
4
4
4
4
4
4
Lo
cal I
nte
rco
nn
ect
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE11
LE12
LE13
LE14
LE15
LE16
4
4
4
4
4
4
Carry & Register Chain
16 LE Feedback Lines
45
Copyright © 2005 Altera Corporation
Cyclone II LAB-Wide Control SignalsCyclone II LAB-Wide Control Signals
8 Available LAB-Wide Signals 2 Clocks 2 Clock Enables (1 Per Clock) 2 Asynchronous Clears 1 Synchronous Clear 1 Synchronous Load
46
Copyright © 2005 Altera Corporation
LAB Row Clocks
Local
interconnect
Local
interconnect
Local
interconnect
Local
interconnect
6
LAB Control Signal Generation
CLR1
CLK2
CLKENA1 CLKENA2
CLK1 CLR2SYNCLOAD
SYNCCLR
Same Restrictions as Cyclone
47
Copyright © 2005 Altera Corporation
Cyclone II LE DiagramCyclone II LE Diagram
48
Copyright © 2005 Altera Corporation
Cyclone II LE FeaturesCyclone II LE Features
Two Modes Normal Arithmetic
Carry Chains Ripple Carry, Not Carry-Select Like Cyclone
Register Packing Register Feedback Register Chains
49
Copyright © 2005 Altera Corporation
Cyclone II LE Normal ModeCyclone II LE Normal Mode
data1
data2
data34-input
LUT4-input
LUTcin
data4
Register Chain
RegReg
sload (LAB-Wide)
sclear (LAB-Wide)
aclr (LAB-Wide)
Row,Column & Direct Link Routing
Local Routing
Register Chain
clock (LAB-Wide)
ena (LAB-Wide)
Register Feedback
50
Copyright © 2005 Altera Corporation
Cyclone II LE Arithmetic ModeCyclone II LE Arithmetic Mode
data1data2
3-inputLUT
3-inputLUT
cin
Register Chain
sload (LAB-Wide)
sclear (LAB-Wide)
Row,Column & Direct Link Routing
Local Routing
Register Chain
Register Feedback
3-inputLUT
3-inputLUT
RegReg
aclr (LAB-Wide)
clock (LAB-Wide)
ena (LAB-Wide)
cout
51
Copyright © 2005 Altera Corporation
Cyclone II LE Carry ChainsCyclone II LE Carry Chains
Connected Vertically LE16 to LE1 in LAB Below
Ripple Carry Implementation
52
Copyright © 2005 Altera Corporation
Register Packing & FeedbackRegister Packing & Feedback Register Packing
LUT & Register Drive Different Outputs
Normal Mode Only Ex. State Machines
Register Feedback Register Output Feeds Its Own LUT Ex. Registered Inputs on IP/Sublevels
Register Chain Register Output Feeds Register Input
Below Ends at LAB Boundary Ex. Shift Registers
Register Packing
LELUT D Q
Register Feedback
LELUT D Q
LE1LUT D Q
LE2D QLUT
Register Chain
53
Copyright © 2005 Altera Corporation
Interconnects (Routing)Interconnects (Routing) Interconnects to Route Between All Device
Blocks Horizontal Interconnects
DirectLink R4 R24
Vertical Interconnects Carry, LUT, Register Chains C4 C16
54
Copyright © 2005 Altera Corporation
DirectLinkDirectLink Allows Blocks to Drive Local Interconnects of
Neighboring Blocks in the Same Row
Lo
cal I
nte
rco
nn
ectLE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE10
LE9
Lo
cal I
nte
rco
nn
ect
Lo
cal I
nte
rco
nn
ect
M4K
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE10
LE9
55
Copyright © 2005 Altera Corporation
DirectLink (cont.)DirectLink (cont.)
Provides Fast Communication between Neighboring Blocks One LE Has Fast Access to Up to 30
(Cyclone) or 48 (Cyclone II) LEs in Area Saves Row Resources
56
Copyright © 2005 Altera Corporation
Row & Column InterconnectsRow & Column Interconnects 2 Sizes of Row & Column Lines
R4 & 24 C4 & C16
Each Block Has Own R4/C4 Resources to Drive in All Directions
R24/C16 Do Not Interface Directly with Blocks
R4
R24
C4
C16
57
Copyright © 2005 Altera Corporation
58
Copyright © 2005 Altera Corporation
Interconnect DetailsInterconnect Details
Staggered Interconnects End-to-End Connections for Longer Routes
LAB-Neighboring LABs Can Use Interconnects from Neighboring
LABs
Proximity is Key to Logic Performance in Cyclone & Cyclone II
59
Copyright © 2005 Altera Corporation
DirectDrive™ TechnologyDirectDrive™ Technology Each Interconnect
Line Driven by Single Source Consistent Access to
Routing Eliminates Congestion
Uniform Routing Resources Across Device Ensures Blocks Can be
Moved within or between Designs
60
Copyright © 2005 Altera Corporation
Cyclone Series ComparisonCyclone Series ComparisonCyclone Series ComparisonCyclone Series Comparison
Parameter / Resource
Device Family
Cyclone Cyclone II
Logic Density (LEs)
3,000 to 20,000 4,500 to 68,000
LAB-Wide Control Signals
10 LAB-Wide Signals (+ Async. Load/Preset &
ADDnSUB)8 LAB-Wide Signals
LE Control Signals6 Per LE
(+ Async. Load/Preset)5 Per LE
LUT Chain Yes No
InterconnectsR4C4
R4/R24C4/C16
Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
Architecture – PLLs & Clock GenerationArchitecture – PLLs & Clock Generation
62
Copyright © 2005 Altera Corporation
PLLs & Clock GenerationPLLs & Clock Generation
Global Clocking Resources Clock Control Block PLLs
63
Copyright © 2005 Altera Corporation
Global Clocking ResourcesGlobal Clocking Resources
Clock Nets Dedicated Clock Pins Dual-Purpose Pins
64
Copyright © 2005 Altera Corporation
Global Clock NetworkGlobal Clock Network
Availability 8 Global Clocks
All Cyclone EP2C5 & EP2C8
16 Global Clocks EP2C20 & Larger
Provide Clocks for All Device Blocks Use for High-Fan Out Control/Data Signals
Cyclone Device
Global Clock Network [n..0]
n = 7 or 15
65
Copyright © 2005 Altera Corporation
Dedicated Clock PinsDedicated Clock Pins Uses
High Fan-Out Control Signals CLK, ENA, ACLR & SCLR
High Fan-Out Data PLL Inputs
Availability 4 (All Cyclone)
2 on Left & Right 8 (EP2C5, EP2C8)
4 on Left & Right 16 (EP2C20 & Larger)
4 on each Side
66
Copyright © 2005 Altera Corporation
Dual-Purpose Clock PinsDual-Purpose Clock Pins Uses
High Fan-Out Control Signals CLK, ENA, ACLR & SCLR
DQS of DDR Memory Interface TRDY/IRDY for PCI Interface High Fan-Out Data
Availability 8 (All Cyclone, EP2C5 & EP2C8)
2 on each Side 20 (EP2C20 & Larger)
4 on Left & Right 6 on Top & Bottom
67
Copyright © 2005 Altera Corporation
Global Clock Control BlockGlobal Clock Control Block
Provides Input to Global Clocks Nets One Per Global Clock Static Controls (Cyclone & Cyclone II)
Clock Selection Clock Enable/Disable
Dynamic Controls (Cyclone II Only) Clock Selection Clock Enable/Disable
1 PLL Output
1 Dedicated Clock Input
1 Dual-Purpose Clock Input
Internal Logic
Cyclone Static Clock Selection
GCLK[n]
68
Copyright © 2005 Altera Corporation
Cyclone II Control BlockCyclone II Control Block
Dedicated Clock Input Pins
PLL Outputs
4 2
2
Static Clock Selection
GCLK[n]
Dynamic Clock Selection
3
1 Dual-Purpose Clock Pin
Internal Logic
Internal Logic
Static Clock Selection
Clock Control Block
2
Clock Select[1..0](1)
Note:1) May be driven by internal logic or pin
69
Copyright © 2005 Altera Corporation
ALTCLKCTRL MegafunctionALTCLKCTRL Megafunction
Use for Dynamic Internal & External Clock Controls
70
Copyright © 2005 Altera Corporation
Cyclone & Cyclone II PLL FeaturesCyclone & Cyclone II PLL Features
General-Purpose Multiplication & Division Three Output Frequencies
Cyclone: 2 Internal & 1 External Cyclone II: 3 Internal & 1 External
Three Operation Modes Single-Ended & Differential Inputs Single-Ended & Differential External Output
71
Copyright © 2005 Altera Corporation
PLL Features (Cont.)PLL Features (Cont.) Phase Shifting
Uses VCO & Output Counters (No Delay Elements)
Programmable Duty Cycle Lock Detect Signal
Indicates a Stable Output in Phase with Reference Clock
PLLENABLE, ARESET, & PFDENA Control Signals
72
Copyright © 2005 Altera Corporation
Cyclone II PLL Additional FeaturesCyclone II PLL Additional Features
Clock Switchover Manual Switchover (No Automatic Circuitry) Use CLKSWITCH Port to Select PLL Input
Programmable Bandwidth Low Bandwidth Filters Jitter High Bandwidth Locks Faster
Gated Lock User Specifies Number of Clock Cycles Before
Valid Lock Signal
73
Copyright © 2005 Altera Corporation
PLL Clock Feedback ModesPLL Clock Feedback Modes No Compensation
PLL Input Clock Aligned with PLL Output Clock
“B” in Phase with “C” Normal
Clock Edge at Input Pin Aligned with Clock Edge at LE Register
“A” in Phase with “D” Zero-Delay Buffer
Clock Edge at Input Pin Aligned with Clock Edge at External Output Clock Pin
“A” in Phase with “F”
PLLinput Delay
FPGA Clock Tree
(internal)
Output Delay
A BC
D
F
Input Pin
Output Pin
LE Register
74
Copyright © 2005 Altera Corporation
Cyclone PLLCyclone PLL
CP/LFCP/LF VCOVCO
MMEE
CLK1 or LVDSCLK1n
G0G0
G1G1
VCO PhaseSelection
Post-ScaleCounter
GlobalClockNetworkNN
I/O BufferΔtΔt
ΔtΔt
CLK0 or LVDSCLK1p
8
8fVCO
To Logic or I/O
Lock DetectLock
Detect
PFDPFD
75
Copyright © 2005 Altera Corporation
Cyclone PLL Specifications Cyclone PLL Specifications
Feature Description
PLL Output Taps Up to 12 Output Frequencies Per Device
Off-Chip Output Clocks 2 Single-Ended / 2 Differential
Frequency RangeInput: 15.625 to 156 MHzOutput (Internal) : 10 to 312 MHzOutput (External): 15.625 to 320 MHz
VCO Frequency Range 500 MHz to 1 GHz
Input Frequency Jitter ± 200 ps
Multiplication/Division M : 2 to 32
N, K (G or E) : 1 to 32
Output Frequency Jitter ± 300 ps
Programmable Phase Adjustable in Steps as Small as 125 ps
Lock Time 10 - 100 µs
Control Signals PFDENA, ARESET, PLLENA
KNM
inout ff *
76
Copyright © 2005 Altera Corporation
Cyclone II PLL Cyclone II PLL
77
Copyright © 2005 Altera Corporation
Cyclone II PLL Clock InputsCyclone II PLL Clock Inputs
DevicePLL1 PLL2 PLL3 PLL4
CLK0 CLK1
CLK2 CLK3
CLK4 CLK5
CLK6 CLK7
CLK8 CLK9
CLK10 CLK11
CLK12 CLK13
CLK14 CLK15
EP2C5
EP2C8
EP2C20
EP2C35
EP2C50
EP2C70
78
Copyright © 2005 Altera Corporation
Cyclone II PLL Feature SummaryCyclone II PLL Feature Summary
Feature Description
PLL Output Taps Up to 12 Output Frequencies Per Device
Off-Chip Output Clocks 4 Single-Ended / 4 Differential
Frequency RangeInput: 10 to 311 MHzOutput (Internal) : 10 to 402.5 MHzOutput (External): 10 to 200 MHz
VCO Frequency Range 300 MHz to 1 GHz
Multiplication/Division M, C : 1 to 32
N : 1 to 4
Programmable Phase Adjustable in Steps as Small as 125 ps
Lock Time 1 ms (Maximum)
Control Signals PFDENA, ARESET, PLLENA
CNM
inout ff *
Note:1) All values pending characterization
79
Copyright © 2005 Altera Corporation
Cyclone PLL/Clock LayoutCyclone PLL/Clock Layout
PLL2PLL1
Global Clocks
8
8
4 Clock Control Blocks
44
DPCLK
DPCLK
DPCLK
DPCLK
DPCLK
DPCLK
DPCLK
DPCLK
CLK2 2
CLK
Notes:1) EP1C3 has only PLL12) Functional Diagram
(1)
80
Copyright © 2005 Altera Corporation
Cyclone II PLL/Clock LayoutCyclone II PLL/Clock Layout
PLL1
PLL2
DPCLK
DPCLK
CLK
DPCLK
DPCLK
CLK
DPCLKDPCLK
DPCLK DPCLK
4 Clock Control Blocks
4 4
EP2C5 & EP2C8
Global Clocks
Note:1) Functional Diagram
8
8 44
81
Copyright © 2005 Altera Corporation
Cyclone II PLL/Clock LayoutCyclone II PLL/Clock LayoutEP2C20EP2C35EP2C50EP2C70
CDPCLKCDPCLK
PLL1
PLL2
DPCLK
DPCLK
CLK
DPCLK
DPCLK
CLK
CDPCLK CDPCLK
4 Clock Control Blocks
16
164 4
Global Clocks
PLL3
PLL4
CDPCLK
CDPCLKCDPCLK
4
4
CDPCLK
DPCLKDPCLKCLK
DPCLKDPCLKCLK
Note:1) Functional Diagram2) Only 1 CDPCLK can feed the
clock control block at one time. The other will be general purpose I/O
22
22
44
4
4
(2)
82
Copyright © 2005 Altera Corporation
EP1C3 100-Pin TQFP ExeptionsEP1C3 100-Pin TQFP Exeptions
2 Dedicated Clock Input Pins 1 on Left & Right Sides
5 Total Dual-Purpose Pins No External Clock Output No LVDS Input
83
Copyright © 2005 Altera Corporation
ALTPLL MegafunctionALTPLL Megafunction
84
Copyright © 2005 Altera Corporation
ALTPLL (cont.)ALTPLL (cont.)
Clock Switchover
85
Copyright © 2005 Altera Corporation
ALTPLL (cont.)ALTPLL (cont.)
Set Output Frequency
Set Phase Shift
Set Duty Cycle
86
Copyright © 2005 Altera Corporation
Cyclone Series ComparisonCyclone Series ComparisonCyclone Series ComparisonCyclone Series ComparisonParameter / Resource
Device Family
Cyclone Cyclone II
Global Clock Nets Up to 8 Up to 16
Clock Input Pins Up to 4 Up to 16
Dual-Purpose Pins Up to 8 Up to 20
Dynamic Clock Control
No Yes
PLLs Up to 2 Up to 4
PLL Locations Left/Right Sides Corners
PLL Outputs3 Output Frequencies
(2 Internal & 1 External)3 Output Frequencies
(3 Internal & 1 External)
PLL FeaturesPhase Shifting, Lock
Detect & Programmable Duty Cycle
Cyclone Features + Manual Switchover,
Programmable Bandwidth & Gated Lock
Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
Embedded MemoryEmbedded Memory
88
Copyright © 2005 Altera Corporation
M4K Embedded MemoryM4K Embedded Memory
Up to 5 Columns of M4K Blocks
DeviceM4K
ColumnsTotal
BlocksTotal Bits
EP1C3 1 13 59,904
EP1C4 1 17 78,336
EP1C6 2 20 92,160
EP1C12 3 52 239,616
EP1C20 5 64 294,912
CycloneDevice
M4K Columns
Total Blocks
Total Bits
EP2C5 2 26 119,808
EP2C8 2 36 165,888
EP2C20 2 52 239,616
EP2C35 3 105 483,840
EP2C50 3 129 594,432
EP2C70 5 250 1,152,000
Cyclone II
250 MHz250 MHz
89
Copyright © 2005 Altera Corporation
Features 4608 Bits Per Block 9 Configurable Sizes 4 Clocking Modes Synchronous Inputs
Optional Output Registers Parity Bit Support Mixed Width Capability Byte Enable Support Address Clock Enable
Cyclone II Only Memory Initialization
M4K BlocksM4K Blocks Modes True Dual-Port RAM Simple Dual-Port RAM Single-Port RAM FIFO ROM Shift Register Mode
90
Copyright © 2005 Altera Corporation
RAM Block with Write Enable Disabled
Data Embedded in Configuration File Loaded (Initialized) at
Configuration Time
ROMROM
address[ ]
clockinclocken
q[ ]
ROM
91
Copyright © 2005 Altera Corporation
One Address Port for Reading & Writing
Clocking Options Single Clock Input/Output Clock Mode
Single-Port RAMSingle-Port RAM
wren
address[ ]data[ ]
inclockinclocken
q[ ]
outclockoutclocken
inaclr outaclr
Single-Port RAM
92
Copyright © 2005 Altera Corporation
Two Address Inputs One Read Address One Write Address
Mixed Width Capability Clocking Options
Single Clock Input/Output Clock Mode Read/Write Clock Mode
Simple Dual-Port RAMSimple Dual-Port RAM
wren
wraddress[ ]data[ ]
inclockinclocken
rdaddress[ ]
rdenq[ ]
outclockoutclocken
inaclr outaclr
Simple Dual-Port RAM
93
Copyright © 2005 Altera Corporation
Two Address Inputs Port A & Port B Supports Two
Simultaneous Reads or Writes
Mixed Width Capability Clocking Options
Input/Output Clock Mode Independent Clock Mode
True Dual-Port RAMTrue Dual-Port RAM
A BwrenA
addressA[ ]
dataA[ ]
qA[ ]
clockA
wrenB
addressB[ ]
dataB[ ]
qB[ ]
clockB
clockenA clockenB
aclrBaclrA
True Dual-Port RAM
94
Copyright © 2005 Altera Corporation
First-In First-Out Memory Ideal for Rate Changing
Clocking Options Single Clock Read/Write Clock Mode
FIFOFIFO
95
Copyright © 2005 Altera Corporation
M4K Blocks Support W x M x N Shift Register W = Bus Width M = Length of Each Tap N = Number of Taps
Multiple Blocks Used Automatically when W*N > 36 W*M*N > 4608
Memory Outputs Feed Datain
Shift RegisterShift Register
96
Copyright © 2005 Altera Corporation
Nine Configuration SizesNine Configuration Sizes
4K x 1 2K x 2 1K x 4 512 x 8/9 256 x 16/18 128 x 32/36
97
Copyright © 2005 Altera Corporation
M4K Simple Dual-PortM4K Simple Dual-PortReadPort
Write Port
4Kx1 2Kx2 1Kx4 512x8 256x16 128x32 512x9
4Kx1
2Kx2
1Kx4
512x8
256x16
128x32
512x9
256x18
128x36
256x18 128x36
98
Copyright © 2005 Altera Corporation
M4K True Dual-PortM4K True Dual-Port
Port A Port B
4Kx1 2Kx2 1Kx4 512x8 256x16 512x9 256x18
4Kx1
2Kx2
1Kx4
512x8
256x16
512x9
256x18
99
Copyright © 2005 Altera Corporation
Clocking ModesClocking Modes
Clocking ModeTrue-Dual Port Mode
Simple Dual-Port Mode
Single-Port Mode
Independent
Input/Output
Read/Write
Single
100
Copyright © 2005 Altera Corporation
All Inputs Registered Self-Timed Write Enable (WREN) Strobe
Generated Automatically Alleviates Memory Setup/Hold Time Design Worry Memory Write Occurs during Falling Edge of Clock
Optional Output Registers Fully Pipelined Memory
Synchronous ImplementationSynchronous Implementation
101
Copyright © 2005 Altera Corporation
True Asynchronous Memory Not Supported Neither Input nor Output Is Registered Generate Write Enable while Meeting Data & Address
Setup & Hold Times
Pseudo-Asynchronous Implementation Supported in Dual-Port Modes Use Negative-Edge Clock for Read Address & Enable Bypass Output Registers
Pseudo-Asynchronous ModePseudo-Asynchronous Mode
102
Copyright © 2005 Altera Corporation
Single Address Read & WriteSingle Address Read & Write
New Data Available on Rising Edge of Same Clock (Flow-Through) Single-Port True Dual-Port
Same Port (e.g. Write A while Read A) Masked Bytes Are Unknown
Old Data Output Simple Dual-Port (Single Clock) True Dual-Port (Single Clock)
Mixed Ports (e.g. Write A while Read B)
Unsupported with Multi-Clock Configurations
103
Copyright © 2005 Altera Corporation
ParityParity Supported by All Blocks Data Sizes Provide for 1 Extra Bit Per byte
(4608 bits = 4096 + 512) 512 x 9 256 x 18 128 x 36
Create Custom Logic to Check/Generate Bits Use for Control Bits Also
104
Copyright © 2005 Altera Corporation
Partition Single M4K into Two Independent 2K Memory Blocks Supported for Single-Ports Only Features independently Defined Widths Increase Memory Utilization Configured As True Dual-Port with MSB High or Low
M4K Block Memory PackingM4K Block Memory Packing
LOGIC
LOGIC
LOGIC
LOGIC 128 X 16
256 X 4
105
Copyright © 2005 Altera Corporation
Address Clock Enable (addressstall)Address Clock Enable (addressstall)
Holds Previous Address Available on Each Address Input Example Use : Cache Memory
RegReg
1
0addressA[n..0]
addressstallAddress Registers
clock
MemoryMemory
Cyclone II Only
106
Copyright © 2005 Altera Corporation
M4K InterfaceM4K Interface
datain
clocks
control signals
address
dataout
C4 C4
R4
DirectLink
DirectLink DirectLink
LAB Row Clocks
Local interconnect
M4K RAM Block
byte enable
6
107
Copyright © 2005 Altera Corporation
Use for All Memory Functions
Memory Compiler MegaWizardMemory Compiler MegaWizard
108
Copyright © 2005 Altera Corporation
Ex. Dual-Port RAMEx. Dual-Port RAMSimple or True Dual-Port
Memory SizeMixed Width?
implementation
109
Copyright © 2005 Altera Corporation
Ex. Dual-Port RAMEx. Dual-Port RAM
110
Copyright © 2005 Altera Corporation
NativeLink™ EDA Tools Support RAM inference Check Documentation for Various Implementations
always@(posedge mem_clk) PROCESS (inclock) begin
begin IF rising_edge(inclock) then
addr_reg <= addr; address_reg <= address;
IF (we = '1') then
if (we) begin mem(conv_integer(address)) <= data;
mem[addr]<=din; END IF;
end END IF;
assign dout=mem[addr_reg]; END PROCESS;
q <= mem(conv_integer(address_reg));
Traditional Black Box Flow Use the MegaWizard to Generate the Wrapper Black Box in the 3rd Party tool
Verilog/VHDL RAM GuidelinesVerilog/VHDL RAM Guidelines
111
Copyright © 2005 Altera Corporation
Memory Control SignalsMemory Control Signals
Cyclone Independent Clock Enables for Each Clock Asynchronous Clear on All Registers
Individually Configurable
Cyclone II Clock Enable Input Disables Clock to Entire
Memory Asynchronous Clear on Output Registers
112
Copyright © 2005 Altera Corporation
Cyclone Series ComparisonCyclone Series ComparisonCyclone Series ComparisonCyclone Series Comparison
Parameter / Resource
Device Family
Cyclone Cyclone II
Memory Features
Parity Bit
Byte Enable
Mixed Width
Mixed Clocking
Initialization
Memory Packing
All Cyclone +
Address Clock Enable
Performance 250 MHz 250 MHz
Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
Cyclone II Embedded MultiipliersCyclone II Embedded Multiipliers
114
Copyright © 2005 Altera Corporation
Cyclone II Embedded MultipliersCyclone II Embedded Multipliers Complete Hardware
Multipliers Optimized for Cost-
Effective DSP Operations No Additional Arithmetic
Logic
Up to 3 Columns of Embedded Multipliers
250 MHz Performance Fully Pipelined
Device Embedded Multiplier Columns
Total Embedded Multipliers
EP2C5 1 13
EP2C8 1 18
EP2C20 1 26
EP2C35 1 35
EP2C50 2 86
EP2C70 3 150
115
Copyright © 2005 Altera Corporation
Embedded Multiplier FeaturesEmbedded Multiplier Features
2 Modes One 18 x 18 Multiplier Two 9 x 9 Multipliers
Full Precision Outputs Dedicated Input & Output Registers Dynamic Signed & Unsigned Support
1 = Signed; 0 = Unsigned
116
Copyright © 2005 Altera Corporation
9 x 9 Multiplication9 x 9 Multiplication
Data Out[17..0]RegReg
Data A[8..0] RegReg
RegReg
XX 18
9
9
Data B[8..0]
9 x 9
Data Out[35..18]RegReg
Data A[17..9] RegReg
RegReg
XX 18
9
9
Data B[17..9]
9 x 9
signasignb
aclrclk
ena
117
Copyright © 2005 Altera Corporation
Embedded Multiplier InterfaceEmbedded Multiplier Interface
Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
Input/OutputInput/Output
119
Copyright © 2005 Altera Corporation
Input/OutputInput/Output
I/O Banks I/O Blocks I/O Elements & Features DDR Interface High-Speed Differential Interface
120
Copyright © 2005 Altera Corporation
I/O BanksI/O Banks
43
2
1
5
6
78
2
3
4
1
Cyclone, EP2C5 & EP2C8 EP2C20 & Larger
121
Copyright © 2005 Altera Corporation
I/O BanksI/O Banks
Have Separate VCCIO Can Support Different I/O Standard Can Support Multiple Standards with Same
VCCIO Have Dual-Purpose VREF
Unused VREF Pins Available as User I/O
122
Copyright © 2005 Altera Corporation
I/O BlocksI/O Blocks Grouping of I/O Elements (IOEs) Share Local Interconnect
Provides Data & Control Row I/O Blocks
Cyclone: Up to 5 IOEs Cyclone II: Up to 3 IOEs
Column I/O Blocks Cyclone: Up to 3 IOEs Cyclone II: Up to 4 IOEs
123
Copyright © 2005 Altera Corporation
Row I/O Block InterfaceRow I/O Block Interface
Row I/O
Block
Row I/O
Block
I/O CLK[5..0]
C4
R4
DirectLink
(1)
Local Interconnect
Note:1) 35 (Cyclone) or 21 (Cyclone II)2) 10 (Cyclone) or 6 (Cyclone II)
(2)
Row Pins:Up to 5 (Cyclone)Up to 3 (Cyclone II)
124
Copyright © 2005 Altera Corporation
Column I/O BlockColumn I/O Block
Column I/O Block InterfaceColumn I/O Block Interface
I/O CLK[5..0]
C4
R4
(1)
Local Interconnect
Note:1) 21 (Cyclone) or 28 (Cyclone II)2) 6 (Cyclone) or 8 (Cyclone II)
Column Pins:Up to 3 (Cyclone)Up to 4 (Cyclone II)
C4
(2)
125
Copyright © 2005 Altera Corporation
I/O Element StructureI/O Element Structure
to/from CoreOUT
in
OE
VCCIO
tt
tt
tt
ProgrammablePull-Up Resistor
Bus-HoldCircuit
VCCIO
PCI ClampDiode
126
Copyright © 2005 Altera Corporation
I/O FeaturesI/O Features Differential & Single-Ended I/O Standards Programmable Output Drive Strength Slew-Rate Control Bus-Hold Circuitry Weak Pull-Ups during Configuration Programmable Pull-Up Resistors Programmable Input & Output Delays Series On-Chip Termination
Cyclone II Only
127
Copyright © 2005 Altera Corporation
IOE Control SignalIOE Control Signal
128
Copyright © 2005 Altera Corporation
Cyclone I/O Standard SupportCyclone I/O Standard Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS PCI LVDS SSTL-3 Class I & II SSTL-2 Class I & II Differential SSTL-2
See Cyclone Handbook for I/O Bank Support
129
Copyright © 2005 Altera Corporation
Cyclone II I/O Standard SupportCyclone II I/O Standard Support 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS PCI/PCI-X LVDS mini-LVDS RSDS LVPECL
SSTL-2 Class I & II SSTL-18 Class I & II HSTL-18 Class I & II HSTL-15 Class I & II “Pseudo”-Differential
SSTL-2 Class I & II “Pseudo”- Differential
SSTL-18 Class I & II “Pseudo”- Differential
HSTL-18 Class I & II “Pseudo”- Differential
HSTL-15 Class I & IISee Cyclone II Handbook for I/O Bank Support
130
Copyright © 2005 Altera Corporation
Cyclone Programmable Drive StrengthCyclone Programmable Drive Strength
I/O Standard IOH/IOL CurrentStrength Setting (mA)
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL (2.5 V)
LVTTL (1.8 V)
LVTLL (1.5 V)
4, 8, 12, 16, or 24
2, 4, 8, or 12
2, 8, 12, or 16
2, 8, or 12
2, 4, or 8
131
Copyright © 2005 Altera Corporation
Cyclone II Programmable Drive StrengthCyclone II Programmable Drive Strength
I/O Standard
Cyclone II
IOH/IOL CurrentStrength Setting (mA)
LVTTL/LVCMOS (3.3 V) 4, 8, 12, 16, 20, 24
LVTTL/LVCMOS (2.5 V) 4, 8, 12, 16
LVTTL/LVCMOS (1.8 V) 2, 4, 6, 8, 10, 12
LVCMOS 1.5 V 2, 4, 6, 8
SSTL-2 Class I 8, 12
SSTL-2 Class II 16, 20, 24
SSTL-18 Class I 4, 6, 8, 10, 12
SSTL-18 Class II 8, 16, 18
HSTL-18 Class I 4, 6, 8, 10, 12
HSTL-18 Class II 16, 18, 20
HSTL-15 Class I 4, 6, 8, 10, 12
HSTL-15 Class II 16
132
Copyright © 2005 Altera Corporation
Cyclone II Series OCTCyclone II Series OCT Series On-Chip Termination Supported
Driver Impedance & Series Termination Implementation Uses Programmable Drive Strength
Feature
Supported Standards 50 Ω Resistance
2.5- & 1.8-V LVCMOS/LVTTL SSTL-2 Class I & II SSTL-18 Class I
25 Ω Resistance 3.3-V LVCMOS/LVTTL
133
Copyright © 2005 Altera Corporation
Other I/O FeaturesOther I/O Features
PCI Support on Side I/O 64-Bit, 66-MHz PCI v2.2 64-Bit, 100-MHz PCI-X Mode 1
Cyclone II Only
Hot Socketing Support
134
Copyright © 2005 Altera Corporation
Multi-VoltMulti-Volt
VCCIOInput (Volts) Output (Volts)
1.5 1.8 2.5 3.3 5.0 1.5 1.8 2.5 3.3 5.0
1.5 V ╳ ╳(3) ╳(3) ╳(3) ╳
1.8 V ╳(6) ╳ ╳(3) ╳(3) ╳(4) ╳2.5 V ╳ ╳(3) ╳(4) ╳(4) ╳3.3 V ╳(5) ╳ ╳(2) ╳(4) ╳(4) ╳(4) ╳ ╳(1)
Notes:1) Cyclone Only; VCCIO of 3.3V exceed Vth for 5.0V LVTTL outputs; VCCIO of 3.3V does not
exceed Vth for 5.0 LVCMOS outputs; Supported on2) Cyclone Only; Requires external resistors & PCI diode turned on; Supported on 3) Must disable PCI clamping diode4) May drive devices (like Cyclone & Cyclone II) that tolerate inputs higher than VCCIO5) VCCIO supply current may be slightly higher than expected6) Cyclone II Only; VCCIO supply current may be slightly higher than expected
135
Copyright © 2005 Altera Corporation
External Memory SupportExternal Memory Support
Cyclone DDR SDRAM FCRAM
Cyclone II DDR SDRAM DDR2 SDRAM
Left/Right I/O Banks : Class I Termination Only
QDRII SRAMLeft/Right I/O Banks : Class I Termination Only
Up to 133 MHz
Up to 167 MHz
136
Copyright © 2005 Altera Corporation
DDR ImplementationDDR Implementation Data & Parity Bits
Up to 18 Pins for Data & Parity
DQS Pins Use Dual-Purpose Pins to Drive LE Registers
PLL Generate System & Shifted DQ Write Clock
Clock Delay Control Generate Shifted DQS Read Clock
DDR/QDR Pins
DQ Pins DQS Pins DQ Pins DM Pins
137
Copyright © 2005 Altera Corporation
DDR input interface DetailsDDR input interface Details
LEReg
Data from ExternalMemory Device
DQS DQ
Aligns DQS to Center of DQ (1)
Global Clock Multiplexer or Clock
Control Block
Global Clock
Network
LEReg
ΔtΔt
CaptureRegisters
LEReg
LEReg
SynchronizationRegisters/FIFO
Global Clock
A
B
•Registers implemented in LEs.
Note:1) Cyclone uses
programmable delay element & Cylcone II uses clock delay control circuitry
138
Copyright © 2005 Altera Corporation
DDR Output Interface DetailsDDR Output Interface Details
LEReg
Data to ExternalMemory Device
DQ
LERegPLL Phase shifted
1X Output
In-Phase1X Output
Global Clock
LEReg
LEReg
OutputEnable
A
B
LEReg
DQS
LEReg
LEReg
LEReg
OutputEnable
Vcc
Gnd
Phase shift of 72 degrees for FCRAM and 90 degrees for all others
139
Copyright © 2005 Altera Corporation
Cyclone II DDR EnhancementsCyclone II DDR Enhancements
DQS Postamble Circuitry
140
Copyright © 2005 Altera Corporation
DDR GroupsDDR Groups
Cyclone Up to 8 Groups in x8 Mode
Cyclone II Up to 14 Groups in x8 Mode Up to 8 Groups in x9, x16, or x18 Modes
141
Copyright © 2005 Altera Corporation
Differential Signaling SupportDifferential Signaling Support Up to 640-Mbps Performance Supported On All Sides of Device Requires Simple External Network Does Not include Dedicated SERDES or PLL
Cyclone Device Receiving Device
External Resistor Network
External Termination Resistor
142
Copyright © 2005 Altera Corporation
Cyclone II Additional SupportCyclone II Additional Support LVDS
Receiver : Up to 805 Mbps (402.5 MHz Clock) Transmitter : Up to 622 Mbps (311 MHz Clock)
RSDS & mini-LVDS : Up to 170 Mbps (85 MHz Clock)
LVPECL (Clock Input Only) : Up to 150 MHz Diff. HSTL & Diff. SSTL : Up to 167 MHz
143
Copyright © 2005 Altera Corporation
Cyclone LVDS SupportCyclone LVDS SupportDevice Number of
LVDS Channels
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Package
144-Pin TQFP
324-Pin FBGA
400-Pin FBGA
144-Pin TQFP
240-Pin PQFP
256-Pin FBGA
240-Pin PQFP
256-Pin FBGA
324-Pin FBGA
324-Pin FBGA
400-Pin FBGA
34
103
129
29
72
72
66
72
103
95
129
144
Copyright © 2005 Altera Corporation
Cyclone II LVDS SupportCyclone II LVDS SupportDevice
Device Package Number of LVDS Channels
EP2C5 144-Pin TQFP 33
208-Pin PQFP 58
EP2C8 144-Pin TQFP 31
208-Pin PQFP 55
256-Pin FBGA 77
EP2C20 256-Pin FBGA 56
484-Pin FBGA 132
EP2C35 484-Pin FBGA 135
672-Pin FBGA 205
EP2C50 484-Pin FBGA 122
672-Pin FBGA 193
EP2C70 672-Pin FBGA 164
896-Pin FBGA 261
145
Copyright © 2005 Altera Corporation
Parameter / Resource
Device Family
Cyclone Cyclone II
I/O Banks Up to 4 Up to 8
I/O Standard Support Differences
LVDS, RSDS, SSTL, PCI, LVTTL, LVCMOS
Same as Cyclone, Plus: HSTL, PCI-X, LVPECL
Programmable Drive Strength Support
LVTTL, LVCMOSLVTTL, LVCMOS, SSTL,
HSTL
On-Chip Termination
No Yes
External Memory Support
DDR, FCRAM DDR, DDR2, QDR II
DDR Memory Bit Widths
X8 X8, x9, x16, x18
Feature ComparisonFeature ComparisonFeature ComparisonFeature Comparison
Copyright © 2005 Altera Corporation
Designing with Cyclone & Cyclone II Devices
Designing with Cyclone & Cyclone II Devices
ConfigurationConfiguration
147
Copyright © 2005 Altera Corporation
ConfigurationConfiguration
SRAM Devices Require Configuration at Power-Up
Operating Modes Command Mode
Configuration Configuration Data Downloaded from Storage
Initialization Clears Registers Enables I/Os
User Mode
148
Copyright © 2005 Altera Corporation
Configuration SchemesConfiguration SchemesConfiguration
SchemeInterface Source MSEL Pins
1 0
Fast Active Serial
(Cyclone II Only)
Dedicated Configuration Pins
EPCS64 & EPCS16 Serial Configuration Devices
1 0
Active Serial (AS) Dedicated Configuration Pins
All Serial Configuration Devices (Cyclone/EPCS64 Not Supported)
0 0
Passive Serial Dedicated Configuration Pins
Enhanced Configuration Devices EPC2 & EPC1 Configuration
Devices Microprocessor (Intelligent Host) Download Cable
0 1
JTAG Dedicated JTAG Pins
Download Cable Microprocessor (Intelligent Host) JAM™ STAPL
N/A
149
Copyright © 2005 Altera Corporation
Fast Active Serial & Active Serial Fast Active Serial & Active Serial Configuration Data Stored in Low-Cost
Serial Configuration Devices FPGA Controls Configuration (Master)
Active Serial : Up to 20 MHz Fast Active Serial : Up to 40 MHz
Multi-Device Chain Supported First FPGA is Master (Active Mode) All Others Are Slaves (Passive Mode) Serial Configuration Devices Cannot Be
Chained
150
Copyright © 2005 Altera Corporation
Fast AS & AS DiagramFast AS & AS Diagram nCONFIG
Signals Start of Configuration
nSTATUS Indicates Configuration
Error CONF_DONE
Signals End of Configuration
DCLK DATA0/DATA
Configuration Data Input nCS0/nCS
Chip Select ASDI/ASDO
Sends Control Signals to Configuration Device
Note:1) Connect to 3.3-V Supply
151
Copyright © 2005 Altera Corporation
Serial Configuration DevicesSerial Configuration Devices Non-Volatile, Flash-Based Devices Four Variations
EPCS64, EPCS16, EPCS4 & EPCS1
Programming Options Download Cables JTAG Indirect Configuration Device Programming
(Serial Flash Loader) Next Slide
Altera Programming Unit (APU) Third-Party Programmers
152
Copyright © 2005 Altera Corporation
JTAG Indirect Configuration Device ProgrammingJTAG Indirect Configuration Device Programming
Cyclone or
Cyclone II
Cyclone or
Cyclone II
JTAG Device
JTAG
SPI
JTAG Device
EPCS4
Programs Serial Configuration Device via JTAG
Uses JIC File Generated by Quartus II
Procedure FPGA Device Configured with
JIC Image via JTAG Configuration Device is
Programmed with Application Image via Serial Interface
Upon Power-up, EP1C3 is Configured with Application Image in Configuration Device
153
Copyright © 2005 Altera Corporation
JIC Device Programming - User FlowJIC Device Programming - User Flow
Compile Design for Cyclone Device
Convert .sof to .jic
Create JTAG Chain
154
Copyright © 2005 Altera Corporation
Passive Serial ConfigurationPassive Serial Configuration Configuration Controlled by External Host
Enhanced Configuration Device Configuration Device (EPC2 or EPC1) Embedded Processor External Host (MAX or MAX II Device) PC Through Download Cable
Up to 100 MHz Configuration Clock Multi-Device Chain Supported
EPC2 & EPC1 Devices May Be Cascaded EPC16, EPC8 & EPC4 Devices Cannot Be Cascaded
155
Copyright © 2005 Altera Corporation
Passive Serial DiagramPassive Serial DiagramEnhanced Configuration Device
Embedded Processor or External Host
156
Copyright © 2005 Altera Corporation
Enhanced Configuration DeviceEnhanced Configuration Device Three Variations
EPC16, EPC8 & EPC4
Clocking Internal Oscillator
10, 33, 50 or 66 MHz
External Oscillator Up to 133 MHz
Programming Download Cable JTAG APU Third-Party Programmer
Store Multiple Pages (Images) for a Single FPGA
Program Up to 8 Devices in Parallel with Different Images
External Flash Interface
Enhanced Configuration
Device
Enhanced Configuration
Device
157
Copyright © 2005 Altera Corporation
JTAG ConfigurationJTAG Configuration JTAG Boundary Scan Testing & Programming
Supported JTAG Instructions Precede Any Device
Operating Modes No Output DCLK in AS or Fast AS Mode
Bypass Mode Allows Programming of Specific Devices in Chain
158
Copyright © 2005 Altera Corporation
JTAG Configuration DiagramJTAG Configuration Diagram
Notes:1) Connect to same supply voltage as download cable.2) These pins may be connected to support another
configuration mode. If no other mode is desired, then pull nCONFIG high, MSEL [1..0] low and DCLK & DATA0 either high or low.
159
Copyright © 2005 Altera Corporation
Data CompressionData Compression
Generate Compressed Configuration File in Quartus II Reduces Configuration File Size by 30-60%
Device Decompresses Data As It Is Received
Device-by-Device Basis in Multi-Device Chains
Not Available during JTAG Configuration
160
Copyright © 2005 Altera Corporation
Example Configuration TimesExample Configuration Times
Cyclone IIDevice
POF Sizein Bits
(Uncompressed)
POF Sizein Bits
(Compressed)
Approximate Configuration Times
Active Serial
(20 MHz)
Active Serial
(40 MHz)
Passive Serial
(100 MHz)
EP2C5 967,680 691,200 35 ms 17 ms 7 ms
EP2C8 1,755,648 1,254,034 63 ms 31 ms 13 ms
EP2C20 4,022,784 2,873,417 144 ms 72 ms 29 ms
EP2C35 7,147,008 5,105,006 255 ms 128 ms 51 ms
EP2C50 10,886,400 7,776,000 389 ms 194 ms 78 ms
EP2C70 14,750,208 10,535,863 527 ms 263 ms 105 ms
Note: All Values in Table Are Estimates & Subject to Change
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Programming FilesProgramming Files
Programming File
AS PS JTAG Comment
SOF Cable download using Altera programmer
POF Cable download or APU (Use to program configuration device which in turn configures Cyclone or Cyclone II at power-up)
RBF Microprocessor
HEX Microprocessor or 3rd-party programmers
JIC Cable download (JTAG indirect configuration uses JTAG and either AS or PS)
JAM/JBC Cable download, APU or microprocessor
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Cyclone Series ComparisonCyclone Series ComparisonCyclone Series ComparisonCyclone Series Comparison
Parameter / Resource
Device Family
Cyclone Cyclone II
Configuration Modes
Active Serial
Passive Serial
JTAG
Fast Active Serial
Active Serial
Passive Serial
JTAG
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Cyclone Handbook Cyclone II Handbook AN306: Implementing Multipliers in FPGA Devices AN311: ASIC-to-FPGA Design Methodology and Guidelines AN344: ASI Reference Design AN348: Interfacing DDR SDRAM with Cyclone Devices AN356: Serial Digital Interface Reference Design for Cyclone &
Stratix Devices AN357: Error Detection Using CRC in Altera Devices Reference Design: Cyclone DDR I/O Reference Design White Paper: SRunner - An Embedded Solution for Serial
Configuration Device Programming White Paper: Delivering RISC Processors in an FPGA for $2
LiteratureLiterature
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Instructor-Led Training
with Altera's instructor-led training courses, you can: Listen to a lecture from an Altera technical training engineer (instructor)
Complete hands-on exercises with guidance from an Altera instructor
Ask questions and receive real-time answers from an Altera instructor
Each instructor-led class is one day in length (8 working hours).
Learn More through Technical Training
On-Line Training
with Altera's on-line training courses, you can:
Take a course at any time that is convenient for you
Take a course from the comfort of your home or office (no need to travel as with instructor-led courses)
Each on-line course will take approximately 2-3 hours to complete.
www.altera.com/training
View Training Class Schedule & Register for a Class
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