![Page 1: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/1.jpg)
Crossbar switches
By Alejandro Ayala
![Page 2: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/2.jpg)
Hardware design
Show hardware design of several modern crossbar switches used for multiprocessing system on chip or
multicore design.
![Page 3: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/3.jpg)
AMD Opteron Architecture [1]
Integrated N.BridgeData & Command packets are separated
![Page 4: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/4.jpg)
Intel Xeon 7500 [2]
![Page 5: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/5.jpg)
Intel Xeon 7500 (cont)
8 port (each 80bit) Intel QuickPath Interconnect
communication
![Page 6: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/6.jpg)
UltraSPARC T2 [4]
pipeline crossbar High-bandwidth 8x9 xBar
Cores-Mem Cores-I/O
![Page 7: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/7.jpg)
UltraSparc T2 (cont)
Divided into two parts PCX CPX
PCX/CPX divided into two parts Arbiter
Assigns by old age Data slice
![Page 8: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/8.jpg)
Characteristics of the crossbar
Compare characteristics of several switches used in modern MPSoC design
Are the switches buffered or bufferless? Is buffering done at the input, output, or at each crosspoint? What is the size of the buffers? Why that much?
How is the crosspoint implemented? Are the crossbars pipelined? What is the size of the crossbar switch? What is the bandwidth?
![Page 9: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/9.jpg)
AMD Opteron [1]
Buffers at InputSize are allocated to optimize throughput
![Page 10: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/10.jpg)
System Request Queue (SRQ)
What is the System request queue in AMD64 Opteron,
Athlon X2?
![Page 11: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/11.jpg)
System Request Queue [1]
Prioritizes the access from both cores to use the crossbar.
Prevents contention to memory/resources
![Page 12: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/12.jpg)
Knockout switch
What is knockout switch?
![Page 13: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/13.jpg)
Knockout switch [3]
Problem: Fully connected switch (ie every input connects to
every output) Congestion at output – different input might want to
talk to same output. Solution:
Concentrator at output Buffer
![Page 14: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/14.jpg)
Knockout switch
Bus Interface
![Page 15: Crossbar switches By Alejandro Ayala. Hardware design Show hardware design of several modern crossbar switches used for multiprocessing system on chip](https://reader030.vdocument.in/reader030/viewer/2022032708/56649e7a5503460f94b7a052/html5/thumbnails/15.jpg)
References
[1] Pat Conway, Bill Hughes, "The AMD Opteron Northbridge Architecture," IEEE Micro, vol. 27, no. 2, pp. 10-21, Mar./Apr. 2007,doi:10.1109/MM.2007.43
[2] Intel Xeon Processor 7500 series Volume 2, Datasheet, March 2010
[3] Y. Yeh, M. Hluchyj, and A. Acampora, “The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching,” IEEE J. Selected Areas in Comm., vol. 5, no. 8, pp. 1274- 1287, Oct. 1987.
[4] U. G. Nawathe, et al.. “An 8-Core 64 Thread 64b Power-Efficient SPARC SoC,” in IEEE International Solid-State Circuits Conference
(ISSCC), Dig. Tech Papers, Feb. 2007, pp. 108-110.