Download - CS137: Electronic Design Automation
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CALTECH CS137 Fall2005 -- DeHon 1
CS137:Electronic Design Automation
Day 3: September 29, 2005
Clustering
(LUT Mapping, Delay)
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CALTECH CS137 Fall2005 -- DeHon 2
Today
• How do we map to LUTs?
• What happens when delay dominates?
• Lessons…– for non-LUTs– for delay-oriented partitioning
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CALTECH CS137 Fall2005 -- DeHon 3
LUT Mapping
• Problem: Map logic netlist to LUTs– minimizing area– minimizing delay
• Old problem?– Technology mapping? (last week)– Library approach require 22K gates in library
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CALTECH CS137 Fall2005 -- DeHon 4
Simplifying Structure
• K-LUT can implement any K-input function
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CALTECH CS137 Fall2005 -- DeHon 5
Cost Function
• Delay: number of LUTs in critical path– doesn’t say delay in LUTs or in wires– does assume uniform interconnect delay
• Area: number of LUTs– Assumes adequate interconnect to use
LUTs
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CALTECH CS137 Fall2005 -- DeHon 6
LUT Mapping
• NP-Hard in general
• Fanout-free -- can solve optimally given decomposition– (but which one?)
• Delay optimal mapping achievable in Polynomial time
• Area w/ fanout NP-complete
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CALTECH CS137 Fall2005 -- DeHon 7
Preliminaries
• What matters/makes this interesting?– Area / Delay target– Decomposition– Fanout
• replication• reconvergent
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CALTECH CS137 Fall2005 -- DeHon 8
Area vs. Delay
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CALTECH CS137 Fall2005 -- DeHon 9
Decomposition
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CALTECH CS137 Fall2005 -- DeHon 10
Decomposition
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CALTECH CS137 Fall2005 -- DeHon 11
Fanout: Replication
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CALTECH CS137 Fall2005 -- DeHon 12
Fanout: Replication
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CALTECH CS137 Fall2005 -- DeHon 13
Fanout: Reconvergence
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CALTECH CS137 Fall2005 -- DeHon 14
Fanout: Reconvergence
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CALTECH CS137 Fall2005 -- DeHon 15
Monotone Property
• Does cost function increase monotonicly as more of the graph is included? (do all subsets have property)– gate count?– I/o?
• Important?– How far back do we need to search?
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CALTECH CS137 Fall2005 -- DeHon 16
Delay
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CALTECH CS137 Fall2005 -- DeHon 17
Dynamic Programming
• Optimal covering of a logic cone is:– Minimum cost (all possible coverings)
• Evaluate costs of each node based on:– cover node– cones covering each fanin to node cover
• Evaluate node costs in topological order
• Key: are calculating optimal solutions to subproblems– only have to evaluate covering options at
each node
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CALTECH CS137 Fall2005 -- DeHon 18
Flowmap
• Key Idea:– LUT holds anything with K inputs– Use network flow to find cuts
logic can pack into LUT including reconvergence
• …allows replication
– Optimal depth arise from optimal depth solution to subproblems
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CALTECH CS137 Fall2005 -- DeHon 19
• Delay objective: – minimum height, K-feasible cut– I.e. cut no more than K edges– start by bounding fanin K
• Height of node will be:– height of predecessors or– one greater than height of predecessors
• Check shorter first
Flowmap
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CALTECH CS137 Fall2005 -- DeHon 20
Flowmap
• Construct flow problem– sink target node being mapped– source start set (primary inputs)– flow infinite into start set– flow of one on each link– to see if height same as predecessors
• collapse all predecessors of maximum height into sink (single node, cut must be above)
• height +1 case is trivially true
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CALTECH CS137 Fall2005 -- DeHon 21
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Example Subgraph
Target: K=4
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CALTECH CS137 Fall2005 -- DeHon 22
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Trivial: Height +1
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CALTECH CS137 Fall2005 -- DeHon 23
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Collapse at max height
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CALTECH CS137 Fall2005 -- DeHon 24
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Collapse not work (different/larger graph)
Forced to label height+1
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CALTECH CS137 Fall2005 -- DeHon 25
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Reconvergent fanout (different/larger graph)
Can label at height
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CALTECH CS137 Fall2005 -- DeHon 26
Flowmap
• Max-flow Min-cut algorithm to find cut
• Use augmenting paths to until discover max flow > K
• O(K|e|) time to discover K-feasible cut
– (or that does not exist)
• Depth identification: O(KN|e|)
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CALTECH CS137 Fall2005 -- DeHon 27
Flowmap
• Min-cut may not be unique
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CALTECH CS137 Fall2005 -- DeHon 28
Two 3-cuts
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CALTECH CS137 Fall2005 -- DeHon 29
Flowmap
• Min-cut may not be unique
• To minimize area achieving delay optimum– find max volume min-cut
• Compute max flow find min cut• remove edges consumed by max flow• DFS from source• Compliment set is max volume set
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CALTECH CS137 Fall2005 -- DeHon 30
Graph
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CALTECH CS137 Fall2005 -- DeHon 31
Graph: maxflow (K=3)
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CALTECH CS137 Fall2005 -- DeHon 32
Graph: BFS source
Reachable
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CALTECH CS137 Fall2005 -- DeHon 33
Max Volume min-cut
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CALTECH CS137 Fall2005 -- DeHon 34
Flowmap
• Covering from labeling is straightforward– process in reverse topological order– allocate identified K-feasible cut to LUT– remove node– postprocess to minimize LUT count
• Notes:– replication implicit (covered multiple places)– nodes purely internal to one or more covers may
not get their own LUTs
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CALTECH CS137 Fall2005 -- DeHon 35
Flowmap Roundup
• Label– Work from inputs to outputs– Find max label of predecessors– Collapse new node with all predecessors at this label– Can find flow cut K?
• Yes: mark with label (find max-volume cut extent)• No: mark with label+1
• Cover– Work from outputs to inputs– Allocate LUT for identified cluster/cover– Recurse covering selection on inputs to identified LUT
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CALTECH CS137 Fall2005 -- DeHon 36
Area
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CALTECH CS137 Fall2005 -- DeHon 37
DF-Map
• Duplication Free Mapping– can find optimal area under this constraint– (but optimal area may not be duplication
free)
[Cong+Ding, IEEE TR VLSI Sys. V2n2p137]
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CALTECH CS137 Fall2005 -- DeHon 38
Maximum Fanout Free Cones
MFFC: bit more general than trees
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CALTECH CS137 Fall2005 -- DeHon 39
MFFC
• Follow cone backward
• end at node that fans out (has output) outside the code
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CALTECH CS137 Fall2005 -- DeHon 40
MFFC example
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CALTECH CS137 Fall2005 -- DeHon 41
MFFC example
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CALTECH CS137 Fall2005 -- DeHon 42
DF-Map
• Partition into graph into MFFCs• Optimally map each MFFC• In dynamic programming
– for each node• examine each K-feasible cut
– note: this is very different than flowmap where only had to examine a single cut
• pick cut to minimize cost– 1 + MFFCs for fanins
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CALTECH CS137 Fall2005 -- DeHon 43
DF-Map Example
Cones?
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CALTECH CS137 Fall2005 -- DeHon 44
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 45
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 46
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 47
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 48
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 49
DF-Map Example
Startmappingcone
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CALTECH CS137 Fall2005 -- DeHon 50
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 51
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 52
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 53
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 54
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 55
DF-Map Example
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Similarto previous
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CALTECH CS137 Fall2005 -- DeHon 56
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CALTECH CS137 Fall2005 -- DeHon 57
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CALTECH CS137 Fall2005 -- DeHon 58
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CALTECH CS137 Fall2005 -- DeHon 59
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CALTECH CS137 Fall2005 -- DeHon 60
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CALTECH CS137 Fall2005 -- DeHon 61
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CALTECH CS137 Fall2005 -- DeHon 63
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CALTECH CS137 Fall2005 -- DeHon 64
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CALTECH CS137 Fall2005 -- DeHon 66
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CALTECH CS137 Fall2005 -- DeHon 69
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CALTECH CS137 Fall2005 -- DeHon 70
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CALTECH CS137 Fall2005 -- DeHon 71
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CALTECH CS137 Fall2005 -- DeHon 72
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CALTECH CS137 Fall2005 -- DeHon 74
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CALTECH CS137 Fall2005 -- DeHon 78
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CALTECH CS137 Fall2005 -- DeHon 79
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CALTECH CS137 Fall2005 -- DeHon 80
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CALTECH CS137 Fall2005 -- DeHon 81
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CALTECH CS137 Fall2005 -- DeHon 82
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 83
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 84
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 85
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 86
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 87
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 88
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 89
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 90
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 91
DF-Map Example
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CALTECH CS137 Fall2005 -- DeHon 92
Composing
• Don’t need minimum delay off the critical path
• Don’t always want/need minimum delay
• Composite:– map with flowmap– Greedy decomposition of “most promising”
non-critical nodes– DF-map these nodes
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CALTECH CS137 Fall2005 -- DeHon 93
Variations on a Theme
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CALTECH CS137 Fall2005 -- DeHon 94
Applicability to Non-LUTs?
• E.g. LUT Cascade – can handle some functions of K inputs
• How apply?
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CALTECH CS137 Fall2005 -- DeHon 95
Adaptable to Non-LUTs
• Sketch:
– Initial decomposition to nodes that will fit
– Find max volume, min-height K-feasible cut– ask if logic block will cover
• yes done• no exclude one (or more) nodes from block and
repeat– exclude == collapse into start set nodes– this makes heuristic
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CALTECH CS137 Fall2005 -- DeHon 96
Partitioning?
• Effectively partitioning logic into clusters– LUT cluster
• unlimited internal “gate” capacity• limited I/O (K)• simple delay cost model
– 1 cross between clusters– 0 inside cluster
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CALTECH CS137 Fall2005 -- DeHon 97
Partitioning
• Clustering – if strongly I/O limited, same basic idea
works for partitioning to components• typically: partitioning onto multiple FPGAs• assumption: inter-FPGA delay >> intra-FPGA
delay
– w/ area constraints • similar to non-LUT case
– make min-cut– will it fit?– Exclude some LUTs and repeat
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CALTECH CS137 Fall2005 -- DeHon 98
Clustering for Delay
• W/ no IO constraint
• area is monotone property
• DP-label forward with delays– grab up largest labels (greatest delays)
until fill cluster size
• Work backward from outputs creating clusters as needed
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CALTECH CS137 Fall2005 -- DeHon 99
Area and IO?
• Real problem:– FPGA/chip partitioning
• Doing both optimally is NP-hard
• Heuristic around IO cut first should do well– (e.g. non-LUT slide)– [Yang and Wong, FPGA’94]
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CALTECH CS137 Fall2005 -- DeHon 100
Partitioning
• To date:– primarily used for 2-level hierarchy
• I.e. intra-FPGA, inter-FPGA
• Open/promising– adapt to multi-level for delay-optimized
partitioning/placement on fixed-wire schedule
• localize critical paths to smallest subtree possible?
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CALTECH CS137 Fall2005 -- DeHon 101
Summary
• Optimal LUT mapping NP-hard in general– fanout, replication, ….
• K-LUTs makes delay optimal feasible– single constraint: IO capacity– technique: max-flow/min-cut
• Heuristic adaptations of basic idea to capacity constrained problem– promising area for interconnect delay
optimization
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CALTECH CS137 Fall2005 -- DeHon 102
Admin
• No class Monday, October 3rd
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CALTECH CS137 Fall2005 -- DeHon 103
Today’s Big Ideas:
• IO may be a dominant cost– limiting capacity, delay
• Exploit structure: K-LUTs
• Mixing dominant modes– multiple objectives
• Define optimally solvable subproblem– duplication free mapping