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DAC Demo: DRM to DRC
DRM -> XML -> OpenDFM -> DRC -> Layout Viewer
Benoit Ramadout / Flavien Delauche / Jake Buurma
For more information:
Jake Buurma
Si2 VP Operations
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Today’s Demo
Primary Demonstration Points
– DRM specification and the DRC runset should always agree but:
• Separated in time and space with many revisions over the lifetime of a chip
• Single mistake in the design flow from DRM to DRC can be fatal
• One DRM is the source of multiple DRC runsets but development and maintenance
of every new DRC runset is expensive and introduces both risk and delays
– Si2 has changed the game with OpenPDK and OpenDFM
• Si2 is unique in that we focus on integrated design flows with inter-operability
• For the first time, executable specifications can provide data previously expressed
on paper but now codified with OPS XML database and XSD
• The meta data of the entire design flow is validated and properly accounted
• Meta data includes revisions and ECOs from inspection to conclusion
– Cooperation on industry standards allows Si2 members to more
efficiently advance their proprietary products and services
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The Problem of Revision Skew
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Runset v1.0
DRM v1.0 DRM v1.x
Runset v1.y
Revision
Skew
Verification Expert fixes the
DRC Runset and notifies Tech
Pubs to update the DRM
Manufacturing Expert
updates the DRM and
notifies Design Team to
fix the DRC Runset
At inception Over a multi-year Lifespan
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OPS XML the Gold Standard
DRM v1.5
Runset v1.5
The OPS XML Database is a complete DRM in both
human readable and machine readable formats
A change in the XML asserts to update all dependent
formats regardless of their physical location
The Solution for Revision Skew
The DRC runset uses xPath pointers into the golden
DRM. OpenDFM and DRC+ are generated from the
layout equations expressed in the DRM
It is NOT a copy of the DRM data it IS the DRM
data and so it must always be accurate
The DRM is viewed via customized style sheets
for all of the different design teams that use it
Text, Equations, Graphics, Layout Clips are
included by either embedding or linking
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Design Rule Manual (DRM)
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Process Database
Human Readable
Contributed by ST Microelectronics
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Design Rule Manual (DRM) in OPS XML
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Process Database
Machine Readable
XPATH through DRM Hierarchy
DRM
Root
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Step 1 Generate OpenDFM DRC Rules
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Mentor
plug-in
Synopsys
plug-in
Cadence
plug-in
Additional
plug-in
Calibre
DRC
Runset
ICV
DRC
Runset
PVS
DRC
Runset
Additional
DRC
Runset
OpenDFM Parser
OPS XML DRM
The DRC runset is composed of Xpath pointers into the DRM
xPath pointer
Multiple Runsets
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Step 2 Create a 45nm Test Case
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XOR2_X2 with Seed Error Nangate XOR2_X2 with No Errors
DAC Demo Flow:
Test case with 50K cells with 500 XOR2_X2 gates randomly placed
Run DRC using ICV, PVS and Calibre on the entire 50K gate chip
Report all seed errors and any false errors
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Step 3 PVS, ICV & Calibre Correlation
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Error
Markers
PVS
ICV
Calibre
All error
markers
an
Exact
Match
100% Correlation
on all seed errors
Zero False Errors
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DAC Demo Contributors
• IBM – OpenDFM Targeting Rules on ICV and Calibre
• TI – OpenDFM DRC rules on PVS, ICV and Calibre
• LSI – OPEX process parameters
• Nangate – 45 nm Standard Cell Library
• ST Microelectronics – OPS XML 45nm DRM Example File
• Cadence – PVS plugin for OpenDFM DRC
• Synopsys – ICV plugin for OpenDFM DRC
• Mentor – Calibre plugin for OpenDFM DRC
• SpringSoft – Laker Custom Layout Editor for Error Viewing
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