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VLSI
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What is VLSI?
Very Large Scale Integration
SSI Small-Scale Integration (0-102)---1960
MSI Medium-Scale Integration (102-103)---1967
LSI Large-Scale Integration (103-105)---1972
VLSI Very Large-Scale Integration (105-107)---1978
ULSI Ultra Large-Scale Integration (>=107)---1989
GSI _ Giant Scale Integration (>=109)---2000
*Where these are given as no of transistors.
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Integration Level Trends
Obligatory historical Moores law plot
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Integrated Circuits/MEMs
Hierarchy of various technology
Semiconductor process
Silicon GaAs
UnipolarBipolar UnipolarBipolar
ECL
TTL
NMOS PMOS
CMOS
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Chips
Integrated circuits consist of: A small square or rectangular die, < 1mm thick
Small die: 1.5 mm x 1.5 mm => 2.25 mm2
Large die: 15 mm x 15 mm => 225 mm2
Larger die sizes mean:
More logic, memory
Less volume
Less yield
Dies are made from silicon (substrate) Substrate provides mechanical support and
electrical common point
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Advancements over the years
Intel 4004
Processor Introduced in
1971
2300 Transistors
108 KHz Clock
Intel P4Processor
Introduced in 2000
40 MillionTransistors
1.5GHz Clock
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System Design Pyramid
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Photo-litho-graphy: latin: light-stone-writing
Photolithography: an optical means for transferring patterns
onto a substrate. Patterns are first transferred to a photoresist layer.
Typically a wafer is about 8-10 inches in diameter.
Individual ICs are placed inside it.
Photolithography andPatterning
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Photoresist is a liquid film that is spread out onto a
substrate, exposed with a desired pattern, and
developed into a selectively placed layer for subsequent
processing.
Photolithography is a binary pattern transfer: there is
no gray-scale, color, nor depth to the image.
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Steps
Photo resist Coating (covering)
A light sensitive organic polymer (plastic)
Mask/ Reticle formation
Exposure to light (UV/X-RAY/E-BEAM)
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WHAT IS A PHOTOMASK?
Photomasks are high precision plates containing microscopic
images of
electronic circuits. Photomasks are made from very flat pieces
of quartz or glass with a layer of chrome on one side. Etched
in the chrome is a portion of an electronic circuit
design. This circuit design on the mask is also called
geometry.
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The Resist
The first step is to coat the Si/SiO2 wafer with a film of alight sensitive material, called a resist.
A resist must also be capable of high fidelity recording of thepattern (resolution) and durable enough to survive later
process steps
Solvent Evaporates
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Next Generation LithographyIn 1996, five technology options were proposed for the
130 nm gate length technology:
X-ray proximity Lithography (XPL)
Extreme Ultraviolet (EUV)Electron Projection Lithography (EPL)
Ion Projection Lithography (IPL)
Direct-write lithography (EBDW).
These options were referred to as the next generationlithography.
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MOSFET Design Rules
Lambda based design Rule
Micron Rule
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Minimum width and Spacing
Layer Value
Poly 2L
Active 3LN select 3L
Metal 3L
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Stick Diagrams
Metal
poly
ndiff
pdiffCan also draw
in shades of
gray/line style.
Wi i T k
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Wiring Tracks
A wiring trackis the space required for a
wire
4 l width, 4 l spacing from neighbor = 8 l
pitch
Transistors also consume one wiring track
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Well spacing
Wells must surround transistors by 6 l
Implies 12 l between opposite transistorflavors
Leaves room for one wire track
Sti k Di
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Basic Circuit Layout
Gnd
VDD
x x
X
X
X
X
VDD
x x
Gnd
Stick
Diagra
m
Stick Diagrams
Sti k Di
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Layout Diagrams
Gnd
VDD
x x
X
X
X
X
VDD
x x
Gnd
Stick Diagrams
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Example: Inverter
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MOSFET Arrays and AOI GatesA B C
yx
y
x
A B C
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Parallel Connected MOS
Patterning
x
y
A B
X X X
A B
x
y
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Alternate Layout Strategy
A B
x
y
X X
X X
x
A B
y
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MOSFET Arrays and AOI GatesNAND2 Layout
Gnd
Vp
ba.
a b
Vp
Gnd
X X X
X
X
a b
ba.
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NOR2 Layout
Gnd
Vp
ba
a b
Vp
Gnd
X X
ba
X X X
a
b
Stick Diagrams
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Stick Diagrams
Power
Ground
B
C
OutA
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Cells, Libraries, and Hierarchical
Design Creation of a Cell Library
x
Gnd
x
X
X
X
X
X
X
X
X
VDD
X xx
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X X X
X X
a
b
X
X
X
X
VDD
x
Gnd
X
.
ab
.ab
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Gnd
X X
ba
X X X
a
b
X
X
X
X
VDD
xa b
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Cell Placement System Hierarchy (MOSFET-Gates-F/Fs-
Registers-Networks-Systems)
Floorplans and Interconnect Wiring
Y= (# of Good Chips/Total No)*100%
Y=Yield
Y depends on total area=A, and no of
defects=D,
Y=e *100%AD
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Interconnects Place and Route Algorithm.
Wiring Delay
td=kl2
l=length of inter connect.td