Instructions for use
Title Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based HexagonalNanowire Networks Utilizing a Hexagonal BDD Quantum Circuit Approach
Author(s) Kasai, S.; Yumoto, M.; Sato, T.; Hasegawa, H.
Citation Nanoscale Devices, Materials, and Biological Systems: Fundamental and Applications, 125-146
Issue Date 2004
Doc URL http://hdl.handle.net/2115/8368
Rights(C) The Electrochemical Society, Inc. 2004. All rights reserved. Except as provided under U.S. copyright law, this workmay not be reproduced, resold, distributed, or modified without the express permission of The Electrochemical Society(ECS). The archival version of this work was published in ECS Proceeding, 2004-13, 125-146 (2004)
Type proceedings (author version)
File Information ECSProc2004.pdf
Hokkaido University Collection of Scholarly and Academic Papers : HUSCAP
Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based Hexagonal Nanowire Networks
Utilizing a Hexagonal BDD Quantum Circuit Approach
S. Kasai, M. Yumoto, T. Sato and H. Hasegawa Research Center for Integrated Quantum Electronics and Graduate School of
Information Science and Technology, Hokkaido University, N14, W9, Sapporo 060-0814, Japan
ABSTRACT
This paper discusses feasibility of design and future implementation of ultra-small-size and ultra-low-power digital logic systems by a hexagonal BDD (binary-decision diagram) quantum circuit approach. The discussion is based on various circuits formed on GaAs-based hexagonal nanowire networks controlled by nanometer scale Schottky wrap gates (WPGs). Starting from basic node devices and elementary logic function blocks, fabrication technology of hexagonal BDD quantum circuits up to 8-bit adders with node densities over 45 million nodes/cm2 has been successfully developed. Their correct operations at low temperatures and room temperature have been confirmed by experiments and simulation. Various circuit components in logic processors, including arithmetic logic unit (ALU), controller and decoders have been successfully designed as hexagonal BDD layouts without nanowire crossover. For sequential circuits, WPG-controlled nanowire FETs on hexagonal networks have been investigated, and registers and counters have been implemented using these nanowire FETs showing correct operation. Hexagonal BDD-based static 2-bit nano-processor unit (NPU) has been successfully designed completely on hexagonal nanowire network. Ultra high-density GaAs hexagonal nanowire networks with much smaller wire sizes than those of etched nanowire networks have been successfully formed by selective MBE growth, showing great promise for room temperature operation in quantum regime as well as reduction of system area and power consumption.
I. INTRODUCTION
Key hardwares in future ubiquitous network society are intelligent digital systems formed on ultra-small-size chips and operating at ultra-low power consumptions. For their realization, further advance of the LSI technology is required. However, the mainstream Si CMOS LSI technology is quickly saturating, facing various problems not only related to devices but also to logic and system architectures [1]. Therefore, exploration of a completely new LSI technology beyond the scaling limit of the Si CMOS LSI is desirable.
As a possible approach, quantum circuits utilizing quantum nanodevices, such as
1
quantum wire transistors (QWRTrs) and single electron transistors (SETs), have been studied for many years, paying attention to their rich functionality and capability of high-speed switching at ultra-small-size and ultra-low power dissipation levels. However, no realistic approach for their large-scale integration has been established up to now. The difficulty seems to have come from the fact that most of the previous attempts have aimed at implementing the logic gate architecture used in Si CMOS LSIs. This architecture requires cascade connection of logic gates formed by robust switches which possess large voltage gain, large current drivability and high uniformity of the threshold voltage. On the other hand, quantum nanodevices can handle only very small currents with small voltage gain and poor controllability of threshold voltages. Additionally, room temperature operation is difficult because quantum effects appear only at low temperatures.
To solve these problems and realize large-scale integration of quantum devices, the authors’ group has recently proposed a novel hexagonal BDD quantum circuit approach [2,3] for integration of QWRTrs and SETs. Here, quantum circuits have been reconsidered, not from the device level, but from the logic architecture level in order to realize optimal use of quantum devices for digital information processing systems in a realistic way. The feasibility of the new approach has been investigated through fabrication of small-scale circuits [4-7].
The purpose of this paper is to discuss, on the basis of the promising results obtained so far, feasibility of designing and implementing digital systems with ultra-small sizes and ultra-low-power consumptions by the hexagonal BDD quantum circuit approach. A special focus is put on a design of a new "nano-processor unit (NPU)" on a GaAs-based hexagonal nanowire network controlled by nano-Schottky wrap gates (WPGs).
II. BASIC CONCEPT OF HEXAGONAL BDD QUANTUM CIRCUIT APPROACHAND ITS IMPLEMENTATIONS
Instead of the conventional logic gate architecture, the hexagonal BDD quantum
circuit appraoch [2,3] utilizes the binary-decision-diagram (BDD) logic architecture [8,9] where a logic function is represented by a directed graph connecting nodes through which an information messenger travels down in one way. More specifically, a BDD circuit consists of binary path-switching node devices suitably interconnected on a hexagonal network to represent a logic function, f, as shown in Fig. 1(a). Each node device has one entry branch and two exit branches and it selects one of the exit branches according to the binary logic input, xi = 0 or 1, as shown in Fig. 1(b). Then, the value of a logic function, f, is evaluated by propagating a messenger from the top root toward bottom terminals in Fig. 1(a) through the path selected by each node device at each node. If the messenger reaches the terminal-1, then the logic value is unity, and if it reaches the terminal-0, then it is zero. Because of the three-hold symmetry of the node device, arranging the node devices on a hexagonal layout naturally provides the highest possible packing density.
The unique feature of the BDD architecture is that it does not have a direct input-output connection, and this results in advantages that no large transfer gain, no high current drivability and no precise threshold voltage control are required for the node device. Although various kinds of combinations of node devices and information messengers can be operated as BDD circuits, the above features are particularly suitable to non-robust and structure- and charge- sensitive quantum nanodevices controlling quantum transport of a single electron (SE) or a few electrons used as the messenger. In
2
such a combination, the power-delay product (PDP) for switching decreases greatly and approaches to the quantum limit given by the Heisenberg uncertainty principle.
For actual hardware implementation of the hexagonal BDD quantum circuit approach, we have been investigating a GaAs-based hexagonal nanowire network structures controlled by Schottky wrap gates (WPGs), as shown in Fig. 2(b). The Schottky wrap gate [10] has a structure where a nanometer sized Schottky gate is wrapped around the nanowire. It has a simple lateral planar structure suitable for planar integration, and can produce tight gate control and strong electron confinement. The nanowire is formed by wet etching of AlGaAs/GaAs modulation doped heterostructure wafers using conventional electron beam (EB) lithography. Here, combination of superb quantum transport along high quality heterointerface and well-behaved Schottky interfaces with sufficiently high barrier height can be utilized.
Various types of node devices can be designed by the WPG arrangements on the nanowire network, as shown in Fig. 2(b). A nanowire piece with a single WPG operates as a QWRTr. A nanowire piece controlled by a couple of narrow WPGs with a small spacing produces double tunneling barriers with a quantum dot in between under suitable WPG voltage and this structure operates as a SET. We call a type of node device having QWR or single electron (SE) switches on each exit branches as the branch-switch type node devices. On the other hand, a SE node device having narrow WPGs on each of three branches, where a quantum dot surrounded by three tunneling barriers is formed at the node position, is called the node-switch type SE node device. The branch-switch and node-switch type SE node devices can precisely control single electrons, and can realizes small values of PDPs. On the other hand, branch-switch type QWR node devices have structure simpler to realize, and useful for feasibility study of integration.
III. DESIGN, FABRICATION AND CHARACTERIZATION OF
SMALL-SCALE HEXAGONAL BDD QUANTUM CIRCUITS
Figure 3(a) shows an SEM image of a fabricated BDD branch-switch QWR node device with its I-V characteristics at room temperature shown in Fig. 3(b). At low temperatures, nanowire branches controlled by WPGs in QWR and SE node devices showed clear conductance quantization and conductance oscillation characteristics, respectively, as shown in Fig. 3(c). These characteristics in the quantum regime are maintained up to a few ten K. Fabricated devices exhibited clear path switching characteristics based quantum transports as shown in Fig. 3(d) for a QWR node device as an example. Successful path switching was also obtained even at room temperature as also shown in Fig. 3(d) where quantum transport should disappear. This is because WPG-controlled nanowires can also operate as conventional semi-classical FETs at high temperatures as can be seen in Fig. 3(b) with excellent gate control. The difference is that the number of electrons should be increased for proper operation, and this results in increase of the PDP value. Thus, hexagonal BDD circuits can operate at room temperature, and since substantial partial involvements of quantum transport mode are expected even at room temperature, reduced PDP values can be expected as compared with those of classical counterparts.
Elemental small-scale logic circuits integrating a few node devices have been successfully fabricated and their correct operations have been realized. Figure 4(a) shows an SEM image of a fabricated QWR-type AND logic and its input-output waveforms. It realized correct switching between 0-th and 1st quantized steps of conductance steps. It could also operate at room temperature in the classical regime
3
adjusting gate and terminal voltage. SE-type OR logic has been also fabricated and their correct operations have been confirmed both in quantum regime with single electron transport and in the classical regime as shown in Fig. 4(b).
As a basis to judge the suitability of the present approach for construction of large scale digital systems, we have estimated power-delay product (PDP) values of the fabricated WPG-based QWR and SE switches, using a simple approximate relation of PDP = CG ∆VG
2, where CG is a gate capacitance and ∆VG a gate voltage swing [3]. Gate capacitances were evaluated experimentally from gate-voltage-dependent Landou plots by magneto-resistance measurement for QWR devices [4] and from Coulomb blockade characteristics for SE devices. Small PDP value of 10-22 J was obtained in SE devices at 1.6 K. This is four orders of magnitude smaller than 10-17 J of 20 nm-gate Si MOSFET at 300 K [11]. The values for QWR devices were 10-20 J for the WPG length, LG = 630 nm and 10-21 J for LG = 65 nm, which are also much smaller than that of the Si MOSFETs. These results indicate the capability of ultra-small power consumption of the hexagonal BDD quantum circuits. The obtained PDPs of QWR devices depend on the WPG size. This shows that further small PDP values can be realized by scale down of WPG size.
Switching speeds of branch switches have been evaluated for QWR devices by direct high-frequency S parameter measurements at room temperature, using a vector network analyzer. Here, special devices having 90 nanowire switches are integrated in parallel have been used to cope with the high impedance nature of quantum device. The results have indicated GHz clock operation capability of branch switches from measured cutoff frequencies over 2 GHz for 110 nm-gate QWR-type devices [6,7]. On the basis of these encouraging results, feasibility of design and fabrication of standard circuit blocks for digital signal processing has been investigated. Here, it is important to be able to design any of such standard circuits on hexagonal nanowire networks without crossover of nanowires. A useful design guidance has been found to be the following; 1) omitting of terminal-0 (because the logic value can be determined by checking whether the messenger has arrived at the terminal-1 or not), 2) representation of a logic function by a principal disjunctive canonical form and 3) removal of redundant/equivalent nodes and branches without causing nanowire crossing. Various circuits for arbitrary bit number can be designed using this design approach. The BDD circuit diagrams of n-bit adder, substractor and comparator are shown in Fig. 5, as examples. In these examples, any standard circuits for any number of bits can be designed by stacking basic units. It should be mentioned that BDD circuits require smaller number of devices than those in the CMOS logic gate architecture [12]. For example, an adder unit in the hexagonal BDD for requires 11 devices, whereas that of the CMOS logic gate requires 24 transistors. Other combinational circuits including decoder, encoder and parity checker have been also designed using the hexagonal BDD quantum circuit approach. Some of the hexagonal BDD-based circuits have been successfully fabricated on hexagonal nanowire networks having node densities of a few ten mega nodes per cm2 formed by EB-lithography and wet chemical etching. Figure 6(a) shows a fabricated QWR-type 2-bit adder as an example. This circuit integrates 14 node devices with a node density of 25M/cm2. The correct operation of this adder circuit was confirmed at room temperature as shown in Fig. 6(b). Here, input logic swing and offset voltages are kept the same for all devices. This indicates that device characteristics are fairly uniform. It may be also the case that the hexagonal BDD circuits can operate allow rather wide variations of device parameters for correct performance. Fig. 7 shows a fabricated QWR-type 8-bit adder, where 84 devices are integrated on 74µm x 19µm area using a network
4
of 25 M nodes/cm2 fabrication process. This is the highest scale of device integration so far reported for the quantum nanodevice circuits. Large number of BDD devices can be integrated without nanowire crossover. At present, 45 M nodes/cm2 circuit fabrication process is being developed.
IV. TOWARD HEXAOGNAL BDD-BASED DIGITAL SYSTEMS
In order to see the feasibility of digital signal processing systems based on the
hexagonal BDD quantum circuit approach, a 2-bit arithmetic logic unit (ALU) has been designed as a first step. The circuit diagram of a 8-instruction 2-bit ALU is shown in Fig. 8(a). This ALU consists of circuits for each instruction combined with selector circuits for each bit. This is a very simple design approach, and makes it easy to check the logic operation even in the case when the numbers of bits and instructions are increased. The device count of the hexagonal BDD is 56 whereas the transistor count of a 7-instruction 2-bit CMOS ALU is 144. This is useful for reducing both the circuit area and the power consumption. This ALU will occupy areas of 360 µm2 and 16 µm2 nanowire network structures with node densities of 45 M and 1G nodes/cm2, respectively. The SEM image of the fabricated QWR-type test ALU structure using 45 M nodes/cm2 fabrication process is shown in Fig. 8(b). The correct operation of the circuit has been confirmed by a SPCIE circuit simulation as shown in Fig. 8(c), although experimental confirmations need more time.
Most digital systems require sequential circuits such as registers. These circuits are difficult to implement by the BDD logic architecture with path switching at nodes. Sense amplifier and level adjusters are also necessary for signal level matching between different BDD logic blocks and between BDD and other blocks such as memory. For this purpose, use of WPG-controlled nanowire FETs formed on hexagonal networks has been investigated. As already shown in Fig. 3(b), WPG-controlled nanowire pieces can operate as FETs. Fabricated inverters using the FETs on a hexagonal nanowire network have shown a transfer gain of 3, even at room temperature, and this is sufficient for implementation of sequential circuits and amplifiers. They obviously can operate also at low temperatures. Thus, whole of the system working from low temperatures to room temperature can be implemented on a hexagonal network structure. As shown in Fig. 9(a), RS flip-flop (FF) circuits have been fabricated and their correct operations have been confirmed experimentally. This also confirms the capability of realization of static RAM (SRAM) on the hexagonal nanowire networks. As an example, a 128 bit SRAM designed on a hexagonal network with 66 x 44 hexagons is shown in Fig. 9(b). Registers by D-FF and counters by T-FF were also successfully designed and correct operations were confirmed by SPICE simulation as shown in Fig. 10, allowing use of small input voltage swings.
Design Feasibility of the present circuit approach for the implementation of digital systems has been confirmed by a successful design of a static 2-bit nano-processor (NPU) as shown in Fig. 11(a). Its system architecture is shown in Fig. 11(b). Execution cores of this system, ALU and controller, are implemented by quantum BDD circuits. Here, the four ALU instructions are implemented. The device count of the hexagonal BDD-based 2-bit NPU is 381 devices, and this number is much smaller than that of about 700 transistors for a processor designed with CMOS logic gates using the same system architecture shown in Fig. 11(b), The 2-bit nano-processor in Fig. 11(a) is now in the process of actual fabrication. Power consumption of the NPU has also been estimated. The system power consumption is estimated from activity factor, a, device count based
5
on this system architecture, nd, and clock frequency, fclock, by a formula, P = a•nd•PDP•fclock. By counting the number of switching events in each component for typical system instructions and data processing, the activity factor has been estimated for each component. The average value is 0.2. Total power consumption can be obtained by summation of power consumptions of each component. Then the power consumption of the hexagonal BDD-based 2-bit NPU using SE-type devices in the quantum regime is estimated only 0.01 nW at 10 MHz clock. Here, 10 times large supply and logic swing voltages have been assumed for the sequential circuits. Even in the classical regime, the system consumes 1 µW at the same clock frequency, where ∆VG = 400mV from the data in Fig. 6(b) has been assumed. It is seen that most of the power is consumed in sequential circuits in the present system architecture. Further sophisticated design of the system architecture and exploring other approaches to implement sequential circuits are thus desirable. On the other hand, when the number of bit increased, system power consumption is dominated by combinational circuits, because their device count increases rapidly with the order of (n2 + n)•N, where n is the number of bit and N is the number of ALU instructions, although the other parts increases with the order of n or n•N. In addition, the device counts in BDD-based combinational circuits is smaller than that of CMOS logic gate combinational circuits [12]. Therefore, the power consumption of the hexagonal BDD-based digital systems for large number of bits will become much smaller than that of the CMOS systems.
For further high-density integration of the system and its quantum regime operation at room temperature, denser hexagonal networks with narrower nanowires realizing strong electron confinement are required. For this purpose, formation of embedded GaAs nanowires by selective MBE growth on patterned substrates [13,14] has been investigated. The selective MBE growth can realize size- and position-controlled nanowires with smaller size than the lithography size where the GaAs nanowires are completely embedded in AlGaAs layer as shown in Fig. 12(a) so as to form high quality heterointerface. Thus, strong one-dimensional confinement is realized, and the operation temperature range of BDD node devices in the quantum regime is increased. As shown in Fig. 12(b), a hexagonal nanowire network structure over 200M nodes/cm2 has been successfully formed, and this will realize the 2-bit NPU discussed here on an area of only 20 x 29 µm2. The nanowire network structure having Giga-node density has also been realized by the selective MBE growth of InP-based materials [15]. QWR-type node devices using the embedded nanowires controlled by WPGs has been fabricated [16,17] and their excellent path switching characteristics have indicated good prospects for realization of the highly dense hexagonal BDD-based digital systems using the hexagonal nanowire networks by the selective MBE growth.
V. CONCLUSIONS
Feasibility of design and implementation of ultra-small-size and ultra-low-power digital systems utilizing the hexagonal BDD quantum circuit approach has been discussed on the basis of circuits formed on GaAs-based hexagonal nanowire networks controlled by nanometer scale Schottky wrap gates (WPGs). Starting from basic node devices and elementary logic function blocks, fabrication technology of hexagonal BDD quantum circuits up to 8-bit adders with node densities over 45 million nodes/cm2 has been successful developed. Correct circuit operations at low temperatures and room temperature have been confirmed by experiments and simulation. Various circuit components in logic processors, including arithmetic logic unit (ALU), controller and
6
decoders have been successfully designed as hexagonal BDD layouts without nanowire crossover. For sequential circuits, WPG-controlled nanowire FETs on hexagonal networks have been investigated, and registers and counters have been implemented using these nanowire FETs showing correct operation. Hexagonal BDD-based static 2-bit nano-processor unit (NPU) has been successfully designed completely on hexagonal nanowire network. Ultra high-density GaAs hexagonal nanowire networks with much smaller wire sizes than those of etched nanowire networks have been successfully formed by selective MBE growth, showing great promise for room temperature operation in quantum regime as well as reduction of system area and power consumption.
ACKNOWLEDGMENT
This work is supported in part by 21st Century COE program in Hokkaido University, "Meme-media Technology Approach to the R&D of next-generation ITs", from MEXT, Japan.
7
References [1] International Technology Roadmap for Semiconductors, http://public.itrs.net/ [2] H. Hasegawa and S. Kasai, Physica E 11, 149 (2001). [3] S. Kasai and H. Hasegawa, IEEE Electron Device Letter 23, 446 (2002). [4] M. Yumoto, S. Kasai and H. Hasegawa, Micro-electronic. Eng. 63, 287 (2002). [5] S. Kasai, M. Yumoto and H. Hasegawa, Solid-State Electronics 47, 199 (2003). [6] M. Yumoto, S. Kasai and H. Hasegawa, presented at 45th Electronic Materials
Conference (EMC), June 25 - 27, 2003, Salt Lake City, Utah, USA. [7] M. Yumoto, S. Kasai and H. Hasegawa, to be presented at 31st International
Symposium on Compound Semiconductors, Sep. 12-16, 2004, Seoul, Korea. [8] S. B. Akers, IEEE Trans. Compt. C-27, 509 (1978). [9] N. Asahi, M. Akazawa, and Y. Amemiya, IEEE Trans. Electron Devices 44, 1109
(1997). [10] S. Kasai, K. Jinushi, H. Tomozawa and H. Haseegawa, Jpn. J. Appl. Phys. 36, 1678
(1997). [11] R. Chau, presented at 2001 Silicon Nanoelectronics Workshop, June 10-11, 2001,
Kyoto, Japan. [12] K. Yano, Y. Sasaki, K. Rikino and K. Seki, IEEE J. Solid-State Circuits 31, 792
(1996). [13] T. Sato, I. Tamai, C. Jiang and H. Hasegawa, Institute of Physics Conference Series
170, 325 (2002). [14] I. Tamai, T. Sato and H. Hasegawa, Physica E 21, 521 (2004). [15] T. Fukushi, T. Muranaka, and H. Hasegawa, presented at 5th International
Conference on Indium Phosphide and Related Materials, May 12-16, 2003, Santa Barbara, USA.
[16] M. Yumoto, T. Tamura, T. Sato and H. Hasegawa, Superlattice and Microstructures
34, 485 (2004). [17] T. Tamura, M. Yumoto, T. Sato and H. Hasegawa, presented at 46th Electronic
Materials Conference, Jun. 23-25, 2004, Nortre Dame.
8
Figure 1: Basic concept of hexagonal BDD quantum circuits. Figure 2: (a) Implementation of the hexagonal BDD quantum circuit and Schottky wrap gate (WPG) structure and (b) designs of WPG-based BDD quantum node devices. Figure 3: (a) SEM image of fabricated WPG-based QWE-type BDD quantum node device, (b) its IDS-VDS characteristics, (c) conductance characteristics of branch switches in QWR and SE-type devices, and (d) path switching characteristics of the QWR-type node devices. Figure 4: Basic BDD logic elements and their operations. (a) QWR-type AND logic and (b) SE-type OR logic. Figure 5: Circuit diagrams of hexagonal BDD subsystems. (a) Adder, (b) substractor and (c) comparator. Figure 6: (a) SEM image of fabricated hexagonal BDD QWR-type 2-bit adder and (b) its input-output waveforms. Figure 7: SEM image of fabricated hexagonal BDD QWR-type 8-bit adder. Figure 8: (a) Circuit diagram of hexagonal BDD 8-instruction 2-bit ALU, (b) SEM image for fabricated circuit and (c) input-output waveforms by simulation. Figure 9: (a) RS flip flop design and measured input-output waveforms and (b) 128-bit SRAM design. Figure 10: Design of D-FF and T-FF, and input-output waveforms for register and 3-bit counter. Figure 11: (a) Hexagonal BDD-based static 2-bit nano-processor design and (b) its system architecture. Figure 12: (a) Corss section of the selectively MBE grown GaAs nanowire and (b) high-density hexagonal GaAs-embedded nanowire network with node density of 2.3x108 nodes/cm2.
9
Architecture
Ex: ƒ = x1•x2 + x3
node device
terminals
x2
x3
ƒ
10
x10 1
0 1
0 1
messenger
hexagonalnetwork
x1
x2
x3
logicinput
rootmessenger: single / a few electron
xi0 1
0-branch
entry
1-branch
xi = "0"xi
0 1
xi = "1"
Figure 1: Basic concept of hexagonal BDD quantum circuit approach.
III-V hexagonal nanowire network Schottky wrap-gate (WPG) structure
electrons
WPG
GaAs
AlGaAs
W
LG
(a)
quantum dot
Quantum wire (QWR) type
QWR
depletion layernanowire
WPG
entry
0-branch 1-branch
VxiVxi
Single electron (SE) type
quantum dot
WPG0 1
VxiVxi
entry
WPG0 1
VxiVxi
entry
(b)
branch switch type node switch type
Figure 2: (a) Implementation of the hexagonal BDD quantum circuit and Schottky wrapgate (WPG) structure and (b) designs of WPG-based BDD quantum node devices.
Figure 3: (a) SEM image of fabricated WPG-based QWE-type BDD quantum nodedevice, (b) its IDS-VDS characteristics, (c) conductance characteristics of branchswitches in QWR and SE-type devices, and (d) path switching characteristics of theQWR-type node devices.
50time (sec)
0
0.5
1.0
0 10 20 30 40
cond
ucta
nce
(2e2
/h)
0-branch1-branchoutput
VDD=0.2mVinput xi
1.7 K
0
1
297 K
0.60
5
10
15
0 0.1 0.2 0.4
outp
ut c
urre
nt (
μA)
time (ms)
VDD=300 mV
output
input xi
0-branch
0
1
1-branch
1000 nm
WPG
xixi
entry
GaAs nanowire
0-branch 1-branch
QWR type
-2800
1
2
3
-360 -3201.6K2.5K3.5K4.2K6K11K19K24K
ID (
nA)
VG (mV)
SE branch
0
2
4
6
8
10
-200 -100 0 100 200
Con
duct
ance
(2e
2 /h)
VDS = 0.2 mV
78K
65K
55K
45K
35K
25K
17K
9K
3.5K
QWR branch
WPG GaAs nanowire
(a) 800
I DS
(μA
)
0
2
4
6
8
10
12
14
0 200 400 600VDS (mV)
295 K VG = 800 mV700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
W = 560 nmLG = 500 nm
(b)
(c)
(d)
VG (mV)
1 0
01
1
AND
x1
x2
1000 nm root
X1
X2 X2
X1
WPG
terminal-1
classical regime (300 K)
500 nA
0 5 10 15time (sec)
output
VDD = 250 mVx1
x2
2020
quantum regime (1.6 K)
time (sec)5 10 15
VDD = 0.2 mV
5 nA
output
x1
x2
0
(a)
output
0 50 100 150 200time (sec)
0.2 nA
classical regime (120 K)
x1
x2
0 2 4 6 8
output
10time (sec)
0.1 nA
quantum regime (1.6 K)x1
x2
1000 nm
x1x1
x2
terminal-1
root
WPG
GaAs nanowire
(b)
1
01
1
x1
x2
OR
Figure 4: Basic BDD logic elements and their operations. (a) QWR-type AND logic and (b) SE-type OR logic.
adder substractor
basicunit
an an-1 ... a0 bn bn-1 ... b0c sn sn-1 ... s0
+
comparator
A = an an-1 ... a0B = bn bn-1 ... b0
1 0 1 0
0 1
1 0
b2
1 0
0 1a2
1 0 1 0
0 1
1 0 1 0
0 1
1 0
b1
1 0
0 1a1
1 0 1 0
0 1
1 0
0 1
1 0 1 0
0 1
1 0
0 1
A>B A<BA=B
b0
a0
b0 b0 b0
a0 a0
a1a1
b1 b1 b1b1b1
a2a2
b2 b2 b2b2b2
1
1 0 1 0
1 010 01
0 011
01 0 1
a1
b1
1 0
1 0
1 0
1 01 0
0 1a0
b0
1 0 1 0
1 010 01
0 011
01 0 1
a2
b2
c s2
s0
s1
1
a0 a0
b0 b0b0
a1 a1 a1
b1 b1 b1 b1 b1 b1
b2 b2 b2 b2 b2 b2
a2 a2 a2
1 0 1 0
0 101 10
0 011
10 1 0
1 0 0
110
01
0
1 0 1 0
01 10
0 011
10 1 0 0 1
s2
s0
s1
b2
a2
a1
b1
a0
b0
b1
b0 b0 b0
a0 a0
b1 b1 b1 b1 b1
a1 a1 a1
b2 b2 b2 b2 b2 b2
a2 a2 a2
an an-1 ... a0bn bn-1 ... b0sn sn-1 ... s0
–
1
(a) (b) (c)
Figure 5: Circuit diagram of hexagonal BDD subsystems. (a) Adder, (b) substractor and(c) comparator.
s0 = a0 + b0
s1 = a0•b0•(a1 + b1)+a0•b0•(a1 + b1)
c1 = a1•b1 + a0•b0•(a1+b1)
5 μmterminal 1
a1
b1
a0
b0
a1
b1
hexagonalnanowirenetwork
WPG
QWRnodedevice
CS1 S0
b0
a0
experiment (classical)
G/2
G/4
G/2
0
G/4
G/3
0
time
0
theory
time (μs)0 400 800
8 kHz
T = 297K VDD=250 mVΔVG = 400 mV, VGoffset = 0 mV
S0
S1
C
a1
a0
b1
b0
(a)
(b)
Figure 6: (a) SEM image of fabricated hexagonal BDD QWR-type 2-bit adder and (b)its input-output waveforms.
s7c
terminal-1
s0
s1
s2
s3
s4
s5
s6
a0b0
a1b1
a2b2
a3b3
a4b4
a5b5
a6b6
a7b7
a0b0
a1b1
a2b2
a3b3
a4b4
a5b5
a6b6
a7b7
hexagonalnanowirenetwork
WPG
10 μm
Figure 7: SEM image of fabricated hexagonal BDD QWR-type 8-bit adder.
(a)
1 0
1 0
1 0
0101 0 1
1 01 0
1 0
10 0 1 01 0 1
1 0
0
1 0 1
101
10
1
0 1
1 0
1 0 1 0
1
0 1
0 1 0
1 0
0 1
0 1
10
1
0
0
0 11
01
1 1 0
1 0 0 1
0
1 1 0
1
1
1
1 0
0 1
00 1
1
0 1
0
1
1
ALU1ALU2
s2
s0
s1
s0s0 s0
s1s1
s2
s0 s0 s0 s0
s1
a1 a1
b1b1
a1
b1
a1
b1b1
a1
b1
a1
b1b1
a1
b1b1
a1
b1
a1
a0
b0b0b0
a0a0
b0 b0
a0 a0
b0
a0 a0
b0
a0
b0
a0
b0
a0
b0
a0
b0
a0
b0
a1
S instructions111: A+B100: AND
110: NOT101: OR
010: bit left shift011: bit right shift
000: comparator001: A-B
sele
cter
subs
yste
ms
(b)
comparator
VDD =10 mV
0 4 8 12 16 20 24 28 32time (ms)
ALU1
ALU0
adder NOR B
0
50
5
s1
s0
a1
a0
b1
b0
ΔVG = 200mV
out
put
inpu
t
(c)
26.2 μm
13.9 μm
root: ALU2 ALU1
terminal-1
nanowire
WPG
Figure 8: (a) Circuit diagram of hexagonal BDD 8-instruction 2-bit ALU, (b) SEM image for fabricated circuit and (c) input-output waveforms by simulation.
S R Qn+1
1 1 Qn 1 0 0 0 1 1 0 0 –
Q
GND
VDDQ
S
RT = 297 K, VDD = 250 mV
S
R
Q
time (s)150 5 10
1 1
0 1
reset
50 mV
0 1
1 1
Qn
set
Qn+1 Qn Qn+1
holdhold
word selecter
word
GND
selecter
bit
memory bus
VDD
bit
60 x 44 hexagons
(a)
(b)
Figure 9: (a) RS flip flop design and measured input-output waveforms and (b) 128-bit SRAM design.
VDD
Trigger
Q
Q
GND
Data
Data
GND
Trigger
Q
Q
VDD
GND
0 0.5 1 1.5 2time (ms)
trigger
input data
Q
Q
200 mV
50 mV
297K
VDD = 400 mV
1-bit register
time (ms)0 0.5 1 1.5 2
C2
C1
C0
VDD = 400 mV
100 mV
100 mV
triger
100 mV
count up50 mV
3-bit counter 297K
(a)
(b)
D-FF
T-FF
Figure 10: (a) Design of a D-FF and input-output waveforms of a register, and (b) design oof T-FF and input-output waveforms of 3-bit counter by T-FF.
GND
D0
D1
D2
c00 1
memory select
c10 1
c30 1
m1m0
c30 1
m5m4
c30 1
m7m6
c30 1
m3m2
c20 1 c20 1
c30 1
m9m8
c30 1
m13m12
c30 1
m15m14
c30 1
m11m10
c20 1 c20 1
c10 1
VDD
Q
VDD
Q
D
GND
TQ
D
GND
Q Q
D
T
Q Q
D
T
Q
Trigger
c0c1
c2
c3
T
D1 D0
VDD
VoutVin
GND
VinVout
sence amplifier
s11 0
ALU1
0s01 s00 1
a11 0
1 b1 0
a10 1
0b1 b11
a11 0
0
a10 1
b10b1 1 0
b01 0
a01 0
1
a00 1
0b01
a00 1
0b01
b11
0s01 s01 0
s11 0
ALU0
1
a00 1
b01 0 10 b0
0 1a0
a10 1
0b10b1 10 1
b00 1
a00
a1
GND
VDD
b1
b0
b0
b1
Q
T
T
D1D0
Q
T
Q
VDD
a0
a0
a1
Vout
VinVDDVin
Vout
clock
1
VDDi0
i0
i2
Q
T
GND
i1
i1
Q
T
Q
T
i2
Q
VDD
PC0
D
T
Q Q
D
T
Q
PC1
s1s0
i010
i201
i101
i201
i001
i101
i210
i20
1p0
10
p101
p101
i010
10
p0
i101
i010
i101
i210
i210
p110
i001
p001
10
i1
p010
i010
p010
i101
i201
i201
i010
i110
i010
10
p0
p110
1
IR triBus -Bf ( reset)Bf tri Adr upA tr iB triAdr up
Bus-M
b1 1
ROM
address decorder
ALU
ACC register
IR
controllerdata bus
29 x 48 hexagon
memory address counter
program counter
decoder
(a)
(b)
program counter
instructiondecoder
ALU
ROM/RAM
data bus
address counter
address decoder trigger
trigger
accumulator(ACC)
instruction
trigger
controller instructionregister(IR)
trigger
register
Figure 11: (a) Hexagonal BDD-based static 2-bit nano-processor design and (b) its architecture.
2.4x108 cm-2
500 nm<510>
<110>
(a)
(b)
GaAs QWR AlGaAs barrierlayer
GaAs pattern substrate
GaAs buffer
Figure 12: (a) Corss section of the selectively MBE grown GaAs nanowire and (b) high-density hexagonal GaAs-embedded nanowire network with node density of 2.3x108 nodes/cm2.
