![Page 1: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/1.jpg)
Design for Testability
1
![Page 2: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/2.jpg)
Basic Concept
• Design for testability (DFT)
– Design techniques that make test generation and test application cost-effective.
• DFT methods for digital circuits:
– Ad-hoc methods
2
– Ad-hoc methods
– Structured methods
• Scan path
• Level sensitive scan design
• Random access scan
• ………
![Page 3: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/3.jpg)
Ad-Hoc DFT Methods
• Good design practices learned through experience are used as guidelines:
– Don’t-s and Do-s
• Avoid asynchronous (unclocked) feedback.
• Avoid delay dependant logic.
3
• Avoid delay dependant logic.
• Avoid parallel drivers.
• Avoid monostables and self-resetting logic.
• Avoid gated clocks.
• Avoid redundant gates.
![Page 4: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/4.jpg)
• Avoid high fanin fanout combinations.
• Make flip-flops initializable.
• Separate digital and analog circuits.
• Provide test control for difficult-to-control signals.signals.
4
![Page 5: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/5.jpg)
Ad-hoc Methods :: Drawbacks
• Experts and tools are not always available.
• Test generation is often manual, and so high fault coverage is not guaranteed.
• Design iterations may be required.
5
• Design iterations may be required.
• Difficult to automate.
![Page 6: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/6.jpg)
Structured Methods
• Helps to provide good controllability and observability of internal state variables for testing.
– Converts the sequential test generation problem into a combinational one.
6
problem into a combinational one.
• Major approaches:
– Scan path
– LSSD
– Random access scan
– Variations to above …….
![Page 7: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/7.jpg)
A Sequential Circuit
Combinational Logic
Primary Input
Primary Output
7
Flipflops
Present State
Next State
![Page 8: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/8.jpg)
Scan Path Design
• Basic Problem– Test generation for sequential circuits is
difficult.
• Objective– Make all the flip-flops directly controllable and
8
– Make all the flip-flops directly controllable and observable.
• What do we gain?– Combinational circuit test generation can be
used.
– A few additional tests to test the flip-flops (shift register).
![Page 9: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/9.jpg)
Scan Design (contd.)
• Pre-specified design rules.
• Test structure added to the verified design.
– Add one (or more) test control (TC) primary input.
– Replace flip-flops by scan flip-flops.
– Connect scan flip-flops to form one or more shift
9
– Connect scan flip-flops to form one or more shift registers in test mode.
– Add SCANIN and SCANOUT pins to shift register.
• Add shift register test and convert ATPG tests into scan sequences for use in manufacturing test.
![Page 10: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/10.jpg)
Scan Design Rules
• Use only clocked D-type master-slave flip-flops for all state variables.
• At least one PI pin must be available for test; more pins, if available, can be used.
• All clocks must be controlled from PIs.
10
• All clocks must be controlled from PIs.
– Necessary for flip-flops to work in scan registers.
• Clocks must not feed data inputs of flip-flops.
– May lead to race condition.
![Page 11: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/11.jpg)
Correcting a Rule Violation
• All clocks must be controlled from PIs.
Comb.logic
Comb.logic
D1
D2
Q
FF
11
logicD2
CK
Comb.logic
D1
D2
CK
Q
FF
Comb.logic
![Page 12: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/12.jpg)
Scan Flip-Flop (master-slave)
D
TC
SD
Q
QMUX
Master latch Slave latch
Logic
overhead
12
CK D flip-flop
CK
TC Normal mode, D selected Scan mode, SD selected
Master open Slave opent
t
![Page 13: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/13.jpg)
Adding Scan Structure
SFF
SFF
Combinationallogic
PI PO
SCANOUT
13
SFF
SFF
SCANIN
TC or TCK
![Page 14: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/14.jpg)
• Application of the test vectors:
PI Present State PO Next State
I1 S1 O1 N1
I2 S2 O2 N2
14
I2 S2 O2 N2
I3 S3 O3 N3
… … … …
![Page 15: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/15.jpg)
Combinational Test Vectors
I2I1 O1 O2
Combinational
PI PO
15
S2S1 N2N1
Combinational
logic
Presentstate
Nextstate
SCANINTC
SCANOUT
![Page 16: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/16.jpg)
Combinational Test Vectors
I2I1PI
SCANIN S1 S2
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC
Don’t care
or random
bits
16
O1 O2PO
SCANOUT N1 N2
![Page 17: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/17.jpg)
• Scan sequence length:
(ns + 1) nc + ns clock periods
17
where nc : number of combinational test vectors
ns : number of scan flip-flops
![Page 18: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/18.jpg)
An example: the I/O specifications
3 inputs, 2 outputs, and 3 state variables
PI Present State PO Next State
0 1 0 1 0 0 0 1 1 0 1
18
0 1 1 0 1 0 1 1 0 0 1
1 0 1 1 0 0 1 0 1 1 1
0 0 1 1 0 1 0 1 0 1 0
![Page 19: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/19.jpg)
contd. : corresponding scan sequence
Clock PI SCANIN TC PO SCANOUT
1 xxx 1 0 xx x
2 xxx 0 0 xx x
3 xxx 0 0 xx x
19
4 010 x 1 01 x
5 xxx 0 0 xx 1
6 xxx 1 0 xx 0
7 xxx 0 0 xx 1
8 011 x 1 11 x
![Page 20: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/20.jpg)
Scan Testing Time
• Scan register has to be tested prior to the application of scan test sequences.
– A shift sequence 00110011… of length ns+4.
– Produces all possible transitions in all flip-flops.
• Total scan test length:
20
• Total scan test length:
(ns + 1) nc + ns + (ns + 4)
ns : number of scan flip-flops
nc : number of combinational test vectors
ns=2000, nc=500 ���� Test length = 106
![Page 21: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/21.jpg)
A Typical Module With Scan Chains
Module
PI
Scan Scan
21
Module
PO
Scan in
Scan out
![Page 22: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/22.jpg)
Multiple Scan Paths
• Scan flip-flops can be distributed among any number of shift registers, each having a separate SCANIN and SCANOUT pin.
– PI and PO pins can be shared with SCANIN and SCANOUT pins respectively.
22
and SCANOUT pins respectively.
• Test sequence length is determined by the longest scan shift register.
• Just one test control (TC) pin is essential.
![Page 23: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/23.jpg)
Multiple Scan Path Example
CombinationalCircuit
MUX
PI/SCANINPO/SCANOUT
23
CircuitSFF
SFF
SFF
MODE
Only one scan path is shown; others can be added similarly
![Page 24: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/24.jpg)
Other Issues
• Multiple scan paths can reduce test application time.
• Scan overhead:– One additional pin (TC)
• Other pins can be multiplexed with
24
• Other pins can be multiplexed with functional input and output pins.
– Area overhead
• Replacing flip-flops by scan flip-flops.
– Performance overhead
• Additional MUX-es in critical path.
• Increase in fanout for the flip-flops.
![Page 25: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/25.jpg)
Scan Overheads
• IO pins:
– One pin necessary.
• Area overhead:
Gate overhead = [4 ns / (ng + 10ns)] x 100%
where n = number of gates in combinational logic
25
where ng = number of gates in combinational logic
ns = number of flip-flops
– Example:
• ng = 100k gates, ns = 2k flip-flops, overhead = 6.7%.
– More accurate estimate must consider scan wiring and layout area.
![Page 26: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/26.jpg)
• Performance overhead:
– Multiplexer delay added in combinational path; approx. two gate-delays.
– Flip-flop output loading due to one additional fanout; approx. 5-6%.
26
fanout; approx. 5-6%.
![Page 27: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/27.jpg)
Hierarchical Scan
• Scan flip-flops are chained within subnetworks before chaining subnetworks.
• Advantages:
• Automatic scan insertion in netlist
• Circuit hierarchy preserved – helps in debugging and design changes
27
and design changes
• Disadvantage: Non-optimum chip layout.
SFF1
SFF2 SFF3
SFF4SFF3SFF1
SFF2SFF4
Scanin Scanout
Scanin
Scanout
Hierarchical netlist Flat layout
![Page 28: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/28.jpg)
ATPG Example: S5378
Original
2,781
179
0
0.0%
Full-scan
2,781
0
179
15.66%
Number of combinational gates
Number of non-scan flip-flops (10 gates each)
Number of scan flip-flops (14 gates each)
Gate overhead
28
0.0%
4,603
35/49
70.0%
70.9%
5,533 s
414
414
15.66%
4,603
214/228
99.1%
100.0%
5 s
585
105,662
Gate overhead
Number of faults
PI/PO for ATPG
Fault coverage
Fault efficiency
CPU time on SUN Ultra II, 200MHz processor
Number of ATPG vectors
Scan sequence length
![Page 29: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/29.jpg)
Summary
• Scan is the most popular DFT technique:• Rule-based design
• Automated DFT hardware insertion
• Combinational ATPG
• Advantages:
29
• Advantages:• Design automation
• High fault coverage; helpful in diagnosis
• Hierarchical – scan-testable modules are easily combined into large scan-testable systems
• Moderate area (~10%) and speed (~5%) overheads
![Page 30: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/30.jpg)
• Disadvantages:• Large test data volume and long test time
• Basically a slow speed (DC) test
30
![Page 31: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/31.jpg)
Level Sensitive Scan Design
• Similar to scan path in concept; uses level sensitive latches.
• Main issues:
– Absence of races and hazards.
– Insensitive to rise time, fall time, delay, etc.
31
– Insensitive to rise time, fall time, delay, etc.
– Lower hardware complexity as compared to scan path design.
– More complex design rules.
![Page 32: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/32.jpg)
LSSD
Polarity-Hold Latch:
L
D
L
D
+L
C D
0 0
0 1
+L
L
L
0
C
32
• The correct change of the latch output (L) is not dependenton the rise/fall time of C, but only on C being ,1, for a periodof time ≥≥≥≥ data propagation and stabilization time.
C 1 0
1 1
0
1
![Page 33: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/33.jpg)
LSSD
Polarity-Hold Shift-Register Latch (SRL):
L1
DI
CSIA
+L1
+L1DI
C
33
• Normal mode: A = B =0, C =0 ���� 1.
• SR (test) mode: C =0, AB = 10 ���� 01 to shift SI through L1
and L2.
L2B
+L2+L2
SI
A
B
![Page 34: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/34.jpg)
LSSD
• Polarity-Hold, hazard-free, and level-sensitive.
• To be race-free, clocks C & B as well as A & B must be non-overlapping.
34
• Avoids performance degradation introduced by the MUX in shift-register modification.
![Page 35: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/35.jpg)
Double-Latch LSSD
C/L
35
XC/L Z
SI SO
CA
B
L1L2 L2 L2L1 L1
![Page 36: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/36.jpg)
Single-Latch LSSD
C/LC/LC/LC/L ZZZZ
36
C/LC/LC/LC/L ZZZZXXXX
SISISISI SOSOSOSO
CCCCAAAA
BBBB
L1L1L1L1L2L2L2L2 L2L2L2L2 L2L2L2L2
L1L1L1L1 L1L1L1L1
![Page 37: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/37.jpg)
Single-Latch LSSD With Conventional SRLs
L2
L2
L1
L1
N1
X1
Y2
SRLe11
e1n
...
...
~~
.
Z1
y1n
..
y11 .
SoutY
1
37
L1 L
2
L2
L1
2
N2
Y1
X2
Scan Path
...
...
..
.
..
.
.~~
e1m
Sin
AC2
.
Z12y
21
y2m .
Y2
B
C1
e21
![Page 38: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/38.jpg)
SRL Using Two-Port L2*
D = DI
C = CK1
S = I = D2
A = CK2
G1
G3
G4
.
. ..
L*
L*
38
G2
G8
G7
G5
G6
..
.
B = CK4
D* = D3
C* = CK3
(a) Gate model
![Page 39: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/39.jpg)
SRL Using Two-Port L2*
D1
CK1
D2
CK2
L1
Q L1
Q L*
L*
.
39
CK2 Q
D1
CK1
D2
CK2
L2
Q L2
L*
(b) Symbol
![Page 40: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/40.jpg)
Single-Latch LSSD With L2* Latches
N1
D1CK1
D2CK2
L1
D1CK1
CK2
L1
Y2
X1
D2
Z1e
11
e1n
... ...
y11
y1n
SRL
Y1
L*
L*
.
.
40
CK2
N2
D1CK1
D2
CK2
D1CK1
D2
CK2
L*
L*
y2n
y21
Y2
X2
CA
...
Z2
e21
e2n
C*B
Sin
Sout
...
Y1
.
.
.
![Page 41: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/41.jpg)
LSSD Design Rules
1. Internal storage elements must be polarity-hold latches.
2. Latches can be controlled by 2 or more non-overlapping clocks that satisfy:
– A latch X may feed the data port of another
41
– A latch X may feed the data port of another latch Y iff the clock that sets the data into Y does not clock X.
– A latch X may gate a clock C to produce a gated clock Cg , which drives another latch Y iff Cg , or any other clock C1g , produced from Cg , does not clock X.
![Page 42: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/42.jpg)
LSSD Design Rules (contd.)
3. There must exist a set of clock primary inputs from which the clock inputs to all SRLs are controlled either through (1) single-clock distribution tree, or (2) logic that is gated by SRLs and/or non-clock primary inputs. In addition, the following conditions must hold:
42
must hold:
– All clock inputs to SRLs must be OFF when clock PIs are OFF.
– Any SRL clock input must be controlled from one or more clock PIs.
– No clock can be ANDed with either the true or the complement of another clock.
![Page 43: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/43.jpg)
LSSD Design Rules (contd.)
4. Clock PIs cannot feed the data inputs to latches, either directly or through combinational logic.
5. Every system latch must be part of an SRL; each SRL must be part of some scan chain.
6. A scan state exists under the following
43
6. A scan state exists under the following conditions:
– Each SRL or scan-out PO is a function of only the preceding SRL or scan-in PI in its scan chain during the scan operation.
– All clocks except the shift clocks are disabled at the SRL inputs.
![Page 44: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/44.jpg)
LSSD Design Rules (contd.)
7. Any shift clock to an SRL can be turned ON or OFF by changing the corresponding clock PI.
– A network that satisfies rules 1-4 is level-sensitive.
– Race-free operation is guaranteed by rules
44
– Race-free operation is guaranteed by rules 2(1) & 4.
– Rule 3 allows a tester to turn off system clocks and use the shift clocks to force data into and out of the scan chain.
– Rules 5 & 6 are used to support scan.
![Page 45: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/45.jpg)
Advantages With LSSD
• Correct operation independent of AC characteristics.
• Reducing FSM to C/L as far as testing is concerned.
45
• Eliminating hazards & races; simplifying test generation and fault simulation.
![Page 46: Design for Testability - Indian Institute of Technology ... · Ad-Hoc DFT Methods • Good design practices learned through experience are used as guidelines: – Don’t-s and Do-s](https://reader030.vdocument.in/reader030/viewer/2022041112/5f1691a3ac197a63d9235169/html5/thumbnails/46.jpg)
Problems With LSSD
• Design rules imposed on designers --- no freedom to vary from the overall schemes, and higher design and hardware costs (4-20% more h/w & 4 extra pins).
• No asynchronous designs.
• Sequential routing of latches can introduce irregular
46
• Sequential routing of latches can introduce irregular structures.
• Faults changing combinational function to sequential may cause trouble, e.g., bridging, CMOS stuck-open.
• Slow test application; normal-speed testing is impossible.
• Not good for memory intensive designs.