Chapter 2 <1>
Digital Design and Computer Architecture, 2nd Edition
Part 4
David Money Harris and Sarah L. Harris
2
Classification of Digital Circuits1. Combinational– no memory– outputs depend only on the present inputs– expressed by Boolean functions
2. Sequential– storage elements + logic gates– the content of the storage elements define the state of
the circuit– outputs are functions of both inputs and current state – state is a function of previous inputs– >> So outputs not only depend on the present inputs but
also the past inputs
3
Combinational Circuits
§ n input bits è 2n possible binary input combinations§ For each possible input combination, there is one
possible output value § truth table
§ Boolean functions (with n input variables)
§ Examples: adders, subtractors, comparators, decoders, encoders, multiplexers.
Combinationalcircuit
(logic gates)
n binaryinputs
m binaryoutputs
4
Analysis & Design of Combinational Logic
• Analysis: to find out the function that a given circuit implements– We are given a logic circuit and– we are expected to find out
1. Boolean function(s)2. Truth table3. A possible explanation of the circuit operation
(i.e. what it does)
5
Analysis of Combinational Logic
• First, make sure that the given circuit is, indeed, combinational.– Verifying the circuit is combinational
üNo memory elementsüNo feedback paths (connections)
• Second, obtain a Boolean function for each output or the truth table
• Finally, interpret the operation of the circuit from the derived Boolean functions or truth table– What is it the circuit doing?
• Addition, subtraction, multiplication, comparison etc.
6
Obtaining Boolean Function
abc
abc
ab
ac
bc
F1
F2
T1
T2
T3
T4
Example
7
Example: Obtaining Boolean Function• Boolean expressions for named wires
§ T1 = abc§ T2 = a + b + c§ F2 = § T3 = § T4 = T3T2§ F1 = T1 + T4
= = ==
8
Example: Obtaining Boolean Function• Boolean expressions for named wires
§ T1 = abc§ T2 = a + b + c§ F2 = ab + ac + bc§ T3 = F2’ = (ab + ac + bc)’§ T4 = T3T2 = (ab + ac + bc)’ (a + b + c)§ F1 = T1 + T4
= abc + (ab + ac + bc)’ (a + b + c)= abc + ((a’ + b’)(a’ + c’)(b’ + c’)) (a + b + c)= abc + ( (a’ + a’c’ + a’b’ + b’c’)(b’ + c’) ) (a + b + c)= abc + (a’b’ + a’c’ + a’b’c’ + b’c’) (a + b + c)= abc + (a’b’ + a’c’ + b’c’) (a + b + c)
9
Example: Obtaining Boolean Function
• Boolean expressions for outputs§ F2 = ab + ac + bc§ F1 = § F1 = § F1 = § F1 =
10
Example: Obtaining Boolean Function
• Boolean expressions for outputs§ F2 = ab + ac + bc§ F1 = abc + (a’b’ + a’c’ + b’c’) (a + b + c)§ F1 = abc + a’b’c + a’bc’ + ab’c’§ F1 = a(bc + b’c’) + a’(b’c + bc’)§ F1 = a(b Å c)’ + a’(b Å c)§ F1 = ( a Å b Å c ) : Odd Function
11
Example: Obtaining Truth Table
a b c T1 T2 T3 T4 F2 F1
0 0 0 0 0 1 00 0 1 0 1 1 10 1 0 0 1 1 10 1 1 0 1 0 01 0 0 0 1 1 11 0 1 0 1 0 01 1 0 0 1 0 01 1 1 1 1 0 0
sumcarryF1 = a Å b Å cF2 = ab + ac + bc
12
Example: Obtaining Truth Table
a b c T1 T2 T3 T4 F2 F1
0 0 0 0 0 1 0 0 00 0 1 0 1 1 1 0 10 1 0 0 1 1 1 0 10 1 1 0 1 0 0 1 01 0 0 0 1 1 1 0 11 0 1 0 1 0 0 1 01 1 0 0 1 0 0 1 01 1 1 1 1 0 0 1 1
sumcarry
This is what we call full-adder (FA)
F1 = a Å b Å cF2 = ab + ac + bc
13
Design of Combinational Logic• Design Procedure:– We start with the verbal specification about what
the resulting circuit will do for us (i.e. which function it will implement)• Specifications are often verbal, and very likely incomplete
and ambiguous (if not even faulty)• Wrong interpretations can result in incorrect circuit
– We are expected to find 1. Boolean function(s) (or truth table) to realize the desired
functionality2. Logic circuit implementing the Boolean function(s) (or the
truth table)
14
Possible Design Steps
1. Find out the number of inputs and outputs2. Derive the truth table that defines the required
relationship between inputs and outputs3. Obtain a simplified Boolean function for each
output4. Draw the logic diagram (enter your design into
CAD)5. Verify the correctness of the design
15
Design Constraints• From the truth table, we can obtain a variety of
simplified expressions, all realizing the same function.
• Question: which one to choose?• The design constraints may help in the selection
process• Constraints:– number of gates– propagation time of the signal all the way from the inputs
to the outputs– number of inputs to a gate– number of interconnections– power consumption– driving capability of each gate
16
Example: Design Process
• BCD-to-2421 Converter• Verbal specification:
– Given a Binary Coded Decimal (BCD) digit (i.e. {0, 1, …, 9}), the circuit computes 2421 code equivalent of the decimal number
• Step 1: how many inputs and how many outputs?– 4 inputs and 4 outputs
• Step 2:– Obtain the truth table– 0000 à 0000– 1001 à 1111– etc.
17
BCD-to-2421 Converter• Truth Table
Inputs OutputsA B C D x y z t0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1
Binary coded decimal (BCD) is a system of writing numerals that assigns a four-digit binary code to each digit 0 through 9 in a decimal (base-10) numeral. The four-bit BCD code for any particular single base-10 digit is its representation in binary notation, as follows:
0 = 00001 = 00012 = 00103 = 00114 = 01005 = 01016 = 01107 = 01118 = 10009 = 1001
Numbers larger than 9, having two or more digits in the decimal system, are expressed digit by digit. For example, the BCD rendition of the base-10 number 1895is
0001 1000 1001 0101
2421 Code
• a weighted code. • The weights assigned to the four digits are 2, 4, 2, and 1.
• The 2421 code is the same as that in BCD from 0 to 4; however, it differs from 5 to 9.
• For example, in this case the bit combination 0100 represents decimal 4; whereas the bit combination 1101 is interpreted as the decimal 7, as obtained from (2 ×1) + (1 ×4) + (0 ×2) + (1 ×1) = 7
• This is also a self-complementary code, • that is, the 9’s complement of the decimal number is
obtained by changing the 1s to 0s and 0s to 1s.
20
BCD-to-2421 Converter• Truth Table
Inputs OutputsA B C D x y z t0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1
21
BCD-to-2421 Converter• Truth Table
Inputs OutputsA B C D x y z t0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 00 0 1 1 0 0 1 10 1 0 0 0 1 0 00 1 0 1 1 0 1 10 1 1 0 1 1 0 00 1 1 1 1 1 0 11 0 0 0 1 1 1 01 0 0 1 1 1 1 1
22
BCD-to-2421 Converter
10
11
01
00
10110100CD
AB
• Step 3: Obtain simplified Boolean expression for each output
• Output x:A B C D x
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
The rest X
x =
23
BCD-to-2421 Converter
11
1110
0000
10
11
01
00
10110100CD
AB
• Step 3: Obtain simplified Boolean expression for each output
• Output x:A B C D x
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
The rest Xx x x xxx
24
BCD-to-2421 Converter
11
1110
0000
10
11
01
00
10110100CD
AB
• Step 3: Obtain simplified Boolean expression for each output
• Output x:
x = BD + BC + A
A B C D x
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
The rest Xx x x xxx
25
Boolean Expressions for OutputsCD
AB 00 01 11 1000
01
11
10
CDAB 00 01 11 10
00
0111
10
• Output y:
• Output z:
A1 B C D y z
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 1
1 0 0 1 1 1
The rest X X
y =z =
26
Boolean Expressions for OutputsCD
AB 00 01 11 1000 0 0 0 001 1 0 1 111 X X X X10 1 1 X X
CDAB 00 01 11 10
00 0 0 1 101 0 1 0 011 X X X X10 1 1 X X
• Output y:
• Output z:
A B C D y z
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 1
1 0 0 1 1 1
The rest X X
y =z =
27
Boolean Expressions for OutputsCD
AB 00 01 11 1000 0 0 0 001 1 0 1 111 X X X X10 1 1 X X
CDAB 00 01 11 10
00 0 0 1 101 0 1 0 011 X X X X10 1 1 X X
• Output y:
• Output z:
A B C D y z
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 1
1 0 0 1 1 1
The rest X X
y = A + BD’ + BCz = A + B’C + BC’D
Boolean Expressions for Outputs
CDAB 00 01 11 10
00
01
1110
• Output t:A B C D T
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
The rest X
t =
29
Boolean Expressions for Outputs
• Step 4: Draw the logic diagram
CDAB 00 01 11 10
00 0 1 1 001 0 1 1 011 X X X X10 0 1 X X
t =
x = BC + BD + Ay = A + BD’ + BCz = A + B’C + BC’D
• Output t:A B C D T
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
The rest X
30
Boolean Expressions for Outputs
• Step 4: Draw the logic diagram
CDAB 00 01 11 10
00 0 1 1 001 0 1 1 011 X X X X10 0 1 X X
t = D
x = BC + BD + Ay = A + BD’ + BCz = A + B’C + BC’D
• Output t:A B C D T
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
The rest X
31
Example: Logic DiagramAB
CD
x = BC + BD + A
y = A + BD’ + BC
z = A + B’C + BC’D
t = D
32
Example: Verification
• Step 5: Check the functional correctness of the logic circuit
• Apply all possible input combinations • And check if the circuit generates the correct outputs
for each input combinations• For large circuits with many input combinations, this
may not be feasible.• Statistical techniques may be used to verify the
correctness of large circuits with many input combinations
November 8, 2020Digital System Design 33
Binary Addersn Addition is a vital function in computer systemsn What does an adder do?
¡ Add binary digits¡ Generate carry if necessary¡ Consider carry from previous digit
n Binary adders operate bit-wise¡ A 16-bit adder uses 16 one-bit adders
n Binary adders come in two flavors¡ Half adder : adds two bits and generate result and
carry¡ Full adder : also considers carry input¡ 2 half adders + OR : make one full adder
November 8, 2020Digital System Design 34
Binary Half Adder
n Specification:¡ Design a circuit that adds two bits and generates the sum and a
carryn Outputs:
¡ Two inputs: x, y¡ Two output: S (sum), C (carry)¡ 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10
n The S output represents the least significant bit of the sum.n The C output represents the most significant bit of the sum
or (a carry).
November 8, 2020Digital System Design 35
Implementation of Half Addern the flexibility for implementationn S = x Å yn S = (x+y)(x'+y')n S' = xy+x'y'n S = (C+x'y')'n C = xy = (x'+y')'
n S = x'y+xy'n C = xy
HalfAdder
X
YSC
November 8, 2020Digital System Design 36
Full-Adder
n Specification:¡ A combinational circuit that
forms the arithmetic sum of three bits and generates asum and a carry
n Inputs:¡ Three inputs: x,y,z¡ Two outputs: S, C
n Truth table:
FullAdder
X Y
S
ZC
November 8, 2020Digital System Design 37
Implementation of Full Adder
S=x’y’z+ x’yz’+xyz’+xyz= x Å y Å z
C= xy + xz + yz
Full Adder: Hierarchical Realization• Sum
§ S = x Å y Å z = (x Å y) Å z• Carry
§ C = xyz’ + xyz + xy’z + x’yz= xy + (xy’ + x’y) z = xy + (x Å y) z
• This allows us to implement a full-adder using 2 half adders and 1 OR gate.
HA
z
S
C
HAx
y
S
C C
40
Full Adder: Hierarchical Realization• Sum
§ S = x Å y Å z = (x Å y) Å z• Carry
§ C = xyz’ + xyz + xy’z + x’yz= xy + (xy’ + x’y) z = xy + (x Å y) z
• This allows us to implement a full-adder using 2 half adders and 1 OR gate.
x Å y Å z = S
HA
z
S
C
HAx
y
S
C C
Chapter 2 <41>
A B0 00 11 01 1
0110
SCout0001
S = A Å BCout = AB
HalfAdderA B
S
Cout +
A B0 00 11 01 1
0110
SCout0001
S = A Å B Å CinCout = AB + ACin + BCin
FullAdder
Cin
0 00 11 01 1
00001111
1001
0111
A B
S
Cout Cin+
Symbols for 1-Bit Adders
November 8, 2020Digital System Design 42
Binary Adder
n A binary adder is a digital circuit that producesthe arithmetic sum of two binary numbers.
n A binary adder can be implemented usingmultiple full adders (FAs).
Chapter 2 <53>
A B
S
Cout Cin+N
NN
• Realized by carry propagate adders (CPAs)• Types of CPAs
– Ripple-carry (slow)– Carry-lookahead (fast)– Prefix (faster)
• Carry-lookahead and prefix adders faster for large adders but require more hardware
Symbol
Multibit Adders (CPAs)
November 8, 2020Digital System Design 54
Example:4-bit binary adder
n 4-bit Ripple Carry Adder
n Classical example of standard components¡ Would require truth table with 29 entries!
C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0
Chapter 2 <55>
S31
A30 B30
S30
A1 B1
S1
A0 B0
S0
C30 C29 C1 C0Cout ++++
A31 B31
Cin
• Chain 1-bit adders together• Carry ripples through entire chain• Disadvantage: slow
Ripple-Carry Adder
56
Hierarchical Design Methodologyn The design methodology we used to build carry-ripple
adder is what is referred as hierarchical design.n In classical design, we have:
§ 9 inputs including C0.§ 5 outputs§ Truth tables with 29 = 512 entries§ We have to optimize five Boolean functions with 9 variables each.
n Hierarchical design¡ we divide our design into smaller functional blocks ¡ connect functional units to produce the larger functionality
November 8, 2020Digital System Design 57
Carry Propagationn In any combinational circuit, the signal must propagate through the
gates before the correct output is available in the output terminals. n Total propagation time =
the propagation delay of a typical gate x the number of gate levelsn The longest propagation delay time in a binary adder is the time it
takes the carry to propagate through the full adders. This is because each bit of the sum output depends on the value of the input carry. This makes the binary adder very slow.
November 8, 2020Digital System Design 58
n-bit Carry Ripple Addersn In the expression of the sum Cj must be generated by
the full adder at the lower position j-1.
n The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 tAND/OR = tFA
n Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position, the total propagation delay of the adder is approximately:
Total Propagation delay ~ 2n tAND/OR = n tFA
November 8, 2020Digital System Design 59
FullAdder
X1 Y1
S1
CinCoutFull
Adder
X0 Y0
S0
CinCout C0 =0Full
Adder
X2 Y2
S2
CinCoutFull
Adder
X3 Y3
S3
CinCoutC1C2C3C4
Data inputs to be added
Sum output
4-bit Carry Ripple Adder
Adds two 4-bit numbers:X = X3 X2 X1 X0Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0, Cout = C4 from the most significant position j=3
4-bitAdder
X3 X2 X1 X0
S3 S2 S1 S0
CinCoutC4
Y3 Y2 Y1 Y0
C0 =0
Inputs to be added
Sum Output Total Propagation delay : 4 tFAor 8 tAND/OR (8 gate delays)
November 8, 2020Digital System Design 60
Larger Addersn Example: 16-bit adder using 4 * 4-bit addersn Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing
a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position.
Data inputs to be added X (X0 to X15) , Y (Y0 to Y15)
Sum output S (S0 to S15)
Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder~ 16 tFA or 32 gate delays
4-bitAdder Cin
X3 X2 X1 X0
Cout
C4
S3 S2 S1 S0
C0=0
Y3 Y2 Y1 Y0
4-bitAdder Cin
X3 X2 X1 X0
CoutC8
S3 S2 S1 S0
Y3 Y2 Y1 Y0
4-bitAdder Cin
X3 X2 X1 X0
Cout
C12
S3 S2 S1 S0
Y3 Y2 Y1 Y0
4-bitAdder Cin
X3 X2 X1 X0
Cout
C16
S3 S2 S1 S0
Y3 Y2 Y1 Y0
Chapter 2 <61>
• Compute carry out (Cout) for k-bit blocks using generate and propagate signals
• Some definitions:– Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out
– Generate (Gi) and propagate (Pi) signals for each column:• Column i will generate a carry out if Ai AND Bi are both 1.
Gi = Ai Bi• Column i will propagate a carry in to the carry out if Ai OR Bi is 1.
Pi = Ai + Bi• The carry out of column i (Ci) is:
Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1
Carry-Lookahead Adder (CLA)
November 8, 2020 62
Carry-Lookahead Addern Full adder: Si = Ai Å Bi Å Ci , Ci+1 = Ai Bi + (Ai Å Bi ) Ci
n Create new signals:¡ Gi = Ai Bi “carry generate” for stage i¡ Pi = Ai Å Bi “carry propagate” for stage i
n Full adder equations expressed in terms of Gi and Pi¡ Si = Pi Å Ci
¡ Ci+1 = Gi + Pi Ci
November 8, 2020Digital System Design 63
Carry Lookahead - Equations
n Full adder functionality can be expressedrecursively¡ Si = Pi Å Ci
¡ Ci+1 = Gi + Pi Ci
n Carry of each stage¡ C0 = input carry¡ C1 = G0 + P0C0¡ C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 +
P1P0C0¡ C3 = G2 + P2C2 = … = G2 + P2G1 + P2P1G0 + P2P1P0C0¡ C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
November 8, 2020Digital System Design 64
Carry Lookahead - Circuit
November 8, 2020Digital System Design 65
4-bit Adder with Carry Lookahead
n Complete adder:¡ Same number of stages for
each bitn Drawback?
¡ Increasing complexity of lookahead logic for morebits
Chapter 2 <72>
For N-bit CLA with k-bit blocks:
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
– tpg : delay to generate all Pi, Gi– tpg_block : delay to generate all Pi:j, Gi:j– tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA
block
An N-bit carry-lookahead adder is generally much faster than a ripple-carry adder for N > 16
Carry-Lookahead Adder Delay
November 8, 2020Digital System Design 80
Four-bit adder-subtractor
If v=0 no overflowIf v=1 overflow occurs
• Recall how we do subtraction: Using complementsX – Y = X + (2n – Y) = X + ~Y + 1
• M sets mode: M=0 addition and M=1 subtraction• M is a “control signal” (not “data”) switching between
Add and Subtract
November 8, 2020Digital System Design 81
Overflow Conditions
n Overflow conditions¡ There is no overflow if signs are different (pos + neg, or neg +
pos)¡ Overflow can happen only when both numbers have the same
sign, and¡ If carry into sign position and out of sign position differ¡ Example: 2’s complement signed numbers wih n = 4 bits
¡ Result would be correct with extra position¡ Detected by XOR gate ( output =1 when inputs differ)¡ Can be used as input carry for next adder circuit
+6 0 110+7 0 111---------------------+13 0 1 101
-6 1 010-7 1 001----------------------13 1 0 011
November 8, 2020Digital System Design 82
0000100011
--------0101
235
0100110110
--------1001
OFL
36-7
1111101101
--------1011
-2-3-5
1011011010
--------0111
OFL
-3-67
0000101100
--------1110
2-4-2
1111100100
--------0010
-242
Addition cases and overflow
86
Decoders• A binary code of n bits
– capable of representing 2n distinct elements of coded information
– A decoder is a combinational circuit that converts binary information from n binary inputs to a maximum of 2n unique output lines
2x4 decoder
x
y
d0
d1
d2
d3
x y d0 d1 d2 d3
0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1
• d0 = • d1 =
• d2 = • d3 =
Chapter 2 <87>
2:4Decoder
A1A0
Y3Y2Y1Y000
011011
0 00 11 01 1
0001
Y3 Y2 Y1 Y0A0A10010
0100
1000
• N inputs, 2N outputs• One-hot outputs: only one output HIGH at
once
Decoders
Decoder with Enable Input
2x4 decoder
x
y
d0
d1
d2
d3
e
e x y d0 d1 d2 d3
0 X X 0 0 0 01 0 0 1 0 0 01 0 1 0 1 0 01 1 0 0 0 1 01 1 1 0 0 0 1
88
Combining Decoders
2x4 decoder
y
z
d0d1d2
d3e
2x4 decoder
d4d5
d6
d7e
x
x y z active output0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
• Decoders with enable inputs can be connected together to form a larger decoder circuit. • Figure shows two 2-to-4-line decoders with enable inputs connected to form a 3-to-8-
line decoder. • When x=0, the top decoder is enabled and the other is disabled. The bottom decoder
outputs are all 0’s, and the top four outputs generate minterms 000 to 011. • When x=1, the enable conditions are reversed: The bottom decoder outputs generate
minterms 100 to 111, while the outputs of the top decoder are all 0’s. • This example demonstrates the usefulness of enable inputs in decoders
92
nx2n
Decoder-1
x0
xn-1
d0d1
d2n
-1e
nx2n
Decoder-2e
nx2n
Decoder-2p
e
px2p
Decoder
xn
xn+p-1
Combining Decoders
d2n+p-1
-1
93
Decoder as a Building Block• A decoder provides the 2n minterms of n input
variables
2x4 decoder
x
y
d0 = x’y’d1 = x’yd2 = xy’
d3 = xy
• We can use a decoder and OR gates to realize any Boolean function expressed as sum of minterms– Any combinational circuit with n inputs and m outputs can be
realized using§ an n-to-2n line decoder§ and m OR gates.
94
Decoder as a Building Block-ROM
3x8 decoder
x
y
d0 = x’y’z’d1 = x’y’zd2 = x’yz’
d3 = x’yzd4 = xy’z’d5 = xy’zd6 = xyz’
d7 = xyz
z
F2 F1 F0
95
Decoder as a Building Block-ROM
3x8 decoder
x
y
z
1 0 0
0 0 1
1 0 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
F2 F1 F0
96
Example: Decoder as a Building Block• Full adder
– C = xy + xz + yz– S = x Å y Å z
3x8 decoder
x
y
z
012
34567
S
C
97
Encoders• An encoder is a combinational circuit that
performs the inverse operation of a decoder– number of inputs: 2n
– number of outputs: n– the output lines generate the binary code
corresponding to the input value• Example: n = 2
d0 d1 d2 d3 x y
1 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1
98
Priority Encoder• Problem with a regular encoder:
– only one input can be active at any given time– the output is undefined for the case when more than
one input is active simultaneously.>> Priority encoder:
– there is a priority among the inputs
1111XXX
10101XX
110001X
1000001
0XX0000
Vbad3d2d1d0
99
Priority Encoder• if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence. • In addition to the two outputs a and b , the circuit has a third output
designated by V ; this is a valid bit indicator that is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no valid input and V is equal to 0. The other two outputs are not inspected when V equals 0 and are specified as don’t-care conditions.
• Priority encoder:
1111XXX
10101XX
110001X
1000001
0XX0000
Vbad3d2d1d0
100
4-bit Priority Encoder• In the truth table
§ X for an input variable represents both 0 and 1. § Good for condensing the truth table§ Example: X100 à (0100, 1100)
§ This means d1 has priority over d0
§ d3 has the highest priority§ d2 has the next§ d0 has the lowest priority
§ V = ?§ The condition for output V is an OR function of
all the input variables.
101
Maps for 4-bit Priority Encoderd2d3
d0d1 00 01 11 1000011110
a =
d2d3
d0d1 00 01 11 1000011110
b =
102
Maps for 4-bit Priority Encoderd2d3
d0d1 00 01 11 1000 X 1 1 101 0 1 1 111 0 1 1 110 0 1 1 1 a =
d2d3
d0d1 00 01 11 1000 X 1 1 001 1 1 1 011 1 1 1 010 0 1 1 0
b =
103
4-bit Priority Encoder: Circuit
d0
d1
d2
d3 b
a
V
a = d2 + d3
b = d1d2’ + d3
V = d0 + d1 + d2 + d3
Chapter 2 <104>
• Selects between one of N inputs and directs it to a single output.
• log2N-bit select input – control input• Example: 2:1 Mux
Y0 00 11 01 1
0101
0000
0 00 11 01 1
1111
0011
0
1
S
D0Y
D1
D1 D0S Y01 D1
D0
S
Multiplexer (Mux)
Chapter 2 <105> 2-<105>
• Logic gates– Sum-of-products form
Y
D0
S
D1
D1
Y
D0
S
S 00 01
0
1
Y
11 10D0 D1
0
0
0
1
1
1
1
0
Y = D0S + D1S
• Tristates– For an N-input mux, use N
tristates– Turn on exactly one to
select the appropriate input
Multiplexer Implementations
109
4-to-1-Line Multiplexer• 4 input lines: I0, I1, I2, I3• 1 output line: Y• 2 selection lines: S1, S0.
11
01
10
00
YS0S1
Y = ?
Interpretation:• In case S1 = 0 and S0 = 0, Y selects I0
• In case S1 = 0 and S0 = 1, Y selects I1
• In case S1 = 1 and S0 = 0, Y selects I2
• In case S1 = 1 and S0 = 1, Y selects I3
110
4-to-1-Line Multiplexer: Circuit
S0
I0
Y
I1
I2
I3
S1
I0
I1MUX Y
S1
0
1
I2
I3
2
3
S0
Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3
111
Multiplexer with Enable Input• To select a certain building block we use enable
inputs
A
BMUX Y
S1
0
1
C
D
2
3
S0
E
E S Y1 XX0 00 A0 01 B0 10 C0 11 D
112
Multiple-Bit Selection Logic 1/2• A multiplexer is also referred as a “data selector”• A multiple-bit selection logic selects a group of
bits
A =
B =
Y =
A
B
MUX Y
S
0
1
2
2
2
1
E
Multiple-bit Selection Logic 2/2
A
B
MUX Y
S
0
1
2
2
2
1
E
E S Y1 X all 0’s0 0 A0 1 B
MUX
0
1
y0
a0
b0
E
S
MUX
0
1
y1
a1
b1
113
114
Design with Multiplexers 1/2• Reminder: design with decoders• Half adder
– C = xy = S(3)
– S = x Å y = x’y + xy’ = S(1, 2)
2x4 decoder
x
y
0
1
2
3
S
C
• A closer look will reveal that a multiplexer is nothing but a decoder with OR gates
115
Design with Multiplexers 2/2• 4-to-1-line multiplexer
I0
I1MUX Y
S1
0
1
I2
I3
2
3
S0
• Y = S1’S0’ I0 + S1’S0 I1 + S1S0’ I2 + S1S0 I3
• Y = x’y’ I0 + x’y I1 + xy’ I2 + xyI3
• Y =
• S1à x• S0à y• S1’S0’ = x’y’, • S1’S0 = x’y,• S1S0’ = xy’, • S1S0 = xy
116
Example: Design with Multiplexers• Example: S = S(1, 2)
I0
I1MUX Y
S1
0
1
I2
I3
2
3
S0
=
=
=
=
x y
117
Example: Design with Multiplexers• Example: S = S(1, 2)
I0
I1MUX Y
S1
0
1
I2
I3
2
3
S0
=
=
=
=
x y
0
1
1
0
118
Design with Multiplexers Efficiently
• More efficient way to implement an n-variable Boolean function1. Use a multiplexer with n-1 selection inputs2. First (n-1) variables are connected to the
selection inputs3. The remaining variable is connected to data
inputs
• Example: Y = S(1, 2)= I0
= I1
Y = S’ I0 + S I1MUX
0
1
x
Y = x’ I0 + x I1
119
Design with Multiplexers Efficiently
• More efficient way to implement an n-variable Boolean function1. Use a multiplexer with n-1 selection inputs2. First (n-1) variables are connected to the
selection inputs3. The remaining variable is connected to data
inputs
• Example: Y = S(1, 2)y = I0
y' = I1
Y = S’ I0 + S I1MUX
0
1
x
Y = x’ I0 + x I1
120
Design with MultiplexersGeneral procedure for n-variable Boolean function F(x1, x2, ..., xn)1. The Boolean function is expressed in a truth table2. The first (n-1) variables are applied to the selection inputs of
the multiplexer (x1, x2, ..., xn-1)3. For each combination of these (n-1) variables, evaluate the
value of the output as a function of the last variable, xn.• 0 , 1 , xn , xn’
4. These values are applied to the data inputs in the proper order.
121
Example: Design with Multiplexers• F(x, y, z) = S(1, 2, 6, 7)
§ F = x’y’z + x’yz’ + xyz’ + xyz§ Y = S1’S0’ I0 + S1’S0 I1 + S1S0’ I2 + S1S0 I3
§ I0 = I1 = I2 = I3 =
111
011
101
001
110
010
100
000
Fzyx
F =
F =
F =
F =
122
Example: Design with Multiplexers• F(x, y, z) = S(1, 2, 6, 7)
§ F = x’y’z + x’yz’ + xyz’ + xyz§ Y = S1’S0’ I0 + S1’S0 I1 + S1S0’ I2 + S1S0 I3
§ I0 = z I1 = z’ I2 = 0 I3 = 1
1111
1011
0101
0001
0110
1010
1100
0000
Fzyx
F =z
F =z’
F =0
F =1
123
Example: Design with Multiplexers
MUX
0
1
2
3
x y
F = x’y’z + x’yz’ + xy
F = x’y’z + x’yz’ + xyz’ + xyz
F = z when x = 0 and y = 0F = z’ when x = 0 and y = 1F = 0 when x = 1 and y = 0F = 1 when x = 1 and y = 1
z
z'
0
1
Design with Multiplexers
MUX
0
1
2
3
x y
I0I1
I2
I3
x‘y’(I0) + x‘y(I1) + xy’(I2) + xy(I3)
F1=x‘y’(0) + x‘y(1) + xy’(1) + xy(0)
F2=x‘y’(z) + x‘y(z’) + xy’(0) + xy(1)
F=x‘y’(P(z,t,q,w)) + x‘y(Q(z,t,q,w)) + xy’(R(z,t,q,w)) + xy(S(z,t,q,w))
124
F
...
Design with Multiplexers
MUX
0
1
2
3
x y
I0I1
I2
I3
F=x‘y’(P(z,t,q,w)) + x‘y(Q(z,t,q,w)) + xy’(R(z,t,q,w)) + xy(S(z,t,q,w))
125
z
t
q
w
Combinational Circuit F
126
Combining Multiplexers
MUX
0
1
2
3
MUX
0
1
2
3
S2 S1MUX
0
1
S2 S1
S0
Example
MUX0
1
X0
MUX0
1
X1
MUX0
1
X1X0
MUX0
1
X2
MUX0
1
X2X0
MUX0
1
X2X1
MUX0
1
X2X1X0
C0
C1
C2C3
C4C5
C6C7
127
Example- 2 Level ROM
p x2n ROM0
z0 z1 zp-1
p x2n ROM1
z0 z1 zp-1
p x2n ROM2k-1
z0 z1 zp-1
x0x1
xn-1
xnXn+1
Xn+k-1
0 1 2k-1 0 1 2k-1 0 1 2k-1
z0 z1 zp-1
128
MUX MUX MUX
Example- 2 Level ROM
p x2n ROM0
z0 z1 zp-1
p x2n ROM1
z0 z1 zp-1
p x2n ROM2k-1
z0 z1 zp-1
x0x1
xn-1
xnXn+1
Xn+k-1
0 1 2k-1 0 1 2k-1 0 1 2k-1
z0 z1 zp-1
129
MUX MUX MUX
Example- 2 Level ROM
p x2n ROM0
z0 z1 zp-1
p x2n ROM1
z0 z1 zp-1
p x2n ROM2k-1
z0 z1 zp-1
x0x1
xn-1
xnXn+1
Xn+k-1
0 1 2k-1 0 1 2k-1 0 1 2k-1
z0 z1 zp-1
130
MUX MUX MUX
Example- 2 Level ROM
p x2n ROM0
z0 z1 zp-1
p x2n ROM1
z0 z1 zp-1
p x2n ROM2k-1
z0 z1 zp-1
x0x1
xn-1
XnXn+1
Xn+k-1
0 1 2k-1 0 1 2k-1 0 1 2k-1
z0 z1 zp-1
0 1 1
131
MUX MUX MUX
0 1 • • • • • 1
Example- 2 Level ROM
p x2n ROM0
z0 z1 zp-1
p x2n ROM1
z0 z1 zp-1
p x2n ROM2k-1
z0 z1 zp-1
x0x1
xn-1
xnXn+1
Xn+k-1
0 1 2k-1 0 1 2k-1 0 1 2k-1
z0 z1 zp-1
1 0 0132
MUX MUX MUX
1 0 • • • • • 0
Example- 2 Level ROM
p x2n ROM0
z0 z1 zp-1
p x2n ROM1
z0 z1 zp-1
p x2n ROM2k-1
z0 z1 zp-1
x0x1
xn-1
xnXn+1
Xn+k-1
0 1 2k-1 0 1 2k-1 0 1 2k-1
133
MUX MUX MUX
1 1 • • • • 1 0
z0 z1 zp-1
1 1 0
134
Three-State Buffers• A different type of logic element
– Instead of two states (i.e. 0, 1), it exhibits three states (0, 1, Z)
– Z (Hi-Z) is called high-impedance– When in Hi-Z state, the circuit behaves like an open
circuit: the output appears to be disconnected, and the circuit has no logic significance
A
C
Y = A if C = 1Y = Hi-Z if C = 0
input
controlinput
135
3-State Buffers• Remember that we cannot connect the outputs of
other logic gates.• We can connect the outputs of three-state buffers– provided that no two three-state buffers drive the same
wire to opposite 0 and 1 values at the same time.
C A Y
0 X Hi-Z
1 0 0
1 1 1
Example- 3 State MUX
n x2n
Decoderz0 z1 z2
n-1
x0x1
xn-1
y0
y1
y2n
-1
Y
136
137
Multiplexing with 3-State BuffersA
S
B
TA
TB
Y
11Z1X1
00Z0X1
1Z1X10
0Z0X00
YTBTABAS
It is, in fact, a 2-to-1-line MUX
138
Two Active Outputs - 1A
C1
B
TA
TB
Y
C0
What will happen if C1 = C0 = 1?
11111
00011
1011
0111
YBAC0C1
ZXX00
11X01
00X01
1X110
0X010
139
Design Principle with 3-State Buffers• Designer must be sure that only one control input
must be active at a time.– Otherwise the circuit may be destroyed by the large
amount of current flowing from the buffer output at logic-1 to the buffer output at logic-0.
2x4 decoder
S1
S0
E
x
y
w
z
t
Example- 3 State Buffer & ROMp x2n ROM
1z0 z1 zp-1
p x2n ROM2
z0 z1 zp-1
p x2n ROM2k
z0 z1 zp-1
x0x1
xn-1
140
k x2
kRO
Mxnxn+1
xn+k-1
z0 z1 zp-1
141
Busses with 3-State Buffers• There are important uses of three-state buffers
CPU Memory
I/O Device
142
Demultiplexer• A demultiplexer is a combinational circuit
– it receives information from a single input line and directs it to one of 2n output lines
– It has n selection lines as to which output will get the input
2x4 decoder
x
y
d0
d1
d2
d3
e
d0
d1
d2
d3
e
x, y
d0 = e when x = 0 and y = 0d1 = e when x = 0 and y = 1d2 = e when x = 1 and y = 0d3 = e when x = 1 and y = 1
Demultiplexer
0
0
0
1
1
1
e
x1 x0
143
Demultiplexer
e
x2
144
0
0
0
1
1
1
0
0
0
1
1
1
0
1
x1 x0
Demultiplexer
145
0
0
1
1
0
0
1
1
x0
Chapter 2 <146>
Symbol Implementation
+
A B
-
YY
A B
NN
N
N N
N
N
Symbols: Subtracter
Chapter 2 <147>
Symbol ImplementationA3B3A2B2A1B1A0B0
Equal=
A B
Equal
44
Symbols: Equality Comparator
Chapter 2 <148> Copyright © 2007 Elsevier 5-<148>
A < B
-
BA
[N-1]
N
N N
Symbols: Less Than Comparator
Chapter 2 <149> Copyright © 2007 Elsevier 5-<149>
ALU
N N
N3
A B
Y
F
F2:0 Function000 A & B001 A | B010 A + B011 not used100 A & ~B101 A | ~B110 A - B111 SLT
Arithmetic Logic Unit (ALU)
Chapter 2 <150> Copyright © 2007 Elsevier 5-<150>
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
ZeroExtend
F2:0 Function000 A & B001 A | B010 A + B011 not used100 A & ~B101 A | ~B110 A - B111 SLT
ALU Design
Chapter 2 <151>
Compare delay of: 32-bit ripple-carry, carry-lookahead, and prefix adders• CLA has 4-bit blocks• 2-input gate delay = 100 ps; full adder delay = 300 ps
tripple = NtFA= 32(300 ps) = 9.6 ns
tCLA = tpg + tpg_block+ (N/k – 1)tAND_OR + ktFA= [100 + 600 + (7)200 + 4(300)] ps= 3.3 ns
tPA = tpg + log2N(tpg_prefix ) + tXOR= [100 + log232(200) + 100] ps= 1.2 ns
Adder Delay Comparisons
Chapter 2 <152> Copyright © 2007 Elsevier 5-<152>
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
ZeroExtend
• Configure 32-bit ALU for SLT operation: A = 25 and B = 32
Set Less Than (SLT) Example
Chapter 2 <153> Copyright © 2007 Elsevier 5-<153>
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
ZeroExtend
• Configure 32-bit ALU for SLT operation: A = 25 and B = 32– A < B, so Y should be 32-bit
representation of 1 (0x00000001)– F2:0 = 111
– F2 = 1 (adder acts as subtracter), so 25 - 32 = -7
– -7 has 1 in the most significant bit (S31 = 1)
– F1:0 = 11 multiplexer selects Y = S31 (zero extended) = 0x00000001.
Set Less Than (SLT) Example
Chapter 2 <154> Copyright © 2007 Elsevier 5-<154>
• Logical shifter: shifts value to left or right and fills empty spaces with 0’s– Ex: 11001 >> 2 =– Ex: 11001 << 2 =
• Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb).– Ex: 11001 >>> 2 =– Ex: 11001 <<< 2 =
• Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end– Ex: 11001 ROR 2 =– Ex: 11001 ROL 2 =
Shifters
Chapter 2 <155>
• Logical shifter:– Ex: 11001 >> 2 = 00110– Ex: 11001 << 2 = 00100
• Arithmetic shifter:– Ex: 11001 >>> 2 = 11110– Ex: 11001 <<< 2 = 00100
• Rotator:– Ex: 11001 ROR 2 = 01110– Ex: 11001 ROL 2 = 00111
Shifters
Chapter 2 <156>
A3:0 Y3:0
shamt1:0
>>
2
4 4
A3 A2 A1 A0
Y3
Y2
Y1
Y0
shamt1:0
00
01
10
11
S1:0
S1:0
S1:0
S1:0
00
01
10
11
00
01
10
11
00
01
10
11
2
Shifter Design
Chapter 2 <157>
• A << N = A × 2N
– Example: 00001 << 2 = 00100 (1 × 22 = 4)– Example: 11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
– Example: 01000 >>> 2 = 00010 (8 ÷ 22 = 2)– Example: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)
Shifters as Multipliers, Dividers
November 8, 2020Digital System Design 158
Binary Multiplicationn Multiplication is achieved by adding a list of shifted
multiplicands according to the digits of the multiplier.
n Ex. (unsigned)11 1 0 1 1 multiplicand (4 bits)
X 13 X 1 1 0 1 multiplier (4 bits)-------- -------------------
33 1 0 1 111 0 0 0 0
______ 1 0 1 1143 1 0 1 1
---------------------1 0 0 0 1 1 1 1 Product (8 bits)
November 8, 2020Digital System Design 159
Binary Multiplicationn An n-bit x n-bit multiplier can be realized in combinational
circuitry by using an array of n-1 n-bit adders where eachadder is shifted by one position.
n For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits.
X3 X2 X1 X0x Y3 Y2 Y1 Y0
----------------------------------------------X3.Y0 X2.Y0 X1.Y0 X0.Y0
X3.Y1 X2.Y1 X1.Y1 X0.Y1X3.Y2 X2.Y2 X1.Y2 X0.Y2
X3.Y3 X2.Y3 X1.Y3 X0.Y3_______________________________________________________________________________________________________________________________________________
P7 P6 P5 P4 P3 P2 P1 P0
Chapter 2 <161>
• Partial products formed by multiplying a single digit of the multiplier with multiplicand
• Shifted partial products summed to form result
Decimal Binary230
42x01010111
5 x 7 = 35
460920+9660
01010101
01010000
x
+0100011
230 x 42 = 9660
multipliermultiplicand
partialproducts
result
Multipliers
Chapter 2 <162>
4 x 4 Multiplier
x B3 B2 B1 B0
A3B0 A2B0 A1B0 A0B0
A3 A2 A1 A0
A3B1 A2B1 A1B1 A0B1
A3B2 A2B2 A1B2 A0B2
A3B3 A2B3 A1B3 A0B3+P7 P6 P5 P4 P3 P2 P1 P0
0
P2
0
0
0
P1 P0P5 P4 P3P7 P6
A3 A2 A1 A0
B0B1
B2
B3
x
A B
P
44
8
Symbol
November 8, 2020Digital System Design 163
Binary Multiplier
n Partial products – AND operations
November 8, 2020Digital System Design 164
4-bit by 3-bit binary multiplier
Chapter 2 <165>
4 x 4 Divider
1
A3000
Q3
1
Q2
B0B1B2B3
R0R1R2R3
A2
1
Q1
A1
1
Q0
A0
+
R B
D
R'
N
CinCout
1 0
R B
DR'N
CoutCin
Legend
A/B = Q + R/BAlgorithm:R’ = 0for i = N-1 to 0R = {R’ << 1. Ai}D = R - Bif D < 0, Qi=0, R’=Relse Qi=1, R’=D
R’=R