LAB BROCHURE
Digital Logic Design LabDEPARTMENT OF ELECTRICAL ENGINEERING
DIGITAL LOGIC DESIGN LABORATORY
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CONTENTS
......................................................................................................................Lab Venue 3.............................................................................................Lab Objectives & Courses 3
.....................................................................................Lab Description & Experiments 4..................................................................................................Hardware Experiments 5
.......................................................................................................Verilog Experiments 6
...............................................................................................................Lab Resources 7
DIGITAL LOGIC DESIGN LABORATORY
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DLD Lab Venue: Computer Interfacing Lab First Floor, Electrical Department
Lab VenueThe Digital Logic Design Lab
(DLD Lab) is one of the most
important and well equipped lab of the Department of Electrical Engineering at University of
Engineering and Technology, Lahore. This lab is conducted at the
Computer Interfacing Lab situated at the first floor of the Electrical Engineering Department.
Scope of the LabThe DLD Lab is for
undergraduate coursework related to
the course EE131. It is one of the core modules of B. Sc. Electrical Engineering therefore the lab has a
significant importance in the department.
Related CoursesThis lab is designed such that the
students get a hands on familiarity
with the concepts they come across in the course EE131 that is the Digital Systems course. This is an
undergraduate course which deals with the basics of digital systems
design and is a core module of the B. Sc. Electrical Engineering coursework as it provides the
prerequisites for advance courses in digital electronics. Because of the
significance of this course the DLD Lab has been carefully designed to meet the course requirement.
Brief Overview of the LabThe Lab is well equipped with
both hardware and software facilities
required by the students to perform the necessary experiments designed for this lab. Details of the lab
equipment has been discussed in a proceeding section.
Experiments are designed in such a way that the students become well aware of the concepts they learn
in the theory sessions. A list of experiments that are conducted in
this lab has also been mentioned in a proceeding section.
Experiments are related to both
digital hardware and Verilog Programming.
Objectives & Courses
DIGITAL LOGIC DESIGN LABORATORY
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Lab Description & Experiments
Lab DescriptionThe Experiments in the
Lab have been divided into
two major portions:
• Hardware Labs
• Hardware Description
Language (Verilog) LabsHardware Labs have
been designed to familiarize students with the Combinational Digital Logic
Design and Sequential Digital Logic Design
through the implementation of Digital Logic Circuits using ICs of basic logic
gates and some simple digital logic circuits.
HDL (Verilog) Labs have been designed to
familiarize students with the HDL based Digital Design Flow. These labs introduce
students with different levels of coding available in
Verilog i.e. Gate level, Dataflow level and Behavioral level. Xilinx ISE
7.1 tools have been used in these labs. Finally, the
skills learnt in the HDL labs are employed to implement some digital
logic circuits on Spartan-3 FPGA, using Xilinx Starter
Kit Development Board.
Expected OutcomesWith the help of the two
threads of the lab
mentioned above, students will have clear understanding of all the
three paradigms of implementation of digital
logic circuits:
• Implementation using ICs for basic logic gates
and simple circuits
• Implementation
through the Development of Dedicated IC(ASIC)
• Implementation
through Reconfigurable Logic (i.e. FPGA)
This makes students adept in basic concepts involved in digital logic
design. The lab contributes a lot to the basic learning of
digital systems.This shows the
indispensability of the
DLD Lab.
List of ExperimentsList of experiments is
given on page 5 and 6. As
mentioned before the lab has two major portions therefore there are two lists
of experiments one related to the hardware labs and
the other related to the hardware description language (verilog) labs. All
these experiments are mandatory and each lab is
followed by specially designed assignments.
A Lab Demonstration
A Digital Chip (inside view)
DIGITAL LOGIC DESIGN LABORATORY
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TITLE TOPICS1 To Verify the Behavior of Logic Gates using Truth Table and
Familiarization with Digital Integrated CircuitsBasic Logic Gates,Truth Table,
Integrated Circuits
2 Implementation of Boolean Function using Logic Gatesand Introduction to Hierarchical Design of Digital Logic Circuits
Boolean Functions,Boolean Algebra,
Hierarchical Design of Digital Logic Circuits
3 Familiarization with the Different Portions of the Datasheet for a Digital IC and Using the Datasheet to Gather Relevant
Information to Utilize the IC as a Component in another Digital Logic Circuit
Datasheet of a Digital Logic IC,Hierarchical Design of Digital Logic Circuits
4 Implementation of 8 bit Binary Comparator using 4 bit Binary Comparators
Binary Comparator,Hierarchical Design of Digital Logic Circuits
5 Implementation of 4bit into 3bit Binary Multiplier using 4bit Binary Adders
Binary Multiplication,Hierarchical Design of Digital Logic Circuits
6 Implementation of BCD Adder using 4bit Binary Adders, 4 to 7 Segment Decoder and 2Digit 7 Segment Display
BCD addition, Hierarchical Design of Digital Logic Circuits
7 Implementing a Full Adder using(a) Decoder
(b) Multiplexer
Implementation of Boolean function using Decoder,
Implementation of Boolean function using Multiplexer
8 Flip Flops Different Types of Flip Flops
9 To study the fundamentals of basic counters and to construct various types of counters
Counters
Hardware Experiments
DIGITAL LOGIC DESIGN LABORATORY
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TITLE TOPICS1 Introduction to HDL based Digital Design Methodology HDL based Digital Design Flow using
Verilog,
Introduction to Outsourcing Business Model
2 Introduction to Basic Syntax of Verilog and Gate level Modeling
through implementation of half adder at gate level and its simulation using Xilinx ISE tools
Basic Concepts of Verilog, Modules and Ports, Gatelevel coding in Verilog,
3 Introduction to the concepts of Instantiation and Hierarchical Design in Verilog through the implementation of full adder
using the previously designed half adder modules
Hierarchical Design in Verilog
4 Introduction to the Concept of Vectors and Introduction to Dataflow modeling through implementation of half adder and
full adder at dataflow level
Vectors in Verilog,Dataflow level coding in Verilog
5 Consolidation of the concepts of Dataflow level modeling and Introduction to the concept of Synthesis by the CAD tool
Dataflow level coding in Verilog, Logic Synthesis
6 Introduction to Behavioral modeling through implementation of half adder and full adder at behavioral level.
Behavioral level coding in Verilog
7 Introduction to if else statement and case statement in Behavioral modeling through implementation of Multiplexer
if else and case statements in Verilog
8 Introduction to the Concepts of Sequential Circuit and a TestBench module (Stimulus Block)
Sequential circuits in Verilog, Concept of Testbench module in Verilog
9 Behavioral Level Coding of Basic Sequential Circuits and Consolidation of the concepts of TestBench module (Stimulus
Block)
Sequential circuits in Verilog
10 Introduction to Field Programmable Gate Array(FPGA) and Steps involved in its Programming
Need for Reconfigurable Logic, Xilinx ISE Tools for Programming the Xilinx FPGAs
Verilog Experiments
DIGITAL LOGIC DESIGN LABORATORY
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Lab Resources
Hardware ResourcesThe lab is fully
equipped with all the
hardware required to conduct the above mentioned experiments.
The hardware resources of the lab are:
• Pentium-IV PCs (with MS WinXp OS)
• Hardware trainers for
logic circuit design and analysis
• Electronic Chips of all digital gates
• Spartan-III FPGA
board kits
• Power Supplies
These resources allow the students to have a
hands on experience of basic digital logic design concepts. This activity
greatly leverages what the students learn in the theory
sessions.
Software ResourcesThe lab also consists of
the software resources
required by the students namely:
• Veriwell
• ModelSim
• Xilinx IDE
• Matlab
Software resources are equally important as
hardware resources are. These software resources are sufficient for the
students to perform experiments. These
softwares provide the students with the necessary platform to work
on HDL that is the Verilog. These softwares are also
required to work with the sophisticated hardwares like Spartan-III FPGA
boards.The lab has all the
resources whether related to hardware or software so that the students become
adept in the basic field of digital electronics.
Students are encouraged to use the lab resources to perform
activities and experiments which help
them strengthen their concepts.
Lab StaffLike other labs of the
department there is a trained and able staff
consisting of skilled lab technicians that take care
of the lab equipment. They also guide
students about handling
the lab equipment and the precautionary measures
required for the students while working in the lab.
A Digital Circuit Board
A Simulation
DIGITAL LOGIC DESIGN LABComputer Interfacing Lab
1st Floor, Department of Electrical EngineeringUNIVERSITY OF ENGINEERING & TECHNOLOGY, LAHORE-54890, PAKISTAN.Ph: + 92 42 9029229, Fax: + 92 42 9250224url: www.uet.edu.pk