Stanford University
Directed Self-Assembly for the Semiconductor Industry
H.-S. Philip Wong, Chris Bencher#
Linda He Yi, Xin-Yu Bao, Li-Wen ChangStanford University, #Applied Materials
Stanford University
2 July 9, 2012
J.W. Jeong...C.A. Ross., Nano Lett. 2011, 11, 4095–4101 [MIT]
R. Ruiz…P. Nealey, Science 321, 936 (2008) [Hitachi, Wisconsin]
C. Tang … C. Hawker, Science, p. 429 (2008). [UCSB]
J. Y. Cheng et al., Adv. Mater. 2008, 20, 3155–3158 [IBM]
Stanford University
Department of Electrical Engineering2012.02.13H.-S. Philip Wong3
Nangate cell library: http://www.nangate.com
J. Stork, TI (2007), Stanford seminar
Device Fabrication
Does not require long range order
Stanford University
Department of Electrical Engineering2012.02.13H.-S. Philip Wong4
Nangate cell library: http://www.nangate.com
J. Stork, TI (2007), Stanford seminar
Device FabricationRequires
Multiple-pitch
Multiple-ordering
Multiple-size
One layer process
Single material system
Industrial compatible process
Transparent to circuit designers
Technical requirement
Practicality (i.e. cost)
Why don’t we place the shapes where we want
them to be?
Adapted from: ucsusa.org
5
Stanford University
6 July 9, 2012
Directed Self-Assembly by Physical Confinement
200nm
120 nm
230 nm
2 rows of holes
L.-W. Chang…H.-S. P. Wong, IEDM , p. 879, 2009
PS-b-PMMA PMMA PSGuiding Template: Physical Confinement
Stanford University
7 July 9, 2012
Control of DSA with Small Guiding Templates Size Comparable to self-assembly dimensions
200nm
AB
60x110nm200nm
ABC
70x145nm75nm
200nm
Flexible and precise control knobs:Thickness, size, density
Square lattice Rhombic lattice92nm 104 nm 108 nm 126 nm 136 nm
scale bar
Stanford University
8 July 9, 2012
Small Templates
...
hole patterns
...
Canonical templates
Canonical templates: Simplest template set to form desired
patterns Manufacturable with current litho tech.
Design Rules: The standards to disassemble a layout to
canonical templates and reassemble canonical templates to pattern devices
Contact hole layout Design A Design B
Alphabet table
Stanford University
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July 9, 2012
Square Template DSA Pattern Size Analysis
20 25 30 35 400%
10%
20%
30%
40%
Coun
t
Hole Size (nm)
126 nmMean: 30.3 nmSD: 2.1 nm
10 15 20 25 30 35 40 45 50 55 600%
10%
20%
30%Mean: 31.7 nmSD: 9.0 nm
Coun
t
Hole Size (nm)
136 nm
15 20 25 30 35 40 45 500%
10%
20%
30%
Coun
t
Hole Size (nm)
92 nmMean = 28.6 nmSD = 5.2 nm
5 10 15 20 25 300%
10%
20%
30%
40% 75 nmMean: 15.2 nmSD: 2.3 nm
Coun
t
Hole Size (nm)
15.2±2.3nm 28.6±5.2nm
30.3±2.1nm 31.7±9nm
9
H. Yi … H.-S. P. Wong, Adv. Mater. , 2012
Stanford University
10 July 9, 2012
2-Hole Pattern Analysis
8 10 12 14 16 18 20 220%
10%
20%
30%
40%
50%
Mean: 15.0 nmSD: 1.8 nm
Coun
t
Hole Size (nm)
60nmx110 nm
34 35 36 37 380%
10%
20%
30%
40%Mean: 37.7nmStd: 1.0nm
Cou
nt
Hole Pitc
35 36 37 38 39 40 41 42 43 44 450%
10%
20%
30%
40%
Cou
nt
Hole Pitch (nm)
Mean: 39.7nmStd: 1.9nm
2-hole pattern
-3 -2 -1 0 1 2 30%
10%
20%
30%
40%
Centroid Deviation (nm)
2-hole: B
Cou
nt
Centroid Deviation (nm)
AveDev-x =1.1 nm AveDev-y =1.3 nm
2-hole: A
-3 -2 -1 0 1 2 30%
10%
20%
30%
40%
Cou
nt
AveDev-x =0.9 nm AveDev-y =1.5 nm
AB
hole centroid
Average centroidHole edge
∆x
∆y
∆x ~1nm∆y ~1.5 nm
15±1.8 nm 40±2nm
Overlay accuracy: Average absolute deviation
H. Yi … H.-S. P. Wong, Adv. Mater. , 2012
Stanford University
11 July 9, 2012
ABC
34 35 36 37 38 39 40 41 420%
10%
20%
30%
40%Mean: 37.7nmStd: 1.0nm
Cou
nt
Hole Pitch (nm)
35 36 37 38 39 40 41 42 43 44 450%
10%
20%
30%
40%3-hole pattern
Cou
nt
Hole Pitch (nm)
Mean: 39.7nmStd: 1.9nm
2-hole pattern
8 10 12 14 16 18 20 22 240%
10%
20%
30%
40%
Mean: 14.8 nmSD: 2.4 nm
Coun
t
Hole Size (nm)
70nmx145nm
-3 -2 -1 0 1 2 3
AveDev-x=1.3 nm AveDev-y=1.9 nm
AveDev-x=1.5 nm AveDev-y=1.8 nm
-3 -2 -1 0 1 2 3Centroid Deviation (nm)
-3 -2 -1 0 1 2 30%
10%
20%
30%
40%
3-hole: C3-hole: B
AveDev-x=1.1 nm AveDev-y=1.8 nm
Cou
nt
3-hole: A
∆x ~1.5 nm∆y ~1.9 nm
14.8±2.4 nm 38±1nm
3-Hole Pattern Analysis
H. Yi … H.-S. P. Wong, Adv. Mater. , 2012
Stanford University
12 July 9, 2012
Design Space for 2-3 Hole Guiding Templates
Parameters:• template size• template shape• thickness• pattern density
H. Yi … H.-S. P. Wong, Adv. Mater. , 2012
Stanford University
13 July 9, 2012
IBM 22-nm SRAM Contact Holes Layout
*Double pattern and double etch process were used to achieve these 26 nm size contact holes. Haran, B. S. Proc. IEDM (2008).
90nm
110 nm
connection
6T-SRAM CellC1 – 1st exposureC2 – 2nd exposure
Stanford University
14 July 9, 2012
Polysilicon gate
Active region
Contact hole
Connection
Template mask layout
Size: 56nm (contacts)56 x 70 nm (connection)
Pitch: x-axis=90nmy-axis=110nm
round hole
elliptical hole
round hole
DSA-Aware Contact Holes for SRAM
Stanford University
15 July 9, 2012
200 nm 200 nm
• 300mm wafer• 193 nm immersion Litho• Industrial compatible sol.
20 30 40 50 60 70 800%
10%
20%
30%
Mean: 66.4 nm SD: 6.9 nm
Mean: 24.8 nm SD: 3.0 nm
Coun
t
Hole Size (nm)
a
‐5 ‐4 ‐3 ‐2 ‐1 0 1 2 3 4 50%
10%
20%
30%
40%
50%
Centroid Deviation (nm)
Cou
nt
AveDev-x= 0.9 nm AveDev-y= 1.2 nm
b
Template SEM DSA SEM
Template ~ 66.4±7nm
Contact hole ~ 25±3nm
Centroid ∆x ~0.9 nm
Centroid ∆y ~1.2 nm
DSA Patterned Contact Holes for SRAM
X.-Y. Bao, H. Yi … H.-S. P. Wong, IEDM, p. 167, 2011
Stanford University
16 July 9, 2012
Contact Holes for NAND (strategy)
AB
60x110nm
15 nm hole size40 nm pitch
Rotate to fit 30nm pitch
Extend to 15-nm NAND
(source: UBM Techinsights)
2-hole templates for NAND
40 nm
30 nm
48.6°
X.-Y. Bao, H. Yi … H.-S. P. Wong, IEDM, p. 167, 2011
Stanford University
17 July 9, 2012
Contact holes for DRAM (strategy)
145nm space165nm pitch
70nm space90nm pitch
Storage Node ContactBit-line Contact
20nm wide eye-guiding grids
Shrink to 2x-nm DRAMExample of 3x-nm DRAM(Source: Chipworks)
3 contacts per active island (2 storage and one bitline)
3-hole templates (70x145nm)
3-hole templates for DRAM
X.-Y. Bao, H. Yi … H.-S. P. Wong, IEDM, p. 167, 2011
Nangate cell library: http://www.nangate.com
J. Stork, TI (2007), Stanford seminar
Stanford University
Contacts for Random Logic Circuit
19
Challenges for DSA patterning• Overcome resolution limits• Irregular contact distribution• Guiding template design• Optimal template size and shape
Courtesy of Jason Sweis, Cadence Design Systems
Example: Conventional 45nm HA-X1 Layout
Source: Nangate 45nm Open Cell Library
Contact hole layout
Design 1 Design 2
July 9, 2012
Stanford University
20
DSA-Aware Layout: Simplifying Template Design
Starting Point: Gridded Design Rule (GDR)
Source: http://www.tela-inc.com
Scan-D Flip Flop designed with Gridded Design Rules
• Lines: parallel, single width & pitch• Contacts: positioned only at pre-
determined grid points
Metal 1 Poly Active Region Contact
Conventional HA-X1 Layout DSA-Aware HA-X1 Layout
• Transistor sizes and connections (pin-out) unchanged
• No area penalty
M2 vertical direction routing not shown for the sake of clarity
July 9, 2012
Stanford University
21
Random Logic Circuit Patterning: 1-bit Half Adder DSA-aware HA-X1 Contact Hole Layout
Template (SEM) DSA results (SEM)
Template defects DSA heal
defects
Scale bar: 200nm
July 9, 2012
Stanford University
22
Random Logic Circuit Patterning: 1-bit Half Adder
Template defects
Scale bar: 200nm
July 9, 2012
Stanford University
23
Random Logic Circuit Patterning: 1-bit Half Adder
DSA heals defects
Scale bar: 200nm
July 9, 2012
Stanford University
24
Random Logic Circuit Patterning: 1-bit Full Adder Conventional FA-X1 (Nangate 45nm Open Cell Library)
DSA-aware FA-X1 Contact Hole Layout
48 49 50 51 52 53 540%
10%
20%
30%
40%
Cou
nt
Template Size (nm)
Mean: 51.1nmStd: 1.3nm
-2 -1 0 1 20%
20%
40%Mean Deviation-Y: 0.8nm
Cou
nt
Centroid Deviation (nm)12 14 16 18 20
0%
10%
20%
30%
40%Mean: 15.0nmStd: 1.4nm
Cou
nt
Hole Size (nm)-3 -2 -1 0 1 2
0%
20%
40%
60%
80%Mean Deviation-X: 0.7nm
Cou
nt
Centroid Deviation (nm)
Merged templates don’t affect DSA holes overlay accuracy and size variation strongly
Green histogram: represent holes in merged templates.
July 9, 2012
Stanford University
25
Random Logic Circuit Patterning: 1-bit Full Adder
-2 -1 0 1 20%
20%
40%Mean Deviation-Y: 0.8nm
Cou
ntCentroid Deviation (nm)
-3 -2 -1 0 1 20%
20%
40%
60%
80%Mean Deviation-X: 0.7nm
Cou
nt
Centroid Deviation (nm)
Merged templates don’t affect DSA holes overlay accuracy and size variation
Green histogram: represent holes in merged templates
48 49 50 51 52 53 540%
10%
20%
30%
40%
Cou
nt
Template Size (nm)
Mean: 51.1nmStd: 1.3nm
12 14 16 18 200%
10%
20%
30%
40%Mean: 15.0nmStd: 1.4nm
Cou
nt
Hole Size (nm)
Scale bar: 200nm
July 9, 2012
Stanford University
26 July 9, 2012
DSA for Contact Hole Patterning
DSA Evolution
1 2 3 4Infinite periodic Boundary periodic
193 nm immersion + DSA
=
Extension of double-patterning
Stanford University
27 July 9, 2012
Looking Forward
Defectivity– 300 mm wafer, statistical data
EDA tool– Think OPC, DFM
– Application of DSA must be transparent to designers
Develop DSA-aware template design rules– Experiments, modeling
Stanford University
28 July 9, 2012
Graduated Student and Post-Doc
Li-Wen ChangPhD 2010Currently with Xilinx
Xinyu BaoPost-doc (2008 – 2010)Currently with AMAT
Stanford University
29 July 9, 2012
Collaborators
Applied Materials (Chris Bencher and team)
Prof. Subhasish Mitra (Stanford, EE & CS Dept.)
Stanford University
30 July 9, 2012
Sponsors and Collaborators