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ECE 3110: Introduction to Digital Systems
Chapter 5 Combinational Logic Design
Practices
Encoders
Three-state devices
Multiplexers
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74x138/139 decoders
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Encoders
Multiple-input/multiple-output device.
Perfoms the inverse function of a Decoder.
Outputs ( m ) are less than inputs ( n ).
Converts input code words into output code words.
input code
output code
ENCODER
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Encoders vs. Decoders
Decoder Encoder
2^n-to-n encoder
Input code : 1-out-of-2^n.
Output code : Binary Code
n-to-2^n
Input code : Binary Code
Output code :1-out-of-2^n.
Binary decoders/encoders
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Binary Encoder
2^n-to-n encoder : 2^n inputs and n outputs. Input code : 1-out-of-2^n. Output code : Binary Code Example : n=3, 8-to-3 encoder
Inputs Outputs
I0 I1 I2 I3 I4 I5 I6 I7 Y0 Y1 Y2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1
I1
I2
I3 Y1
Y2I4
I5
I6
I0
Y0
I7
Binary encoder
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8-to-3 encoder Implementation
Simplified implementation:- From the truth table Y2 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y0 = I4 + I5 + I6 + I7
Limitations :- I0 has no effect on the output- Only one input can be activated
Application:Handling multiple devices requests But, no simultaneous requests
Establishing priorities solve the problem of multiple requests
I1
I2
I3
I4
I5
I6
I0
I7
Y1
Y2
Y0
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Need priority in most applications
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Priority Encoder
Assign priorities to the inputs When more than one input are asserted, the output
generates the code of the input with the highest priority Priority Encoder :
H7=I7 (Highest Priority) H6=I6.I7’ H5=I5.I6’.I7’ H4=I4.I5’.I6’.I7’ H3=I3.I4’.I5’.I6’.I7’ H2=I2.I3’.I4’.I5’.I6’.I7’ H1=I1. I2’.I3’.I4’.I5’.I6’.I7’ H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’ IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’ - Encoder Y0 = H1 + H3 + H5 + H7 Y1 = H2 + H3 + H6 + H7 Y2 = H4 + H5 + H6 + H7
I6
I5
I4 Y1
Y0I3
I2
I1
I7
Y2
I0
Binary encoder
I6
I5
I4
I3
I2
I1
I7
I0
Priority Circuit
H6
H5
H4
H3
H2
H1
H7
H0
IDLE
I6
I5
I4
I3
I2
I1
I7
I0
A1
A0
A2
IDLE
Priority encoder
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8-input priority encoder
I7 has the highest priority,I0 least
A2-A0 contain the number of the highest-priority asserted input if any.
IDLE is asserted if no inputs are asserted.
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74x148 8-input priority encoder
Active-low I/O Enable Input “Got Something”:Group Select Enable Output
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74x148 Truth Table
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74x148circuit
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Cascading priority encoders
32-inputpriority encoder
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Three State Buffers/Drivers
A buffer/inverter with enable input
Buffer Buffer Inverter Inverter Actice High Enable Actice Low Enable Active High Enable Actice Low Enable
The device behaves like an ordinary buffer/inverter when the enable input is asserted.
The ouput is floating ( High Impedance, Hi-Z ) when the enable input is deasserted ( The input is isolated from the output, behaves as if it did not exist)
Application: Controlling the access of a single line/bus by multiple devices
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Three-state buffers
Output = LOW, HIGH, or Hi-Z.
Can tie multiple outputs together, if at most one at a time is driven.
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8 sources share a three-state party line
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Timing considerations
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Standard SSI/MSI 3-state buffers
SSI: 74x125, 74x126 (independent enable inputs)
MSI: 74x541 and varieties such as 74x540, 74x240, 74x241
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Octal noninverting 3-state buffer
Hysteresis
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Driver application
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Pairs of 3-state buffers connected in opposite directions between each pair of pins, so data can be transferred in either direction.
DIR determines the direction of transfer (A-->B or B-->A)
Three-state transceiver
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Transceiver application
Bidirectional buses
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Multiplexers (mux)
Select one of n sources of data to transmit on a bus.
Eg. Put between Processor’s registers and ALU
A 16-bit processor where 3-bit field specifies on of 8 registers.
The 3-bit field is connected to the select inputs of an 8-input, 16-bit mux.
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MSI: 74x1518-input 1-bit multiplexer
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74x151 truth table
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Other multiplexer varieties 2-input, 4-bit-wide
74x157
4-input, 2-bit-wide 74x153
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Expanding Multiplexers
32-to-1 mux
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Demultiplexers
A mux is used to select one of n sources of data to transmit on a bus.
A demultiplexer can be used to route the bus data to one of m destinations. Just the inverse of a mux.
A binary decoder with an enable input can be used as a demux. Eg. 74x139 can be used as a 2-bit, 4-output demux.
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Next…
X-OR gates and Parity circuits Comparators Adders, subtractors, ALUs
Reading Wakerly CH-5.8-5.11