ECE 3450 M. A. Jupina, VU, 2014
Reaction Timer Project
Reference:Fundamentals of Digital Logic, section 7.14.3.
Design and implement on the DE2 board a reaction-timer circuit. The circuit is to operate as follows:1. The circuit is reset by pressing the pushbutton switch KEY0.2. After an elapsed time, the red light labeled LEDR0 turns on and a four-digit BCD counter starts counting in intervals of milliseconds. The amount of time in seconds from when the circuit is reset until LEDR0 is turned on is set by the output of a pseudo random number generator (PRNG).3. A person whose reflexes are being tested must press the pushbutton KEY3 as quickly as possible to turn the LED off and freeze the counter in its present state. The count which shows the reaction time will be displayed on the 7-segment displays HEX3-0.
Reaction Timer Sequence of Events
An operator hits KEY0 to reset and trigger the
system.
ECE 3450 M. A. Jupina, VU, 2014
Time delay (< 3 s)set by PRNG
An user reacts and hits KEY3. The LED goes off and the reaction time is
displayed.
Reaction time (< 1 s)
Figure 7.76. A reaction-timer circuit.
D Q
Q
(a) Clock divider
10-bit counterClock
c 0 c 1 c 9
Two-digit BCD counter
w 0
a
w 1
b
w 2 w 3
g
w 0
a
w 1
b
w 2 w 3
g
BCD 0 BCD 1 E
Converter Converter
c 9
V DD
R
w
V DD
R L
(c) Push-button switch, LED, and 7-segment displays
Reset Clear
V DD
R L
V DD
V LED
1
0
1
(b) LED circuit
ECE 3450 M. A. Jupina, VU, 2014
Stop Key
Figure 7.79. Simulation of the reaction-timer circuit.
ECE 3450 M. A. Jupina, VU, 2014
Reaction Timer Block Diagram
Timing Circuit(Dual OS)
Reset Key LED
PRN
G Reaction Timer Circuit
Stop Key
7 S
egm
ent
Dis
play
s
DelayValue
DelayedPulse
ReactionTimeValue
ECE 3450 M. A. Jupina, VU, 2014
“w”signal
Reaction Timer Block Diagram
Timing Circuit(Dual OS)
Reset Key LED
PRN
G Reaction Timer Circuit
Stop Key
7 S
egm
ent
Dis
play
s
DelayValue
DelayedPulse
ReactionTimeValue
ECE 3450 M. A. Jupina, VU, 2014
“w”signal
Linear Feedback Shift RegisterA diagram of an eight bit LFSR
This functionality can be implemented using the altshift_taps Megafunction found in the Megafunction library in the storage folder.
ECE 3450 M. A. Jupina, VU, 2014
Tap SettingsThe following table shows a minimum number of taps that yield maximal length sequences for LFSRs ranging from 2 to 8 bits.
ECE 3450 M. A. Jupina, VU, 2014
The ALTSHIFT_TAPS Megafunction and Its Application in a PRNG Circuit
ECE 3450 M. A. Jupina, VU, 2014
An Example of the Simulated Waveforms for the ALTSHIFT_TAPS Megafunction
ECE 3450 M. A. Jupina, VU, 2014
Reaction Timer Block Diagram
Timing Circuit(Dual OS)
Reset Key LED
PRN
G Reaction Timer Circuit
Stop Key
7 S
egm
ent
Dis
play
s
DelayValue
DelayedPulse
ReactionTimeValue
ECE 3450 M. A. Jupina, VU, 2014
“w”signal
Dual OS Circuit to Generate “w signal” (trigger signal to light LED)
ECE 3450 M. A. Jupina, VU, 2014
?
Reaction Timer Block Diagram
Timing Circuit(Dual OS)
Reset Key LED
PRN
G Reaction Timer Circuit
Stop Key
7 S
egm
ent
Dis
play
s
DelayValue
DelayedPulse
ReactionTimeValue
ECE 3450 M. A. Jupina, VU, 2014
“w”signal
Figure 7.77. Code for the two-digit BCD counter in Figure 7.28.
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;
ENTITY BCDcount ISPORT ( Clock : IN STD_LOGIC ;
Clear, E : IN STD_LOGIC ;BCD1, BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END BCDcount ;
ARCHITECTURE Behavior OF BCDcount ISBEGIN
PROCESS ( Clock )BEGIN
IF Clock'EVENT AND Clock = '1' THENIF Clear = '1' THEN
BCD1 <= "0000" ; BCD0 <= "0000" ;ELSIF E = '1' THEN
IF BCD0 = "1001" THENBCD0 <= "0000" ;IF BCD1 = "1001" THEN
BCD1 <= "0000";ELSE
BCD1 <= BCD1 + '1' ;END IF ;
ELSEBCD0 <= BCD0 + '1' ;
END IF ;END IF ;
END IF;END PROCESS;
END Behavior ;
ECE 3450 M. A. Jupina, VU, 2014
Figure 7.28. A two-digit BCD counter.
ECE 3450 M. A. Jupina, VU, 2014
Reaction Timer Block Diagram
Timing Circuit(Dual OS)
Reset Key LED
PRN
G Reaction Timer Circuit
Stop Key
7 S
egm
ent
Dis
play
s
DelayValue
DelayedPulse
ReactionTimeValue
ECE 3450 M. A. Jupina, VU, 2014
“w”signal
Figure 6.25. A BCD-to-7-segment
display code converter.
c e
1 0 1 1
1 1 1
w 0 a
1
b
0 1
1 1
1
0 1
1 0 1
0
0
w 1
0 1 1
0
0
w 2
0 0 0
0
1
w 3
0 0 0
0
0
c
1 0 1 0
0 1 1 0
1 1 1 0
0 0 0 1
1 0 0 1
1 1 1 1
0 1 1
0
1 1
1 1
1
1 1
0 1 1
1
d
0
1 0
0
1 0
e
1 0 1
1
1
0 1
0
0 1
0 0 0
1
f
1
0 0
1
1 1
g
1 0 1
1
1
1 1
1
0 1
(c) Truth table
(a) Code converter
w 0
a
w 1
b c d w 2
w 3 e f g
a
g
b f
d
(b) 7-segment display
ECE 3450 M. A. Jupina, VU, 2014
Figure 6.47. Code that represents a BCD-to-7-segment decoder.
LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY seg7 IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGIN
PROCESS ( bcd )BEGIN
CASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;
END CASE ;END PROCESS ;
END Behavior ;
ECE 3450 M. A. Jupina, VU, 2014
Hexadecimal to
7-Segment Decoder
ETC.
Input
Outputs
ECE 3450 M. A. Jupina, VU, 2014
Clock Divider for DE2
The clock_50MHz input is connected to pin number N2.
ECE 3450 M. A. Jupina, VU, 2014
DE2_pin_assignments.csv File
ECE 3450 M. A. Jupina, VU, 2014
Settings for Signal Tap II Logic Analyzer
@1: EP2C35 (0x020B 40DD)
ECE 3450 M. A. Jupina, VU, 2014
Example of Signals Displayed in Signal Tap II
@1: EP2C35 (0x020B 40DD)
ECE 3450 M. A. Jupina, VU, 2014
Reaction Timer Pre-Lab Assignment
1) Alter the VHDL code for the two-stage BCD counter in figure 7.77 to create a four-stage BCD counter. Your system will be able to measure a maximum elapsed time of 9.999 s (time resolution is 1 ms).
2) Draw a block diagram of the dual one-shot timing circuit that will be used to create the w trigger signal to turn the LED on. The signal generated by the pushbutton switch KEY0 will be used as an input to this circuit and the output of a Pseudo Random Number Generator will be used to control the time delay in the circuit. Sketch the signal waveforms in your timing circuit. Show all details: switches, pin numbers, clock frequencies used, etc.
3) Draw a block diagram of your Reaction Timer circuit design. Show all details: switches, LED display elements, pin numbers, clock frequencies used, etc.
ECE 3450 M. A. Jupina, VU, 2014
Reaction Timer Project Practicum WorkWork to be preformed in the Lab:1) Compile and simulate the four-stage BCD counter. Call this project
four_stage_BCD_counter. 2) Compile and simulate the w signal trigger circuit. Call this project
w_signal_trigger_circuit.3) Compile and simulate the Pseudo Random Number Generator
circuit. Call this project PRNG_circuit.4) Compile and simulate the reaction timer circuit. Do not use the
clock divider and seven segment decoder blocks in this project. Call this project reaction_timer_simulated.
5) Create a new project, reaction_timer, where the clock divider, seven segment decoders, and pin assignments are added to the project. Compile your design. If the design compiles without errors, then add the Signal Tap II logic analyzer to your project and re-compile. Program the DE2 board and test your design. If your design is not operational, then use the observed signals in the Signal Tap display to debug your design.
6) Record your reaction time. How fast are you?
ECE 3450 M. A. Jupina, VU, 2014