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VALLIAMMAI ENGINEERING COLLEGE
SRM NAGAR, KATTANKULATHUR
DEPARTMENT OF ELECTRICAL & ELECTRONICS
ENGINEERING
LAB MANUAL
NAME :
REGISTER NUMBER:
CLASS :
SEMESTER : IV SEM
SUBJECT CODE : EE 2258
SUBJECT : LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB
1
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SYLLABUS
EE 2258 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
AIM:To study various digital & linear integrated circuits used in simple system
configuration.
LIST OF !"#IM$TS:
1. Study of %asic igital I'(s. )erification of trut* ta+le for A$, O#, !O#, $OT, $O#, $A$, - FF, #S FF, FF/
0. Implementation of %oolean Functions, Adder Su+tractor circuits.2.a/. 'ode converters, "arity generator and parity c*ec3ing, 4cess 2, 0s
'omplement, %inary to gray code using suita+le I'(s .
+/ ncoders and ecoders: ecimal and Implementation of 56+it s*ift registers inSISO,SI"O,"ISO,"I"O modes using suita+le I'(s.
5. 'ounters: esign and implementation of 56+it modulo counters as sync*ronousand async*ronous types using FF I'(s and specific counter I'.
7. S*ift #egisters: esign and implementation of 56+it s*ift registers in SISO, SI"O,"ISO, "I"O modes using suita+le I'(s.
8. Multiple4 e6multiple4 : Study of 5:19 :1 multiple4er and Study of 1:59 1:demultiple4er
;. Timer I' application.Study of $S 777 timer in Asta+le, Monosta+le operation.
. Application of Op6Amp6I Sle< rate verifications, inverting and non6inverting amplifier, Adder,
comparator,Integrator and ifferentiator.
=. Study of Analog to igital 'onverter and igital to Analog 'onverter: )erification
of A conversion using dedicated I'(s.
1>. Study of )'O and "LL I's i. )oltage to fre?uency c*aracteristics of $ S 788 I'. ii. Fre?uency multiplication using $S 787 "LL I'.
" @ 57 Total @ 57
0
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CONTENTS
Sl.No Dat Na! o" t# E$%&'!(t Pa) No. Ma&*+ A,a&-- /01
Average Mar3s
4. $o:
5
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ate:STUDY OF BASIC DIGITAL ICS
AIM:
To verify t*e trut* ta+le of +asic digital I's of A$, O#, $OT, $A$, $O#, !6O#gates.
APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity
1. igital I' trainer 3it 1
0. A$ gate I' ;5> 1
2. O# gate I' ;520 1
5. $OT gate I' ;5>5 1
7. $A$ gate I' ;5>> 1
8. $O# gate I' ;5>0 1
;. !6O# gate I' ;58 1
. 'onnecting
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A $A$ gate is a complemented A$ gate. T*e output of t*e $A$ gate ( if all t*e input signals are E1( and (.
e. $O# gate:
A $O# gate is a complemented O# gate. T*e output of t*e O# gate ( and ( if any one of t*e input signal is E1(.
f. !6O# gate:
An 46O# gate performs t*e follo( :
8
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T#BTH TA%L:
S.$oI$"BT OBT"BT
A % @ A G %1. > > >0. > 1 12. 1 > 15. 1 1 1
$OT AT
LOI' IA#AM:
"I$ IA#AM OF I' ;5>5 :
'I#'BIT IA#AM:
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'I#'BIT IA#AM:
T#BTH TA%L:
S.$oI$"BT OBT"BT
A % @ A. %/(1. > > 10. > 1 12. 1 > 15. 1 1 >
$O# AT
LOI' IA#AM:
"I$ IA#AM OF I' ;5>0 :
1>
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'I#'BIT IA#AM:
T#BTH TA%L:
S.$oI$"BT OBT"BT
A % @ A G %/(
1. > > 10. > 1 >2. 1 > >5. 1 1 >
!6O# AT
LOI' IA#AM
"I$ IA#AM OF I' ;58:
'I#'BIT IA#AM:
11
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T#BTH TA%L:
S.$oI$"BT OBT"BT
A % @ A %1. > > >0. > 1 12. 1 > 15. 1 1 >
DISCUSSION UESTIONS:
1. J*at is Integrated 'ircuitK
0. J*at is a Logic gateK
2. J*at are t*e +asic digital logic gatesK
5. J*at are t*e gates called universal gatesK
7. J*y $A$ and $O# gates are called universal gatesK8. J*at are t*e properties of !6$O# gateK
#SBLT:
T*e trut* ta+les of all t*e +asic digital I's
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ate:DESIGN AND IMPLEMENTATION OF ADDER4SUBTRACTOR
AIM:
To design and construct *alf adder, full adder, *alf su+tractor and full su+tractor circuitsand verify t*e trut* ta+le using logic gates.
APPARATUS REUIRED:
S. No Na! S%'"'at'o( 6a(t't7
1. I' ;520, ;5>, ;58, ;52 1
0. igital I' Trainer it 1
2. "atc* c*ords 6
T3EORY:
T*e most +asic arit*metic operation is t*e addition of t G > @ >> G 1 @ 11 G > @ 1
1 G 1 @ 1>0
T*e first t*ree operations produce a sum of
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T#BTH TA%L:
S.$oI$"BT OBT"BT
A % S '
1. > > > >0. > 1 1 >2. 1 > 1 >5. 1 1 > 1
SI$:
From t*e trut* ta+le t*e e4pression for sum and carry +its of t*e output can +eo+tained as, Sum, S @ A % 9 'arry, ' @ A . %
CIRCUIT DIAGRAM:
FBLL A#
T#BTH TA%L:
S.$oI$"BT OBT"BT
A % ' SBM 'A##1. > > > > >0. > > 1 1 >2. > 1 > 1 >5. > 1 1 > 17. 1 > > 1 >8. 1 > 1 > 1;. 1 1 > > 1. 1 1 1 1 1
SI$:
15
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From t*e trut* ta+le t*e e4pression for sum and carry +its of t*e output can +e o+tainedas,SBM @ A(%(' G A(%'( G A%('( G A%'9'A## @ A(%' G A%(' G A%'( GA%'Bsing arnaug* maps t*e reduced e4pression for t*e output +its can +e o+tained as,
SBM
SBM @ A(%(' G A(%'( G A%('( G A%' @ A % '
'A##
'A## @ A% G A' G %'
CIRCUIT DIAGRAM:
HALF SB%T#A'TO#:
17
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A com+inational circuit > > >0. > 1 1 12. 1 > 1 >5. 1 1 > >
SI$:
From t*e trut* ta+le t*e e4pression for difference and +orro< +its of t*e output can +eo+tained as, ifference, IFF @ A %9 %orro
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T#BTH TA%L:
S.$oI$"BT OBT"BT
A % ' IFF %O##1. > > > > >
0. > > 1 1 12. > 1 > 1 15. > 1 1 > 17. 1 > > 1 >8. 1 > 1 > >;. 1 1 > > >. 1 1 1 1 1
SI$:
From t*e trut* ta+le t*e e4pression for difference and +orro< +its of t*e output can +e
o+tained as,
ifference, IFF@ A(%(' G A(%'( G A%('( G A%'%orro
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PROCEDURE:
T*e connections are given as per t*e circuit diagram.
T
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4. $o:ate:
PARITY GENERATOR C3EC9ER
AIM:To design and verify t*e trut* ta+le of a t*ree +it Odd "arity generator and c*ec3er &
ven "arity enerator And '*ec3er.
APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity
1. igital I' trainer 3it 1
0. !6O# gate I' ;58
2.$OT gate I' ;5>5
5. 'onnecting
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"A#IT $#ATO#
T#BTH TA%L:
S.$o
I$"BT
T*ree +itmessage/
OBT"BT Odd "arity +it/ OBT"BT ven "arity +it/
A % ' " "1. > > > 1 >0. > > 1 > 12. > 1 > > 15. > 1 1 1 >7. 1 > > > 18. 1 > 1 1 >;. 1 1 > 1 >
. 1 1 1 > 1
From t*e trut* ta+le t*e e4pression for t*e output parity +it is," A, %, '/ @ >, 2, 7, 8/Also
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"A#IT 'H'#
PROCEDURE:
1. 'onnections are given as per t*e circuit diagrams.0. For all t*e I's ;t* pin is grounded and 15t*pin is given G7 ) supply.
2. Apply t*e inputs and verify t*e trut* ta+le for t*e "arity generator and c*ec3er.
DISCUSSION UESTIONS:
1. J*at is parity +itK0. J*y parity +it is added to messageK2. J*at is parity c*ec3erK5. J*at is odd parity and even parityK7. J*at are t*e gates involved for parity generatorK
RESULT:
T*e design of t*e t*ree +it odd "arity generator and c*ec3er& ven "arity enerator and'*ec3er circuits
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4. $o:ate:
CODE CONVERTER
AIM:
To construct and verify t*e performance of +inary to gray and gray to +inary.
APPARATUS REUIRED:
S. No Na! S%'"'at'o( 6a(t't7
1. I' ;5>5, ;58 1
0. igital I' Trainer it 1
2. "atc* c*ords 6
T3EORY:
%I$A# TO #A:
T*e MS% of t*e +inary code alone remains unc*anged in t*e ray code. T*e remaining
+its in t*e gray are o+tained +y !6O# ing t*e corresponding gray code +it and previous +it in
t*e +inary code. T*e gray code is often used in digital systems +ecause it *as t*e advantage t*at
only one +it in t*e numerical representation c*anges +et
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%I$A# TO #A:
#A TO %I$A#
02
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TRUT3 TABLE
ecimal %inary code ray codeD ' % A 2 0 1 O
> > > > > > > > >
1 > > > 1 > > > 10 > > 1 > > > 1 12 > > 1 1 > > 1 >5 > 1 > > > 1 1 >7 > 1 > 1 > 1 1 18 > 1 1 > > 1 > 1; > 1 1 1 > 1 > > 1 > > > 1 1 > >= 1 > > 1 1 1 > 11> 1 > 1 > 1 1 1 111 1 > 1 1 1 1 1 >10 1 1 > > 1 > 1 >12 1 1 > 1 1 > 1 115 1 1 1 > 1 > > 117 1 1 1 1 1 > > >
DISCUSSION UESTIONS:
1. List t*e procedures to convert gray code into +inaryK0. J*y
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4. $o:ate:
/1 ENCODER
AIM:
To design and implement encoder using I' ;515 62 encoder/
APPARATUS REUIRED:
S. No Na! S%'"'at'o( 6a(t't7
1. I' ;515 1
0. igital I' Trainer it 1
2. "atc* c*ords 6
T3EORY:
An encoder is digital circuit t*at *as 0ninput lines and n output lines. T*e output lines
generate a +inary code corresponding to t*e input values 2 encoder circuit *as inputs, one
for eac* of t*e octal digits and t*ree outputs t*at generate t*e corresponding +inary num+er.
na+le inputs 1s*ould +e connected to ground and os*ould +e connected to )''
PROCEDURE:
'onnections are given as per t*e logic diagram.
T*e trut* ta+le is verified +y varying t*e inputs.
PIN DIAGRAM
O U T P2
N I N P U T
N
E N C O D E R
/
2
/
2
N2 N : /
2 N
07
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TRUTH TABLE
1I$"BTS OBT"BTS
A> A1 A0 A2 A5 A7 A8 A; 0 1 >> > 1 1 1 1 1 1 1 > > >> 1 > 1 1 1 1 1 1 > > 1> 1 1 > 1 1 1 1 1 > 1 >> 1 1 1 > 1 1 1 1 > 1 1> 1 1 1 1 > 1 1 1 1 > >> 1 1 1 1 1 > 1 1 1 > 1> 1 1 1 1 1 1 > 1 1 1 >> 1 1 1 1 1 1 1 > 1 1 11 1 1 1 1 1 1 1 1 1 1 1
2) DECODERAIM:
To design and implement decoder using I' ;5177 26 decoder/.
APPARATUS REUIRED:
S. No Na! S%'"'at'o( 6a(t't7
1. I' ;5177 1
0. igital I' Trainer it 1
2. "atc* c*ords 6
08
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T3EORY:
A decoder is a com+inational circuit t*at converts +inary information from n input lines
to 0nuni?ue output lines.
In 26 line decoder t*e t*ree inputs are decoded into rig*t outputs in for proper operation.
PROCEDURE:
'onnections are given as per t*e logic diagram.
T*e trut* ta+le is verified +y varying t*e inputs.
CIRCUIT DIAGRAM:
O U T PN
/
2
/
2
N
N I N P U T D E C O D E R
2 N2 N : /
0;
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4. $o:ate:
MULTIPLEXER DEMULTIPLEXER
AIM:
To design and verify t*e trut* ta+le of a 5!1 Multiple4er & 1!5 emultiple4er.APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity1. igital I' trainer 3it 10. O# gate I' ;5202. $OT gate I' ;5>55. A$ gate t*ree input / I' ;5117. 'onnecting
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T#BTH TA%L:
S.$oSL'TIO$ I$"BT OBT"BT
S1 S0 1. > > I>
0. > 1 I12. 1 > I05. 1 1 I2
"I$ IA#AM OF I' ;511:
'I#'BIT IA#AM:
2>
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1!5 MBLTI"L!#
LOI' SM%OL:
T#BTH TA%L:
S.$o
I$"BT OBT"BT
S1 S0 in > 1 0 2
1. > > > > > > >
0. > > 1 1 > > >
2. > 1 > > > > >
5. > 1 1 > 1 > >
7. 1 > > > > > >
8. 1 > 1 > > 1 >
;. 1 1 > > > > >
. 1 1 1 > > > 1
21
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CIRCUIT DIAGRAM:
PROCEDURE:
1. 'onnections are given as per t*e circuit diagrams.0. For all t*e I's ;t* pin is grounded and 15t*pin is given G7 ) supply.2. Apply t*e inputs and verify t*e trut* ta+le for t*e multiple4er & demultiple4er.
DISCUSSION UESTIONS:
1. J*at is t*e ot*er name of de6multiple4erK
0. 'ompare MB! and 6MB!K2. Ho< many select lines needed for four outputs of 6MB!K5. J*at is ot*er name of multiple4erK7. J*at is serial to parallel converterK8. J*at is t*e use of select linesK;. Ho< to ena+le t*e multiple4erK. J*at are t*e applications of multiple4erK
RESULT:
T*e design of t*e 541 Multiple4er and 145 emultiple4er circuits
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4. $o:ate:
S3IFT REGISTERS
AIM:
To implement t*e follo
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S3IFT REGISTER:
I C ; < ;
>
/ 2 ? < 5 @ ;
8A/ 0/ // 2/ ?/ 'loc3 Serial input Serial output
> > >5 1 1 1 110 > >18 > >
27
2 /0
D
2 C B A
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PIPO
'loc3 "arallel input "arallel output
A % ' CA C% C' C> > > > > > > > >
1 1 1 > 1 1 1 > 1
SIPO
L"t +#'"t
$o of cl3 pulse Serial input in "arallel output
C2 C0 C1 C>> > > > > >
1 1 > > > 1
0 1 > > 1 1
2 > > 1 1 >
5 1 1 1 > 1
7 > 1 > 1 >
8 > > 1 > >
; > 1 > > >
> > > > >
R')#t S#'"t
$o of cloc3 pulse Serial input in "arallel output
C2 C0 C1 C>> > > > > >
1 1 1 > > >
0 1 > 1 > >
2 > 1 > 1 >5 1 1 1 > 1
7 > > 1 1 >
8 > > > 1 1
; > > > > 1
> > 0 > >
28
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DISCUSSION UESTIONS:
1. J*at is registerK0. J*at are t*e modes of s*ift registerK2. Ho< ring counter is implemented using s*ift registersK
5. 'ompare parallel and serial su+ registersK7. efine se?uence generatorK8. J*at are t*e types of s*ift registerK;. efine s*ift registers.
RESULT:
T*us t*e SISO, SI"O, "ISO, "I"O s*ift registers
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4. $o:ate:
ASYNC3RONOUS COUNTER
AIM:
To implement and verify t*e trut* ta+le of an async*ronous decade counter.APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity1. igital I' trainer 3it 10. - Flip Flop I' ;5;2 05. $A$ gate I' ;5>> 17. 'onnecting
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'I#'BIT IA#AM:
T#BTH TA%L:
S.$o'LO'"BLS
OBT"BTMS%/ ' % ALS%/
1 6 > > > >0 1 > > > 1
2 0 > > 1 >5 2 > > 1 17 5 > 1 > >8 7 > 1 > 1; 8 > 1 1 > ; > 1 1 1= 1 > > >
1> = 1 > 1 >11 1> > > > >
PROCEDURE:
1. 'onnections are given as per t*e circuit diagrams.0. Apply t*e input and verify t*e trut* ta+le of t*e counter.
DISCUSSION UESTIONS:
2=
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1. 'ompare sync*ronous and async*ronous se?uential circuitsK0. J*at is ripple counterK2. J*at is propagation delay in ripple counterK5. efine MO counterK
7. J*at are t*e applications of countersK8. State t*e types of counterK;. efine +it, +yte and
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ate:TIMER IC APPLICATIONS I
ASTABLE MULTIVIBRATOR1
AIM:
To design an asta+le multivi+rator circuit for t*e given specifications using 777 Timer I'.APPARATUS REUIRED:
S. $o $ame of t*e Apparatus #ange Cuantity1. Function enerator 2 MHD 10. '#O 2> MHD 12. ual #"S > 2> ) 15. Timer I' I' 777 17. %read %oard 18. #esistors
;. 'apacitors. 'onnecting
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CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:
SI$:
50
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iven f@ 5 HD,T*erefore, Total time period, T @ 1f @
Je 3no.8= #0/ 'T*erefore, #0@
tc@ >.8= #1 G #0/ 'T*erefore, #1@
PROCEDURE:
1. 'onnections are given as per t*e circuit diagram.0. G 7) supply is given to t*e G )cc terminal of t*e timer I'.2. At pin 2 t*e output
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DISCUSSION UESTIONS:
1. efine Offset voltage.0. efine duty cycle.2. Mention t*e applications of I'777.5. ive t*e met*ods for o+taining symmetrical s?uare
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TIMER IC APPLICATIONS II
MONOSTABLE MULTIVIBRATOR1
AIM:
To design a monosta+le multivi+rator for t*e given specifications using 777 Timer I'.APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity1. Function enerator 2 MHD, Analog 10. '#O 2> MHD 12. ual #"S > 2> ) 15. Timer I' I' 777 17. %read %oard 18. #esistors
;. 'apacitors. 'onnecting
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SI$:
iven tp@ >.818 ms @ 1.1 #1'T*erefore, #1@
PROCEDURE:
1. 'onnections are given as per t*e circuit diagram.0. G 7) supply is given to t*e G )cc terminal of t*e timer I'.2. A negative trigger pulse of 7), 0 HD is applied to pin 0 of t*e 777 I'5. At pin 2 t*e output
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DISCUSSION UESTIONS:
1. 4plain t*e operation of I'777 in monosta+le mode.0. J*at is t*e c*arging time for capacitor in monosta+le modeK
2. J*at are t*e modes of operation of 777 timersK5.Give the comparison between combinational circuits and sequential circuits.5. What do you mean by present state
!. Give the applications o" 555 timers #$.
RESULT:
T*e design of t*e Monosta+le multivi+rator circuit
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APPLICATIONS OF OPAMP I
INVERTING AND NON INVERTING AMPLIFIER1
a. INVERTING AMPLIFIER
AIM:
To design an Inverting Amplifier for t*e given specifications using Op6Amp I' ;51.
APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity1. Function enerator 2 MHD 10. '#O 2> MHD 12. ual #"S > 2> ) 1
5. Op6Amp I' ;51 17. %read %oard 18. #esistors As re?uired;. 'onnecting
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CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:
SI$:Je 3no< for an inverting Amplifier A'L @ #F #1Assume #1 appro4. 1> U/ and find #fHence )Ot*eoretical/ @6 A'L )I
OBSERVATIONS:
S.$o. Amplitude $o. of div 4 )olts per div /
Time period $o. of div 4 Time per div /
InputOutput T*eoretical 6
"ractical 6ODEL GRAP3:
5=
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I$)#TI$ AM"LIFI#:
INPUT SIGNAL:
OUTPUT SIGNAL:
RESULT:
T*e design and testing of t*e inverting amplifier is done and t*e input and output
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AIM:
To design a $on6Inverting Amplifier for t*e given specifications using Op6Amp I' ;51.
APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity1. Function enerator 2 MHD 10. '#O 2> MHD 12. ual #"S > 2> ) 15. Op6Amp I' ;51 17. %read %oard 18. #esistors As re?uired;. 'onnecting
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CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:
SI$:
Je 3no< for a $on6inverting Amplifier A'L@ 1 G #F #1/Assume #1 appro4. 1> U / and find #fHence )o@ A'L)i
OBSERVATIONS:
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S.$o. Amplitude $o. of div 4 )olts per div /
Time period $o. of div 4 Time per div /
InputOutput T*eoretical 6
"ractical 6
MODEL GRAP3:$O$ 6 I$)#TI$ AM"LIFI#:
INPUT SIGNAL:
OUTPUT SIGNAL:
DISCUSSION UESTIONS:
1. J*at do you mean +y linear circuitsK
0. efine an I'K
2. J*at is an inverting amplifierK
5. J*at is t*e type of feed+ac3 employed in t*e inverting op6amp
7. J*at is a voltage follo
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RESULT:
T*e design and testing of t*e $on6inverting amplifier is done and t*e input and output
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ate: APPLICATIONS OF OPAMP II DIFFERENTIATOR AND INTEGRATOR1
0. a. IFF#$TIATO#
AIM:
To design a ifferentiator circuit for t*e given specifications using Op6Amp I' ;51.APPARATUS REUIRED:
S.$o $ame of t*e Apparatus #ange Cuantity1. Function enerator 2 MHD 10. '#O 2> MHD 12. ual #"S > 2> ) 15. Op6Amp I' ;51 17. %read %oard 18. #esistors;. 'apacitors
. 'onnecting
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SI$:iven fa @ 666666666666666Je 3no< t*e fre?uency at d%, fa @ 1 0X #f'1/
Let us assume '1@ >.1 WF9 t*en#f@ Since f+@ 0> fa, f+@ 666666666666666Je 3no< t*at t*e gain limiting fre?uency f+@ 1 0X #1'1/Hence #1@ Also since #1'1 @ #f'f 9 'f@
PROCEDURE:
1. 'onnections are given as per t*e circuit diagram.0. G )cc and 6 )ccsupply is given to t*e po
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IFF#$TIATO#:
INPUT SIGNAL:
OUTPUT SIGNAL:
RESULT:
T*e design of t*e ifferentiator circuit
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SI$:
Je 3no< t*e fre?uency at d%, f+ @ 1 0X #1'f/T*erefore f+@ Since f+@ 1> fa, and also t*e gain limiting fre?uency fa@ 1 0X #f'f/Je get, #f@ and *ence #1@
PROCEDURE:
1. 'onnections are given as per t*e circuit diagram.
0. G )cc and 6 )cc supply is given to t*e po
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8. Jrite t*e disadvantages of ideal differentiator.
;. Jrite t*e application of differentiatorK
. J*y compensation resistance is needed in differentiator and *o<
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AIM:
To verify t*e c*aracteristic ta+le of #S, , -, and T Flip flops .
APPARATUS REUIRED:S.$o $ame of t*e Apparatus #ange Cuantity
1. igital I' trainer 3it 10. $O# gate I' ;5>02. $OT gate I' ;5>55. A$ gate t*ree input / I' ;5117. $A$ gate I' ;5>>8. 'onnecting
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T*is is a modification of - Flip Flop, o+tained +y connecting +ot* inputs - and inputstoget*er. T Flip Flop is also called Toggle Flip Flop.
#S FLI" FLO"
LOI' SM%OL:
CIRCUIT DIAGRAM:
C3ARACTERISTIC TABLE:
'LO'"BLS
I$"BT "#S$TSTAT C/
$!TSTATCG1/
STATBSS #
1 > > > >0 > > 1 12 > 1 > >5 > 1 1 >7 1 > > 18 1 > 1 1; 1 1 > ! 1 1 1 !
FLI" FLO"
LOI' SM%OL:
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CIRCUIT DIAGRAM:
C3ARACTERISTIC TABLE:
'LO'"BLS
I$"BT
"#S$TSTAT C/
$!TSTATCG1/
STATBS
1 > > >
0 > 1 >
2 1 > 1
5 1 1 1
- FLI" FLO"
LOI' SM%OL:
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CIRCUIT DIAGRAM:
C3ARACTERISTIC TABLE:
'LO'"BLS
I$"BT "#S$TSTAT C/
$!TSTATCG1/
STATBS-
1 > > > >0 > > 1 12 > 1 > >5 > 1 1 >7 1 > > 1
8 1 > 1 1; 1 1 > 1 1 1 1 >
T FLI" FLO"
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LOI' SM%OL:
CIRCUIT DIAGRAM:
C3ARACTERISTIC TABLE:
'LO'
"BLS
I$"BT
T
"#S$T
STAT C/
$!T
STATCG1/
STATBS
1 > > >0 > 1 >2 1 > 15 1 1 >
PROCEDURE:
1. 'onnections are given as per t*e circuit diagrams.
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0. For all t*e I's ;t* pin is grounded and 15t*pin is given G7 ) supply.2. Apply t*e inputs and o+serve t*e status of all t*e flip flops.
DISCUSSION UESTIONS:
1. efine flip6flop0. J*at is race around conditionK
2. 4plain t*e flip6flop e4citation ta+les for flip6flop
5. 4plain t*e flip6flop e4citation ta+les for - flip6flop
7. J*at is a master6slave flip6flopK
8. J*at is edge6triggered flip6flopK
;. J*at is t*e operation of flip6flopK
. J*at are t*e different types of flip6flopK
RESULT:
T*e '*aracteristic ta+les of #S, , -, T flip flops
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AIM:
To design and test t*e ' po>.1WF,1>>pF,22> WF,00 WF666
11101116
PROCEDURE:
LM;2?:
i/ 'onnections are made as per t*e circuit diagram
ii/ Set up t*e input voltage as 7),8) and 1>)
iii/ )ary t*e resistance #0designing value/ t*e corresponding output voltage are noted
do
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LM?/;: LM?/;:
LM;2?:
TABULATION:
8=
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LM;2?: LM?/;:)in:
#esistance in o*ms Output voltage )o
MODEL GRAP3:
LM;2?:
LM?/;:
DISCUSSION UESTIONS:
;>
V'( Vo6t
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1. J*at are t*e main advantages of voltage regulatorK0. efine line regulator or source regulator2. Ho< is t*e I' ;02 protected from s*ort circuitK5. efine ripple reection