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EE241 Spring 2011EE241 - Spring 2011Advanced Digital Integrated Circuits
Lecture 2: Scaling Trends and Features of Modern Technologiesand Features of Modern Technologies
Outline
Scaling issues
Technology scaling trends
Features of modern technologiesLithography
Process technologies
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IC Design: Major Roadblocks
1. Managing complexityHow to design a 10 billion transistor chip?And what to use all these transistors for?And what to use all these transistors for?
2. Cost of integrated circuits is increasingIt takes >$10M to design a chipMask costs are more than $3M in 45nm technology
3. The end of frequency scaling - Power as a limiting factor
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factorDealing with leakages
4. Robustness issuesVariations, SRAM, soft errors, coupling
5. The interconnect problem
Moore’s Law: Transistor Counts
Transistor Counts in Intel's Microprocessors
1000Itanium II
0 1
1
10
100
sist
ors
[in
mill
ion
s]
80286 386DX
486DX486DX4
PentiumPentium Pro
Pentium II
Pentium MMX
Pentium III
Pentium 4
Itanium
Itanium II
Core2
4
Doubles every 2 years
0.001
0.01
0.1
1970 1975 1980 1985 1990 1995 2000 2005
Tra
ns
4004
80088080
80868088
3
Frequency Trends in Intel's Microprocessors
10000Pentium 4 Core2
Frequency
10
100
1000
req
uen
cy [
MH
z]
8086
80286
386DX
486DX486DX4
Pentium
Pentium ProPentium II
Pentium MMX
Pentium III
ItaniumItanium II
Core2
5
0.1
1
1970 1975 1980 1985 1990 1995 2000 2005
Fr
4004
8008
8080
8088 Has been doublingevery 2 years, but is now slowing down
Power Dissipation
Power Trends in Intel's Microprocessors
1000
Has been > doublingevery 2 years
10
100
Po
wer
[W
]
808680286 486DX
Pentium
Pentium Pro
Pentium II
Pentium IIIPentium 4
Itanium
Itanium II Core 2
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Has to stay ~constant
0.1
1
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008 8080
8088386DX
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Some Recent DevicesIn research:10nm device
In production:45nm high-k strained Si
L = 10 nmg
C d t
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Corresponds tosub-22nm node(~10 years)
K. Mistry, IEDM’07
Some Recent Devices
Intel’s 30nm transistor, circa 2002
Ion = 570m/mIoff = 60nA/ m
8[B. Doyle, Intel]
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More Recent Devices
Intel’s 20nm transistor, circa 2002
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[B. Doyle, Intel]
@0.75V
More Recent Devices
SOI: Silicon-on-Insulator
Thin-Body SOI MOSFET
SOI: Silicon-on-Insulator
10Cheng, IEDM’09
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Sub-5nm FinFET
Gate
Gate
BOX Si fin - Body!
DrainSource
Gate
Silicon Fin
X. Huang, et al, IEDM’1999.
11Lee, VLSI Technology, 2006
Scaling Issues
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GATE
WIRINGVoltage, V /
W/tox/
CMOS Scaling Rules
p substrate, doping *NA
L/xd/
GATE
n+ source
n+ drain
SCALING:Voltage: V/
R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).
11Å
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Voltage: V/Oxide:Oxide: ttox ox //Wire width: W/Gate width: L/Diffusion: xd /Substrate: * NA
RESULTS:Higher Density: ~2
Higher Speed: ~Power/ckt: ~1/2
Power Density:Power Density: ~Constant~Constant
Transistor ScalingShrink by 30%
32nm transistor“Contacted poly pitch”Shrink by 30%
28nmF. Arnaud, IEDM’08
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8
1000
10000
I DSAT
Id l I
Ideal vs. Real Scaling
[µA/µm]
1
10
100
V DD
T inv
V Th
Ideal I DSAT
Ideal V DD
Ideal T
[x10V]
[ps]
[V]
15
0.1
10 100 1000Lg [nm]
Ideal T inv
Ideal V Th
Leakage slows down VTh, VDD scaling
Technology Flavors
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LP keeps drain leakage constant
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Lg, R, C scaling1000010000
10001000
1010
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nmnm
0.7X every 2 years
Nominal feature sizeNominal feature size
180nm180nm
250nm250nm
With scaling L, need to scale up doping, to scale junction depth (control leakage) – S/D resistance goes up
mm
100100
1010
0.10.1
0.010.01
nmnm130nm130nm
90nm90nm
70nm70nm
50nm50nm
Gate LengthGate Length65nm65nm
35nm35nm
19701970 19801980 19901990 20002000 20102010 20202020
45nm45nm
32nm32nm
22nm22nm
~30nm~30nm
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(control leakage) S/D resistance goes up
External resistance limits current
/D DS channel extI V R R
Parasitic Capacitance Scaling
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S. Thompson, Materials Today, 2006.
Reality: Overlap + fringe can be 50% of Cchannel in 32nm
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/45nm/32nm Technology Features
EE 141 Technology vs. 45nmFEOL
0.25m featuresLg ~ 240nm248nm lithography
FEOL45nm technologyLg = 35-40nm193nm immersion lithography
No OPC, liberal design rulesSiO2 oxide, 3.5nm
106 dopant atomsLOCOSNobody knew what is ‘strain’Velocity saturatedNo SD leakageNo gate leakage
OPC, restricted design rulesSiO2 oxide, 1.1nm(or Hf-based dielectric)<103 dopant atomsSTIStrained silicon in channelVelocity saturatedIDS,off ~ 100nA/µmIg ~ 10nA/µm2
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One transistor flavorBEOL
Al interconnectSiO2 ILD4-5 M layersNo CMP, no density rules
g
Many transistor flavorsBEOL
Cu interconnectLo-k ILD8-10 M layersCMP, density rules
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Step-and-Scan Lithography
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Lithography Scaling10000100001010
Nominal feature size scaling
mm
10001000
100100
11
0.10.1
nmnm
130nm130nm90nm90nm
65nm65nm
180nm180nm250nm250nm
365nm365nm248nm248nm
193nm193nm
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10100.010.01
19701970 19801980 19901990 20002000 20102010 20202020
45nm45nm32nm32nm
22nm22nm EUV 13nmEUV 13nm
EUV – Technology of the future (forever)?
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Sub-Wavelength Lithography
Light projected through a gap
193nm light
Mask
193nm light
Lightintensity
Lightintensity
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Sub-Wavelength Lithography
1CD k
NA
Decrease Presently: 193 nm (ArF excimer laser)(Distant?) future: EUV
Increase NA = nsinαMaximum n is 1 in airPresently: ~0 92-1 35
min 1
1930.25 50
0 92nm
CD k nmNA
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Presently: 0.92-1.35Immersion
Result: Shrinking k1Presently: 0.35 – 0.4Theoretical limit: 0.25
0.92NA
45nm technology beyond resolution limit
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Litho: How to Enhance Resolution?
Immersion
Off-axis illumination
Optical proximity correction
Phase-shifting masks
Double patterning
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Litho: Immersion
Project through a drop of liquid
nwater = 1.47 min 1
1930.25 35
1 35nm
CD k nmNAmin 1 1.35NA
26IBM
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Litho: Illumination
Regular Illumination
Many off-axis designs (OAI)
Annular
Quadrupole / Quasar or
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Amplifies certain pitches/rotations at expense of others
Dipole +
A.Kahng, ICCAD’03
Litho: Resolution Enhancement
28J.Hartmann, ISSCC’07
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OPC
Optical Proximity Correction (OPC)Correction (OPC)modifies layout to compensate for process distortions
Add non-electrical structures to layout to control diffraction of light
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Rule-based (past) or model-based
A.Kahng, ICCAD’03
OPC: Mask Implications
OPC Fracture
Design Mask
Mask Cost Data Volume
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OPC, PSM, Fill increased feature complexity increased mask cost
A.Kahng, ICCAD’03
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Restricted Design Rules
31J.Hartmann, ISSCC’07
Also: note poly density rules
Litho: Phase-Shift Masks
Phase Shifting Masks (PSM)Creates interference fringes on the wafer Interference effects gboost contrast Phase Masks can make extremely small lines
conventional maskglass Chrome
phase shifting mask
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Electric field at mask
Intensity at wafer
Phase shifter
A.Kahng, ICCAD’03
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Litho: Current Options (22nm)
Immersion lithographyUse high index (NA ~ 1.6-1.7, k1 < 0.3)
Double patterningNA ~ 1.2-1.35
EUV lithography (?) = 13.5nm
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Litho: Double Patterning
Double exposure double etchDouble exposure double etch
Pitch split
Double exposure single etchDipole decomposition (DDL)
Pack-unpack for contact
Resist freeze technology
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Sidewall image transfer (SIT)
From Colburn, VLSI Technology 2008 Workshop
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Double-Exposure Double-EtchStarting layout Line + cut split Cut over line
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Result:SRAM image from K. Mistry, IEDM’07
Pitch Split Double ExposureStarting layout Split pattern Overlay
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With overlay misalignment
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32nm Examples
Single exposure Double exposure
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IEDM’08
Litho: Design Implications
Forbidden directionsDepends on illumination type
Poly lines in other directions can exist but need to be thicker
Forbidden pitchesNulls in the interference pattern
Forbidden shapes in PSM
Assist features
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Assist featuresIf a transistor doesn’t have a neighbor, let’s add a dummy
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Next Lecture
Technology features
Transistor models
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