EE241
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UC Berkeley EE241 B. Nikoli c
EE241 - Spring 2000Advanced Digital Integrated Circuits
Lecture 15
Adiabatic CircuitsArithmetic Circuits
UC Berkeley EE241 B. Nikoli c
Announcements
l Midterm project reports due Today 5pml Homework #3 this weekl Tomorrow CAD seminar – 5-6pm in
Hogan: Prof. Horowitz
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UC Berkeley EE241 B. Nikoli c
Adiabatic CircuitsR
Ctr
E = (RC/tr)CV2 (for tr >> RC)
Applying slow input slopes reduces E below CV2
Useful for driving large capacitors (Buffers)Power reduction > 4 for pad drivers (1 MHz) ISI
ADIABATIC CHARGING
UC Berkeley EE241 B. Nikoli c
Adiabatic Computing
Basic ConceptsWhen charging a capacitor through RC-network with a slowly changing ramp, power dissipation is reduced by reducing the slope of the ramp.No switch should ever be enabled when a voltage is over itMake sure every node is reset to the original stage before performing the next operation!“reversible computing”-> take energy back to the source-> ensure that state is known
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UC Berkeley EE241 B. Nikoli c
Adiabatic Computing
l Principles of storing and erasing information:» Energy dissipation of the combinational logic can be made
arbitrarily small by operation the circuit slowly enough» Information can be loaded into memory circuits dissipating
only arbitrarily small energy» Information can be copied with arbitrarily small energy» Erasing the last copy of a piece of information dissipates an
irreducible finite amount of energy.
Koller, Athas, PhysComp’92, Landauer, IBM J. ResDev’61
UC Berkeley EE241 B. Nikoli c
Six-Phase Charge Transfer
Watkins, JSSC 12/67
One-bit delay
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UC Berkeley EE241 B. Nikoli c
Split-Level Charge Recovery
Younis, Knight, IWLPD’94
UC Berkeley EE241 B. Nikoli c
Adiabatic Circuits
A B C
φ0
φ1
φ2
from Athas
Holding the inputs for the each stageuntil the output energy has been returned
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UC Berkeley EE241 B. Nikoli c
Reversible Pipelines
In
OutLogic
return logic
clkC
Make return path different
Problem: always results in CVth2/2 loss!
UC Berkeley EE241 B. Nikoli c
Reversible Pipelines
holdresetφ0
φ1
φ2
φ3
di
di-1
di+1
φi
retrun
din
φ1 φ3
φ0 φ2
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UC Berkeley EE241 B. Nikoli c
Partially Erasable Latches
Pck
M1F1 F1
M2
M3 M4
V
0
Output stays at Vth
Stored energy is½ CVth
2, vs. ½ CV2
How to use this?
UC Berkeley EE241 B. Nikoli c
Partially Erasable Latches
Pck
M1F1 F1
M2
M3 M4M5 M6F0 F0
Denker, ISLPED’94
Pck
Pck1
Pck
Pck1
Requires 4-clocks for interfacing
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UC Berkeley EE241 B. Nikoli c
Single Pck + Auxiliary ClockPck
M1F1 F1
M 2
M3 M4
M5 M6
M8M7F0 F0
CXCX
2 41 2..
µµ
2 41 2..
µµ
2 41 2..
µµ
2 41 2..
µµ
2 412..
µµ
2 41 2..
µµ
2 41 2..
µµ
2 41 2..
µµ
1
0
0
1 1 0
PckCX
F0
F1A B
Maksimovic et al,ISLPED’97
UC Berkeley EE241 B. Nikoli c
Clock Generation
Logi
c
VDD 2 Clk QR
C
PckL
VG
01 fc
Clk
÷ 2Q
Q
Stage1
Stage2
Stagen
L
VB
Q
F0
F0
F1
F1
Pck
Ck
CX
CX
Clk
F0 F2
F2
Fn
Fn
F1 F1 F2 Fn−1
7201 2
µµ.
Enable
Principle
Implementation
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UC Berkeley EE241 B. Nikoli c
Single Pck + Reference Voltages
Kim, Papaefthymiou, ISLPED’98
UC Berkeley EE241 B. Nikoli c
Cascading Gates
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UC Berkeley EE241 B. Nikoli c
Adiabatic µP
Athas, et al, JSSC 12/97
UC Berkeley EE241 B. Nikoli c
Adiabatic µP
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UC Berkeley EE241 B. Nikoli c
E-R LatchW/ dynamic logic
W/ PTL
UC Berkeley EE241 B. Nikoli c
Advanced Arithmetic Circuits
Adders, Multipliers
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UC Berkeley EE241 B. Nikoli c
Resources
l Prof. Oklobdzija’s notes:http://www.ece.ucdavis.edu/courses/F99/EEC280/Arith-Chapter-v6.PDF
l Selected journal publicationsl Books:
» K. Hwang, "Computer Arithmetic : Principles, Architecture and Design", John Wiley and Sons, 1979.
» E. E. Swartzlander, “Computer Arithmetic ” Vol. 1 & 2, IEEE Computer Society Press, 1990.
» S.Waser, M.Flynn, “Introduction to Arithmetic for Digital Systems Designers”, Holt, Rinehart and Winston 1982.
» I. Koren, Computer Arithmetic Algorithms,” Brookside 1998.» B. Parhami, “Computer Arithmetic,” Oxford 2000.
UC Berkeley EE241 B. Nikoli c
Full-Adder
A B
Cout
Sum
Cin Fulladder
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UC Berkeley EE241 B. Nikoli c
The Binary Adder
S A B Ci⊕ ⊕=
A= BCi ABCi ABCi ABCi+ + +
Co AB BCi ACi+ +=
A B
Cout
Sum
Cin Fulladder
UC Berkeley EE241 B. Nikoli c
Full Adder Implementation
Standard CMOS Multiplexer-based
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UC Berkeley EE241 B. Nikoli c
The Ripple-Carry Adder
A0 B0
S0
Co,0Ci ,0
A1 B1
S1
Co,1
A2 B2
S2
Co,2
A3 B3
S3
Co ,3
(= Ci ,1)FA FA FA FA
Worst case delay linear with the number of bits
tadder N 1–( )tcarry tsum+≈
td = O(N)
Goal: Make the fastest possible carry path circuit
UC Berkeley EE241 B. Nikoli c
Complimentary Static CMOS Full Adder
VDD
VDD
VDD
VDD
A B
Ci
S
Co
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
B
A
Ci
A
B
BA
28 Transistors
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UC Berkeley EE241 B. Nikoli c
Inversion PropertyA B
S
CoCi FA
A B
S
CoCi FA
UC Berkeley EE241 B. Nikoli c
Minimize Critical Path by Reducing Inverting Stages
A0 B0
S0
Co,0Ci,0
A1 B1
S1
Co,1
A2 B2
S2
Co,2 Co ,3FA’ FA’ FA’ FA’
A3 B3
S3
Odd CellEven Cell
Exploit Inversion Property
Note: need 2 different types of cells
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UC Berkeley EE241 B. Nikoli c
The better structure: the Mirror Adder
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B C i
C i
B
A
Ci
A
BBA
VDD
SCo
24 transistors
UC Berkeley EE241 B. Nikoli c
Carry-Skip Adder
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mul
tiple
xer
BP=PoP1P2P3
Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.
Bypass
MacSorley, Proc IRE 1/61Lehman, Burla, IRE Trans on Comp, 12/61
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UC Berkeley EE241 B. Nikoli c
Carry-Skip Adder
Setup
CarryPropagation
Sum
Setup
CarryPropagation
Sum
Setup
CarryPropagation
Sum
Setup
CarryPropagation
Sum
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
C i,0
Critical Path
( ) ( ) RCASKIPRCAd tktN
tkt 122
1 −+
−+−=
For N-bit adder with k-bit groups
UC Berkeley EE241 B. Nikoli c
Carry-Skip Adder
( ) SKIPRCAd tN
tkt
−+−= 2
212
Critical path delay with constant groups
N
tp
ripple adder
bypass adder
4..8