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EE415 VLSI Design
COMBINATIONAL LOGIC
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
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EE415 VLSI Design
Overview
Simple complementary MOS gatesConstruction of complex CMOS gatesVLSI cell design methodologyStandard cellsStick diagrams Euler pathDelaysTransistor sizingFan-in and fan-out considerations
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EE415 VLSI Design
Combinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
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EE415 VLSI Design
Static Complementary CMOS
PUN and PDN are dual logic networks
Pull-up network (PUN) and pull-down network (PDN)VDD
F(In1,In2,…InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
……
PMOS transistors only
pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1
NMOS transistors only
pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0
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EE415 VLSI Design
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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EE415 VLSI Design
PMOS Transistors in Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
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EE415 VLSI Design
Threshold Drops
VDD
VDD 0PDN
0 VDD
CL
CL
PUN
VDD
0 VDD - VTn
CL
VDD
VDD
VDD |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
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EE415 VLSI Design
Complementary CMOS Logic Style
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EE415 VLSI Design
Example Gate: NAND
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EE415 VLSI Design
Example Gate: NOR
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EE415 VLSI Design
Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
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EE415 VLSI Design
Constructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
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EE415 VLSI Design
Cell Design
Standard Cells» General purpose logic» Can be synthesized» Same height, varying width
Datapath Cells» For regular, structured designs (arithmetic)» Includes some wiring in the cell» Fixed height and width
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EE415 VLSI Design
Standard Cell Layout Methodology – 1980s
signals
Routingchannel
VDD
GND
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EE415 VLSI Design
Standard Cell Layout Methodology – 1990s
M2
No Routingchannels
VDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
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EE415 VLSI Design
Standard Cells
Cell boundary
N Well
Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objects
Cell height is “12 pitch”
2
Rails ~10
InOut
VDD
GND
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EE415 VLSI Design
Standard Cells
InOut
VDD
GND
In Out
VDD
GND
With silicided diffusion
With minimaldiffusionrouting
OutIn
VDD
M2
M1
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EE415 VLSI Design
Standard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
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EE415 VLSI Design
Stick Diagrams
Contains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
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EE415 VLSI Design
Stick Diagrams
j
VDDX
X
i
GND
AB
C
PUN
PDN
Logic Graph
C
A B
X = C • (A + B)
B
AC
i
j
ABC
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EE415 VLSI Design
A B C
X
VDD
GND
X
CA B
VDD
GND
uninterrupted diffusion strip
Two Versions of C • (A + B)
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EE415 VLSI Design
Consistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each edge is visited once and only once.
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EE415 VLSI Design
OAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
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EE415 VLSI Design
Example: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}
b
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EE415 VLSI Design
Multi-Fingered TransistorsOne finger Two fingers (folded)
Less diffusion capacitance
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EE415 VLSI Design
CMOS Circuit Styles Static complementary CMOS - except during switching,
output connected to either VDD or GND via a low-resistance path» high noise margins
– full rail to rail swing
– VOH and VOL are at VDD and GND, respectively
» low output impedance, high input impedance
» no steady state path between VDD and GND (no static power consumption)
» delay a function of load capacitance and transistor resistance
» comparable rise and fall times
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EE415 VLSI Design
Switch Delay Model
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
NAND2
A
ReqA
A
Rp
A
Rp
A
Rn CL
INV
NOR2
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EE415 VLSI Design
Input Pattern Effects on Delay
Delay is dependent on the pattern of inputs
Low to high transition» both inputs go low
– delay is 0.69 Rp/2 CL
» one input goes low– delay is 0.69 Rp CL
High to low transition» both inputs go high
– delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
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EE415 VLSI Design
Delay Dependence on Input Patterns
-0.5
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400
A=B=10
A=1, B=10
A=1 0, B=1
time [ps]
Vo
ltage
[V]
Input Data
Pattern
Delay
(psec)
A=B=01 67
A=1, B=01 64
A= 01, B=1 61
A=B=10 45
A=1, B=10 80
A= 10, B=1 81
NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF
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EE415 VLSI Design
Transistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
11
4
4
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EE415 VLSI Design
Transistor Sizing a Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
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EE415 VLSI Design
Fan-In Considerations
DCBA
D
C
B
A CL
C3
C2
C1
Distributed RC model (Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.
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EE415 VLSI Design
tp as a Function of Fan-In
tpLH
t p (
pse
c)
fan-in
Gates with a fan-in greater than 4 should be avoided.
0
250
500
750
1000
1250
2 4 6 8 10 12 14 16
tpHL
quadratic
linear
tp
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EE415 VLSI Design
tp as a Function of Fan-Out
2 4 6 8 10 12 14 16
tpNOR2
t p (
pse
c)
eff. fan-out
All gates have the same drive current.
tpNAND2
tpINV
Slope is a function of “driving strength”
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EE415 VLSI Design
Problems with Complementary CMOS
•Gate with N inputs requires 2N transistors•other circuit styles use N+1 transistors
•tp deteriorates with high fan-in•increases total capacitance•series connected transistors slow down gate
•fan-out loads down gate•1 fan-out = 2 gate capacitors (PMOS and NMOS)
FOaFIaFIat p 32
21